arch/sh/kernel/cpu/sh4/probe.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001 - 2006  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18
  19 int __init detect_cpu_and_cache_system(void)
  20 {
  21         unsigned long pvr, prr, cvr;
  22         unsigned long size;
  23
  24         static unsigned long sizes[16] = {
  25                 [1] = (1 << 12),
  26                 [2] = (1 << 13),
  27                 [4] = (1 << 14),
  28                 [8] = (1 << 15),
  29                 [9] = (1 << 16)
  30         };
  31
  32         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
  33         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  34         cvr = (ctrl_inl(CCN_CVR));
  35
  36         /*
  37          * Setup some sane SH-4 defaults for the icache
  38          */
  39         cpu_data->icache.way_incr       = (1 << 13);
  40         cpu_data->icache.entry_shift    = 5;
  41         cpu_data->icache.sets           = 256;
  42         cpu_data->icache.ways           = 1;
  43         cpu_data->icache.linesz         = L1_CACHE_BYTES;
  44
  45         /*
  46          * And again for the dcache ..
  47          */
  48         cpu_data->dcache.way_incr       = (1 << 14);
  49         cpu_data->dcache.entry_shift    = 5;
  50         cpu_data->dcache.sets           = 512;
  51         cpu_data->dcache.ways           = 1;
  52         cpu_data->dcache.linesz         = L1_CACHE_BYTES;
  53
  54         /*
  55          * Setup some generic flags we can probe
  56          * (L2 and DSP detection only work on SH-4A)
  57          */
  58         if (((pvr >> 16) & 0xff) == 0x10) {
  59                 if ((cvr & 0x02000000) == 0)
  60                         cpu_data->flags |= CPU_HAS_L2_CACHE;
  61                 if ((cvr & 0x10000000) == 0)
  62                         cpu_data->flags |= CPU_HAS_DSP;
  63
  64                 cpu_data->flags |= CPU_HAS_LLSC;
  65         }
  66
  67         /* FPU detection works for everyone */
  68         if ((cvr & 0x20000000) == 1)
  69                 cpu_data->flags |= CPU_HAS_FPU;
  70
  71         /* Mask off the upper chip ID */
  72         pvr &= 0xffff;
  73
  74         /*
  75          * Probe the underlying processor version/revision and
  76          * adjust cpu_data setup accordingly.
  77          */
  78         switch (pvr) {
  79         case 0x205:
  80                 cpu_data->type = CPU_SH7750;
  81                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  82                                    CPU_HAS_PERF_COUNTER;
  83                 break;
  84         case 0x206:
  85                 cpu_data->type = CPU_SH7750S;
  86                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  87                                    CPU_HAS_PERF_COUNTER;
  88                 break;
  89         case 0x1100:
  90                 cpu_data->type = CPU_SH7751;
  91                 cpu_data->flags |= CPU_HAS_FPU;
  92                 break;
  93         case 0x2000:
  94                 cpu_data->type = CPU_SH73180;
  95                 cpu_data->icache.ways = 4;
  96                 cpu_data->dcache.ways = 4;
  97                 cpu_data->flags |= CPU_HAS_LLSC;
  98                 break;
  99         case 0x2001:
 100         case 0x2004:
 101                 cpu_data->type = CPU_SH7770;
 102                 cpu_data->icache.ways = 4;
 103                 cpu_data->dcache.ways = 4;
 104
 105                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
 106                 break;
 107         case 0x2006:
 108         case 0x200A:
 109                 if (prr == 0x61)
 110                         cpu_data->type = CPU_SH7781;
 111                 else
 112                         cpu_data->type = CPU_SH7780;
 113
 114                 cpu_data->icache.ways = 4;
 115                 cpu_data->dcache.ways = 4;
 116
 117                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 118                                    CPU_HAS_LLSC;
 119                 break;
 120         case 0x3000:
 121         case 0x3003:
 122         case 0x3009:
 123                 cpu_data->type = CPU_SH7343;
 124                 cpu_data->icache.ways = 4;
 125                 cpu_data->dcache.ways = 4;
 126                 cpu_data->flags |= CPU_HAS_LLSC;
 127                 break;
 128         case 0x3008:
 129                 if (prr == 0xa0) {
 130                         cpu_data->type = CPU_SH7722;
 131                         cpu_data->icache.ways = 4;
 132                         cpu_data->dcache.ways = 4;
 133                         cpu_data->flags |= CPU_HAS_LLSC;
 134                 }
 135                 break;
 136         case 0x8000:
 137                 cpu_data->type = CPU_ST40RA;
 138                 cpu_data->flags |= CPU_HAS_FPU;
 139                 break;
 140         case 0x8100:
 141                 cpu_data->type = CPU_ST40GX1;
 142                 cpu_data->flags |= CPU_HAS_FPU;
 143                 break;
 144         case 0x700:
 145                 cpu_data->type = CPU_SH4_501;
 146                 cpu_data->icache.ways = 2;
 147                 cpu_data->dcache.ways = 2;
 148                 break;
 149         case 0x600:
 150                 cpu_data->type = CPU_SH4_202;
 151                 cpu_data->icache.ways = 2;
 152                 cpu_data->dcache.ways = 2;
 153                 cpu_data->flags |= CPU_HAS_FPU;
 154                 break;
 155         case 0x500 ... 0x501:
 156                 switch (prr) {
 157                 case 0x10:
 158                         cpu_data->type = CPU_SH7750R;
 159                         break;
 160                 case 0x11:
 161                         cpu_data->type = CPU_SH7751R;
 162                         break;
 163                 case 0x50 ... 0x5f:
 164                         cpu_data->type = CPU_SH7760;
 165                         break;
 166                 }
 167
 168                 cpu_data->icache.ways = 2;
 169                 cpu_data->dcache.ways = 2;
 170
 171                 cpu_data->flags |= CPU_HAS_FPU;
 172
 173                 break;
 174         default:
 175                 cpu_data->type = CPU_SH_NONE;
 176                 break;
 177         }
 178
 179 #ifdef CONFIG_SH_DIRECT_MAPPED
 180         cpu_data->icache.ways = 1;
 181         cpu_data->dcache.ways = 1;
 182 #endif
 183
 184 #ifdef CONFIG_CPU_HAS_PTEA
 185         cpu_data->flags |= CPU_HAS_PTEA;
 186 #endif
 187
 188         /*
 189          * On anything that's not a direct-mapped cache, look to the CVR
 190          * for I/D-cache specifics.
 191          */
 192         if (cpu_data->icache.ways > 1) {
 193                 size = sizes[(cvr >> 20) & 0xf];
 194                 cpu_data->icache.way_incr       = (size >> 1);
 195                 cpu_data->icache.sets           = (size >> 6);
 196
 197         }
 198
 199         /* Setup the rest of the I-cache info */
 200         cpu_data->icache.entry_mask = cpu_data->icache.way_incr -
 201                                       cpu_data->icache.linesz;
 202
 203         cpu_data->icache.way_size = cpu_data->icache.sets *
 204                                     cpu_data->icache.linesz;
 205
 206         /* And the rest of the D-cache */
 207         if (cpu_data->dcache.ways > 1) {
 208                 size = sizes[(cvr >> 16) & 0xf];
 209                 cpu_data->dcache.way_incr       = (size >> 1);
 210                 cpu_data->dcache.sets           = (size >> 6);
 211         }
 212
 213         cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -
 214                                       cpu_data->dcache.linesz;
 215
 216         cpu_data->dcache.way_size = cpu_data->dcache.sets *
 217                                     cpu_data->dcache.linesz;
 218
 219         /*
 220          * Setup the L2 cache desc
 221          *
 222          * SH-4A's have an optional PIPT L2.
 223          */
 224         if (cpu_data->flags & CPU_HAS_L2_CACHE) {
 225                 /*
 226                  * Size calculation is much more sensible
 227                  * than it is for the L1.
 228                  *
 229                  * Sizes are 128KB, 258KB, 512KB, and 1MB.
 230                  */
 231                 size = (cvr & 0xf) << 17;
 232
 233                 BUG_ON(!size);
 234
 235                 cpu_data->scache.way_incr       = (1 << 16);
 236                 cpu_data->scache.entry_shift    = 5;
 237                 cpu_data->scache.ways           = 4;
 238                 cpu_data->scache.linesz         = L1_CACHE_BYTES;
 239                 cpu_data->scache.entry_mask     =
 240                         (cpu_data->scache.way_incr - cpu_data->scache.linesz);
 241                 cpu_data->scache.sets           = size /
 242                         (cpu_data->scache.linesz * cpu_data->scache.ways);
 243                 cpu_data->scache.way_size       =
 244                         (cpu_data->scache.sets * cpu_data->scache.linesz);
 245         }
 246
 247         return 0;
 248 }