arch/sh/kernel/cpu/sh2/setup-sh7619.c

   1 /*
   2  * SH7619 Setup
   3  *
   4  *  Copyright (C) 2006  Yoshinori Sato
   5  *  Copyright (C) 2009  Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17
  18 enum {
  19         UNUSED = 0,
  20
  21         /* interrupt sources */
  22         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  23         WDT, EDMAC, CMT0, CMT1,
  24         SCIF0, SCIF1, SCIF2,
  25         HIF_HIFI, HIF_HIFBI,
  26         DMAC0, DMAC1, DMAC2, DMAC3,
  27         SIOF,
  28 };
  29
  30 static struct intc_vect vectors[] __initdata = {
  31         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  32         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  33         INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
  34         INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
  35         INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
  36         INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
  37         INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
  38         INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
  39         INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
  40         INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
  41         INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
  42         INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
  43         INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
  44         INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
  45         INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
  46         INTC_IRQ(SIOF, 108),
  47 };
  48
  49 static struct intc_prio_reg prio_registers[] __initdata = {
  50         { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
  51         { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
  52         { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
  53         { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
  54         { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
  55         { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
  56         { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
  57 };
  58
  59 static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
  60                          NULL, prio_registers, NULL);
  61
  62 static struct plat_sci_port sci_platform_data[] = {
  63         {
  64                 .mapbase        = 0xf8400000,
  65                 .flags          = UPF_BOOT_AUTOCONF,
  66                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  67                 .scbrr_algo_id  = SCBRR_ALGO_2,
  68                 .type           = PORT_SCIF,
  69                 .irqs           = { 88, 88, 88, 88 },
  70         }, {
  71                 .mapbase        = 0xf8410000,
  72                 .flags          = UPF_BOOT_AUTOCONF,
  73                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  74                 .scbrr_algo_id  = SCBRR_ALGO_2,
  75                 .type           = PORT_SCIF,
  76                 .irqs           = { 92, 92, 92, 92 },
  77         }, {
  78                 .mapbase        = 0xf8420000,
  79                 .flags          = UPF_BOOT_AUTOCONF,
  80                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  81                 .scbrr_algo_id  = SCBRR_ALGO_2,
  82                 .type           = PORT_SCIF,
  83                 .irqs           = { 96, 96, 96, 96 },
  84         }, {
  85                 .flags = 0,
  86         }
  87 };
  88
  89 static struct platform_device sci_device = {
  90         .name           = "sh-sci",
  91         .id             = -1,
  92         .dev            = {
  93                 .platform_data  = sci_platform_data,
  94         },
  95 };
  96
  97 static struct resource eth_resources[] = {
  98         [0] = {
  99                 .start = 0xfb000000,
 100                 .end =   0xfb0001c8,
 101                 .flags = IORESOURCE_MEM,
 102         },
 103         [1] = {
 104                 .start = 85,
 105                 .end = 85,
 106                 .flags = IORESOURCE_IRQ,
 107         },
 108 };
 109
 110 static struct platform_device eth_device = {
 111         .name = "sh-eth",
 112         .id     = -1,
 113         .dev = {
 114                 .platform_data = (void *)1,
 115         },
 116         .num_resources = ARRAY_SIZE(eth_resources),
 117         .resource = eth_resources,
 118 };
 119
 120 static struct sh_timer_config cmt0_platform_data = {
 121         .name = "CMT0",
 122         .channel_offset = 0x02,
 123         .timer_bit = 0,
 124         .clk = "peripheral_clk",
 125         .clockevent_rating = 125,
 126         .clocksource_rating = 0, /* disabled due to code generation issues */
 127 };
 128
 129 static struct resource cmt0_resources[] = {
 130         [0] = {
 131                 .name   = "CMT0",
 132                 .start  = 0xf84a0072,
 133                 .end    = 0xf84a0077,
 134                 .flags  = IORESOURCE_MEM,
 135         },
 136         [1] = {
 137                 .start  = 86,
 138                 .flags  = IORESOURCE_IRQ,
 139         },
 140 };
 141
 142 static struct platform_device cmt0_device = {
 143         .name           = "sh_cmt",
 144         .id             = 0,
 145         .dev = {
 146                 .platform_data  = &cmt0_platform_data,
 147         },
 148         .resource       = cmt0_resources,
 149         .num_resources  = ARRAY_SIZE(cmt0_resources),
 150 };
 151
 152 static struct sh_timer_config cmt1_platform_data = {
 153         .name = "CMT1",
 154         .channel_offset = 0x08,
 155         .timer_bit = 1,
 156         .clk = "peripheral_clk",
 157         .clockevent_rating = 125,
 158         .clocksource_rating = 0, /* disabled due to code generation issues */
 159 };
 160
 161 static struct resource cmt1_resources[] = {
 162         [0] = {
 163                 .name   = "CMT1",
 164                 .start  = 0xf84a0078,
 165                 .end    = 0xf84a007d,
 166                 .flags  = IORESOURCE_MEM,
 167         },
 168         [1] = {
 169                 .start  = 87,
 170                 .flags  = IORESOURCE_IRQ,
 171         },
 172 };
 173
 174 static struct platform_device cmt1_device = {
 175         .name           = "sh_cmt",
 176         .id             = 1,
 177         .dev = {
 178                 .platform_data  = &cmt1_platform_data,
 179         },
 180         .resource       = cmt1_resources,
 181         .num_resources  = ARRAY_SIZE(cmt1_resources),
 182 };
 183
 184 static struct platform_device *sh7619_devices[] __initdata = {
 185         &sci_device,
 186         &eth_device,
 187         &cmt0_device,
 188         &cmt1_device,
 189 };
 190
 191 static int __init sh7619_devices_setup(void)
 192 {
 193         return platform_add_devices(sh7619_devices,
 194                                     ARRAY_SIZE(sh7619_devices));
 195 }
 196 __initcall(sh7619_devices_setup);
 197
 198 void __init plat_irq_setup(void)
 199 {
 200         register_intc_controller(&intc_desc);
 201 }
 202
 203 static struct platform_device *sh7619_early_devices[] __initdata = {
 204         &cmt0_device,
 205         &cmt1_device,
 206 };
 207
 208 #define STBCR3 0xf80a0000
 209
 210 void __init plat_early_device_setup(void)
 211 {
 212         /* enable CMT clock */
 213         __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
 214
 215         early_platform_add_devices(sh7619_early_devices,
 216                                    ARRAY_SIZE(sh7619_early_devices));
 217 }