1 #ifndef __MACH_SDK7786_FPGA_H
2 #define __MACH_SDK7786_FPGA_H
5 #include <linux/types.h>
6 #include <linux/bitops.h>
9 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
14 #define INTTESTR 0x040
20 #define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */
21 #define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */
36 #define PCIECR_PCIEMUX1 BIT(15)
37 #define PCIECR_PCIEMUX0 BIT(14)
38 #define PCIECR_PRST4 BIT(12) /* slot 4 card present */
39 #define PCIECR_PRST3 BIT(11) /* slot 3 card present */
40 #define PCIECR_PRST2 BIT(10) /* slot 2 card present */
41 #define PCIECR_PRST1 BIT(9) /* slot 1 card present */
42 #define PCIECR_CLKEN BIT(4) /* oscillator enable */
50 #define LCLASR_FRAMEN BIT(15)
52 #define LCLASR_FPGA_SEL_SHIFT 12
53 #define LCLASR_NAND_SEL_SHIFT 8
54 #define LCLASR_NORB_SEL_SHIFT 4
55 #define LCLASR_NORA_SEL_SHIFT 0
57 #define LCLASR_AREA_MASK 0x7
59 #define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
60 #define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
61 #define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
62 #define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
65 #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
66 #define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */
69 #define PWRCR_SCISEL0 BIT(0)
70 #define PWRCR_SCISEL1 BIT(1)
71 #define PWRCR_SCIEN BIT(2) /* Serial port enable */
72 #define PWRCR_PDWNACK BIT(5) /* Power down acknowledge */
73 #define PWRCR_PDWNREQ BIT(7) /* Power down request */
74 #define PWRCR_INT2 BIT(11) /* INT2 connection to power manager */
75 #define PWRCR_BUPINIT BIT(13) /* DDR backup initialize */
76 #define PWRCR_BKPRST BIT(15) /* Backup power reset */
93 #define IASELR10 0x2a0
94 #define IASELR11 0x2b0
95 #define IASELR12 0x2c0
96 #define IASELR13 0x2d0
97 #define IASELR14 0x2e0
98 #define IASELR15 0x2f0
100 #define IBSELR1 0x310
101 #define IBSELR2 0x320
102 #define IBSELR3 0x330
103 #define IBSELR4 0x340
104 #define IBSELR5 0x350
105 #define IBSELR6 0x360
106 #define IBSELR7 0x370
107 #define IBSELR8 0x380
108 #define IBSELR9 0x390
109 #define IBSELR10 0x3a0
110 #define IBSELR11 0x3b0
111 #define IBSELR12 0x3c0
112 #define IBSELR13 0x3d0
113 #define IBSELR14 0x3e0
114 #define IBSELR15 0x3f0
117 #define USRLCDR 0x420
125 /* arch/sh/boards/mach-sdk7786/fpga.c */
126 extern void __iomem *sdk7786_fpga_base;
127 extern void sdk7786_fpga_init(void);
129 #define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg))
132 * A convenience wrapper from register offset to internal I2C address,
133 * when the FPGA is in I2C slave mode.
135 #define SDK7786_FPGA_I2CADDR(reg) ((reg) >> 3)
137 static inline u16 fpga_read_reg(unsigned int reg)
139 return ioread16(sdk7786_fpga_base + reg);
142 static inline void fpga_write_reg(u16 val, unsigned int reg)
144 iowrite16(val, sdk7786_fpga_base + reg);
147 #endif /* __MACH_SDK7786_FPGA_H */