arch/sh/include/asm/sh7785lcr.h

   1 #ifndef __ASM_SH_RENESAS_SH7785LCR_H
   2 #define __ASM_SH_RENESAS_SH7785LCR_H
   3
   4 /*
   5  * This board has 2 physical memory maps.
   6  * It can be changed with DIP switch(S2-5).
   7  *
   8  * phys address                 | S2-5 = OFF    | S2-5 = ON
   9  * -----------------------------+---------------+---------------
  10  * 0x00000000 - 0x03ffffff(CS0) | NOR Flash     | NOR Flash
  11  * 0x04000000 - 0x05ffffff(CS1) | PLD           | PLD
  12  * 0x06000000 - 0x07ffffff(CS1) | reserved      | I2C
  13  * 0x08000000 - 0x0bffffff(CS2) | USB           | DDR SDRAM
  14  * 0x0c000000 - 0x0fffffff(CS3) | SD            | DDR SDRAM
  15  * 0x10000000 - 0x13ffffff(CS4) | SM107         | SM107
  16  * 0x14000000 - 0x17ffffff(CS5) | I2C           | USB
  17  * 0x18000000 - 0x1bffffff(CS6) | reserved      | SD
  18  * 0x40000000 - 0x5fffffff      | DDR SDRAM     | (cannot use)
  19  *
  20  */
  21
  22 #define NOR_FLASH_ADDR          0x00000000
  23 #define NOR_FLASH_SIZE          0x04000000
  24
  25 #define PLD_BASE_ADDR           0x04000000
  26 #define PLD_PCICR               (PLD_BASE_ADDR + 0x00)
  27 #define PLD_LCD_BK_CONTR        (PLD_BASE_ADDR + 0x02)
  28 #define PLD_LOCALCR             (PLD_BASE_ADDR + 0x04)
  29 #define PLD_POFCR               (PLD_BASE_ADDR + 0x06)
  30 #define PLD_LEDCR               (PLD_BASE_ADDR + 0x08)
  31 #define PLD_SWSR                (PLD_BASE_ADDR + 0x0a)
  32 #define PLD_VERSR               (PLD_BASE_ADDR + 0x0c)
  33 #define PLD_MMSR                (PLD_BASE_ADDR + 0x0e)
  34
  35 #define SM107_MEM_ADDR          0x10000000
  36 #define SM107_MEM_SIZE          0x00e00000
  37 #define SM107_REG_ADDR          0x13e00000
  38 #define SM107_REG_SIZE          0x00200000
  39
  40 #if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
  41 #define R8A66597_ADDR           0x14000000      /* USB */
  42 #define CG200_ADDR              0x18000000      /* SD */
  43 #define PCA9564_ADDR            0x06000000      /* I2C */
  44 #else
  45 #define R8A66597_ADDR           0x08000000
  46 #define CG200_ADDR              0x0c000000
  47 #define PCA9564_ADDR            0x14000000
  48 #endif
  49
  50 #define R8A66597_SIZE           0x00000100
  51 #define CG200_SIZE              0x00010000
  52 #define PCA9564_SIZE            0x00000100
  53
  54 #endif  /* __ASM_SH_RENESAS_SH7785LCR_H */
  55