arch/s390/include/asm/system.h

   1 /*
   2  * Copyright IBM Corp. 1999, 2009
   3  *
   4  * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
   5  */
   6
   7 #ifndef __ASM_SYSTEM_H
   8 #define __ASM_SYSTEM_H
   9
  10 #include <linux/kernel.h>
  11 #include <linux/errno.h>
  12 #include <asm/types.h>
  13 #include <asm/ptrace.h>
  14 #include <asm/setup.h>
  15 #include <asm/processor.h>
  16 #include <asm/lowcore.h>
  17
  18 #ifdef __KERNEL__
  19
  20 struct task_struct;
  21
  22 extern struct task_struct *__switch_to(void *, void *);
  23
  24 static inline void save_fp_regs(s390_fp_regs *fpregs)
  25 {
  26         asm volatile(
  27                 "       std     0,%O0+8(%R0)\n"
  28                 "       std     2,%O0+24(%R0)\n"
  29                 "       std     4,%O0+40(%R0)\n"
  30                 "       std     6,%O0+56(%R0)"
  31                 : "=Q" (*fpregs) : "Q" (*fpregs));
  32         if (!MACHINE_HAS_IEEE)
  33                 return;
  34         asm volatile(
  35                 "       stfpc   %0\n"
  36                 "       std     1,%O0+16(%R0)\n"
  37                 "       std     3,%O0+32(%R0)\n"
  38                 "       std     5,%O0+48(%R0)\n"
  39                 "       std     7,%O0+64(%R0)\n"
  40                 "       std     8,%O0+72(%R0)\n"
  41                 "       std     9,%O0+80(%R0)\n"
  42                 "       std     10,%O0+88(%R0)\n"
  43                 "       std     11,%O0+96(%R0)\n"
  44                 "       std     12,%O0+104(%R0)\n"
  45                 "       std     13,%O0+112(%R0)\n"
  46                 "       std     14,%O0+120(%R0)\n"
  47                 "       std     15,%O0+128(%R0)\n"
  48                 : "=Q" (*fpregs) : "Q" (*fpregs));
  49 }
  50
  51 static inline void restore_fp_regs(s390_fp_regs *fpregs)
  52 {
  53         asm volatile(
  54                 "       ld      0,%O0+8(%R0)\n"
  55                 "       ld      2,%O0+24(%R0)\n"
  56                 "       ld      4,%O0+40(%R0)\n"
  57                 "       ld      6,%O0+56(%R0)"
  58                 : : "Q" (*fpregs));
  59         if (!MACHINE_HAS_IEEE)
  60                 return;
  61         asm volatile(
  62                 "       lfpc    %0\n"
  63                 "       ld      1,%O0+16(%R0)\n"
  64                 "       ld      3,%O0+32(%R0)\n"
  65                 "       ld      5,%O0+48(%R0)\n"
  66                 "       ld      7,%O0+64(%R0)\n"
  67                 "       ld      8,%O0+72(%R0)\n"
  68                 "       ld      9,%O0+80(%R0)\n"
  69                 "       ld      10,%O0+88(%R0)\n"
  70                 "       ld      11,%O0+96(%R0)\n"
  71                 "       ld      12,%O0+104(%R0)\n"
  72                 "       ld      13,%O0+112(%R0)\n"
  73                 "       ld      14,%O0+120(%R0)\n"
  74                 "       ld      15,%O0+128(%R0)\n"
  75                 : : "Q" (*fpregs));
  76 }
  77
  78 static inline void save_access_regs(unsigned int *acrs)
  79 {
  80         asm volatile("stam 0,15,%0" : "=Q" (*acrs));
  81 }
  82
  83 static inline void restore_access_regs(unsigned int *acrs)
  84 {
  85         asm volatile("lam 0,15,%0" : : "Q" (*acrs));
  86 }
  87
  88 #define switch_to(prev,next,last) do {                                       \
  89         if (prev == next)                                                    \
  90                 break;                                                       \
  91         save_fp_regs(&prev->thread.fp_regs);                                 \
  92         restore_fp_regs(&next->thread.fp_regs);                              \
  93         save_access_regs(&prev->thread.acrs[0]);                             \
  94         restore_access_regs(&next->thread.acrs[0]);                          \
  95         prev = __switch_to(prev,next);                                       \
  96 } while (0)
  97
  98 extern void account_vtime(struct task_struct *, struct task_struct *);
  99 extern void account_tick_vtime(struct task_struct *);
 100
 101 #ifdef CONFIG_PFAULT
 102 extern void pfault_irq_init(void);
 103 extern int pfault_init(void);
 104 extern void pfault_fini(void);
 105 #else /* CONFIG_PFAULT */
 106 #define pfault_irq_init()       do { } while (0)
 107 #define pfault_init()           ({-1;})
 108 #define pfault_fini()           do { } while (0)
 109 #endif /* CONFIG_PFAULT */
 110
 111 extern void cmma_init(void);
 112 extern int memcpy_real(void *, void *, size_t);
 113
 114 #define finish_arch_switch(prev) do {                                        \
 115         set_fs(current->thread.mm_segment);                                  \
 116         account_vtime(prev, current);                                        \
 117 } while (0)
 118
 119 #define nop() asm volatile("nop")
 120
 121 #define xchg(ptr,x)                                                       \
 122 ({                                                                        \
 123         __typeof__(*(ptr)) __ret;                                         \
 124         __ret = (__typeof__(*(ptr)))                                      \
 125                 __xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \
 126         __ret;                                                            \
 127 })
 128
 129 extern void __xchg_called_with_bad_pointer(void);
 130
 131 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
 132 {
 133         unsigned long addr, old;
 134         int shift;
 135
 136         switch (size) {
 137         case 1:
 138                 addr = (unsigned long) ptr;
 139                 shift = (3 ^ (addr & 3)) << 3;
 140                 addr ^= addr & 3;
 141                 asm volatile(
 142                         "       l       %0,%4\n"
 143                         "0:     lr      0,%0\n"
 144                         "       nr      0,%3\n"
 145                         "       or      0,%2\n"
 146                         "       cs      %0,0,%4\n"
 147                         "       jl      0b\n"
 148                         : "=&d" (old), "=Q" (*(int *) addr)
 149                         : "d" (x << shift), "d" (~(255 << shift)),
 150                           "Q" (*(int *) addr) : "memory", "cc", "0");
 151                 return old >> shift;
 152         case 2:
 153                 addr = (unsigned long) ptr;
 154                 shift = (2 ^ (addr & 2)) << 3;
 155                 addr ^= addr & 2;
 156                 asm volatile(
 157                         "       l       %0,%4\n"
 158                         "0:     lr      0,%0\n"
 159                         "       nr      0,%3\n"
 160                         "       or      0,%2\n"
 161                         "       cs      %0,0,%4\n"
 162                         "       jl      0b\n"
 163                         : "=&d" (old), "=Q" (*(int *) addr)
 164                         : "d" (x << shift), "d" (~(65535 << shift)),
 165                           "Q" (*(int *) addr) : "memory", "cc", "0");
 166                 return old >> shift;
 167         case 4:
 168                 asm volatile(
 169                         "       l       %0,%3\n"
 170                         "0:     cs      %0,%2,%3\n"
 171                         "       jl      0b\n"
 172                         : "=&d" (old), "=Q" (*(int *) ptr)
 173                         : "d" (x), "Q" (*(int *) ptr)
 174                         : "memory", "cc");
 175                 return old;
 176 #ifdef __s390x__
 177         case 8:
 178                 asm volatile(
 179                         "       lg      %0,%3\n"
 180                         "0:     csg     %0,%2,%3\n"
 181                         "       jl      0b\n"
 182                         : "=&d" (old), "=m" (*(long *) ptr)
 183                         : "d" (x), "Q" (*(long *) ptr)
 184                         : "memory", "cc");
 185                 return old;
 186 #endif /* __s390x__ */
 187         }
 188         __xchg_called_with_bad_pointer();
 189         return x;
 190 }
 191
 192 /*
 193  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 194  * store NEW in MEM.  Return the initial value in MEM.  Success is
 195  * indicated by comparing RETURN with OLD.
 196  */
 197
 198 #define __HAVE_ARCH_CMPXCHG 1
 199
 200 #define cmpxchg(ptr, o, n)                                              \
 201         ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),       \
 202                                         (unsigned long)(n), sizeof(*(ptr))))
 203
 204 extern void __cmpxchg_called_with_bad_pointer(void);
 205
 206 static inline unsigned long
 207 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 208 {
 209         unsigned long addr, prev, tmp;
 210         int shift;
 211
 212         switch (size) {
 213         case 1:
 214                 addr = (unsigned long) ptr;
 215                 shift = (3 ^ (addr & 3)) << 3;
 216                 addr ^= addr & 3;
 217                 asm volatile(
 218                         "       l       %0,%2\n"
 219                         "0:     nr      %0,%5\n"
 220                         "       lr      %1,%0\n"
 221                         "       or      %0,%3\n"
 222                         "       or      %1,%4\n"
 223                         "       cs      %0,%1,%2\n"
 224                         "       jnl     1f\n"
 225                         "       xr      %1,%0\n"
 226                         "       nr      %1,%5\n"
 227                         "       jnz     0b\n"
 228                         "1:"
 229                         : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
 230                         : "d" (old << shift), "d" (new << shift),
 231                           "d" (~(255 << shift)), "Q" (*(int *) ptr)
 232                         : "memory", "cc");
 233                 return prev >> shift;
 234         case 2:
 235                 addr = (unsigned long) ptr;
 236                 shift = (2 ^ (addr & 2)) << 3;
 237                 addr ^= addr & 2;
 238                 asm volatile(
 239                         "       l       %0,%2\n"
 240                         "0:     nr      %0,%5\n"
 241                         "       lr      %1,%0\n"
 242                         "       or      %0,%3\n"
 243                         "       or      %1,%4\n"
 244                         "       cs      %0,%1,%2\n"
 245                         "       jnl     1f\n"
 246                         "       xr      %1,%0\n"
 247                         "       nr      %1,%5\n"
 248                         "       jnz     0b\n"
 249                         "1:"
 250                         : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
 251                         : "d" (old << shift), "d" (new << shift),
 252                           "d" (~(65535 << shift)), "Q" (*(int *) ptr)
 253                         : "memory", "cc");
 254                 return prev >> shift;
 255         case 4:
 256                 asm volatile(
 257                         "       cs      %0,%3,%1\n"
 258                         : "=&d" (prev), "=Q" (*(int *) ptr)
 259                         : "0" (old), "d" (new), "Q" (*(int *) ptr)
 260                         : "memory", "cc");
 261                 return prev;
 262 #ifdef __s390x__
 263         case 8:
 264                 asm volatile(
 265                         "       csg     %0,%3,%1\n"
 266                         : "=&d" (prev), "=Q" (*(long *) ptr)
 267                         : "0" (old), "d" (new), "Q" (*(long *) ptr)
 268                         : "memory", "cc");
 269                 return prev;
 270 #endif /* __s390x__ */
 271         }
 272         __cmpxchg_called_with_bad_pointer();
 273         return old;
 274 }
 275
 276 /*
 277  * Force strict CPU ordering.
 278  * And yes, this is required on UP too when we're talking
 279  * to devices.
 280  *
 281  * This is very similar to the ppc eieio/sync instruction in that is
 282  * does a checkpoint syncronisation & makes sure that
 283  * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 284  */
 285
 286 #define eieio() asm volatile("bcr 15,0" : : : "memory")
 287 #define SYNC_OTHER_CORES(x)   eieio()
 288 #define mb()    eieio()
 289 #define rmb()   eieio()
 290 #define wmb()   eieio()
 291 #define read_barrier_depends() do { } while(0)
 292 #define smp_mb()       mb()
 293 #define smp_rmb()      rmb()
 294 #define smp_wmb()      wmb()
 295 #define smp_read_barrier_depends()    read_barrier_depends()
 296 #define smp_mb__before_clear_bit()     smp_mb()
 297 #define smp_mb__after_clear_bit()      smp_mb()
 298
 299
 300 #define set_mb(var, value)      do { var = value; mb(); } while (0)
 301
 302 #ifdef __s390x__
 303
 304 #define __ctl_load(array, low, high) ({                         \
 305         typedef struct { char _[sizeof(array)]; } addrtype;     \
 306         asm volatile(                                           \
 307                 "       lctlg   %1,%2,%0\n"                     \
 308                 : : "Q" (*(addrtype *)(&array)),                \
 309                     "i" (low), "i" (high));                     \
 310         })
 311
 312 #define __ctl_store(array, low, high) ({                        \
 313         typedef struct { char _[sizeof(array)]; } addrtype;     \
 314         asm volatile(                                           \
 315                 "       stctg   %1,%2,%0\n"                     \
 316                 : "=Q" (*(addrtype *)(&array))                  \
 317                 : "i" (low), "i" (high));                       \
 318         })
 319
 320 #else /* __s390x__ */
 321
 322 #define __ctl_load(array, low, high) ({                         \
 323         typedef struct { char _[sizeof(array)]; } addrtype;     \
 324         asm volatile(                                           \
 325                 "       lctl    %1,%2,%0\n"                     \
 326                 : : "Q" (*(addrtype *)(&array)),                \
 327                     "i" (low), "i" (high));                     \
 328 })
 329
 330 #define __ctl_store(array, low, high) ({                        \
 331         typedef struct { char _[sizeof(array)]; } addrtype;     \
 332         asm volatile(                                           \
 333                 "       stctl   %1,%2,%0\n"                     \
 334                 : "=Q" (*(addrtype *)(&array))                  \
 335                 : "i" (low), "i" (high));                       \
 336         })
 337
 338 #endif /* __s390x__ */
 339
 340 #define __ctl_set_bit(cr, bit) ({       \
 341         unsigned long __dummy;          \
 342         __ctl_store(__dummy, cr, cr);   \
 343         __dummy |= 1UL << (bit);        \
 344         __ctl_load(__dummy, cr, cr);    \
 345 })
 346
 347 #define __ctl_clear_bit(cr, bit) ({     \
 348         unsigned long __dummy;          \
 349         __ctl_store(__dummy, cr, cr);   \
 350         __dummy &= ~(1UL << (bit));     \
 351         __ctl_load(__dummy, cr, cr);    \
 352 })
 353
 354 #include <linux/irqflags.h>
 355
 356 #include <asm-generic/cmpxchg-local.h>
 357
 358 static inline unsigned long __cmpxchg_local(volatile void *ptr,
 359                                       unsigned long old,
 360                                       unsigned long new, int size)
 361 {
 362         switch (size) {
 363         case 1:
 364         case 2:
 365         case 4:
 366 #ifdef __s390x__
 367         case 8:
 368 #endif
 369                 return __cmpxchg(ptr, old, new, size);
 370         default:
 371                 return __cmpxchg_local_generic(ptr, old, new, size);
 372         }
 373
 374         return old;
 375 }
 376
 377 /*
 378  * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 379  * them available.
 380  */
 381 #define cmpxchg_local(ptr, o, n)                                        \
 382         ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
 383                         (unsigned long)(n), sizeof(*(ptr))))
 384 #ifdef __s390x__
 385 #define cmpxchg64_local(ptr, o, n)                                      \
 386   ({                                                                    \
 387         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 388         cmpxchg_local((ptr), (o), (n));                                 \
 389   })
 390 #else
 391 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 392 #endif
 393
 394 /*
 395  * Use to set psw mask except for the first byte which
 396  * won't be changed by this function.
 397  */
 398 static inline void
 399 __set_psw_mask(unsigned long mask)
 400 {
 401         __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
 402 }
 403
 404 #define local_mcck_enable()  __set_psw_mask(psw_kernel_bits)
 405 #define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)
 406
 407 #ifdef CONFIG_SMP
 408
 409 extern void smp_ctl_set_bit(int cr, int bit);
 410 extern void smp_ctl_clear_bit(int cr, int bit);
 411 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
 412 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
 413
 414 #else
 415
 416 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
 417 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
 418
 419 #endif /* CONFIG_SMP */
 420
 421 static inline unsigned int stfl(void)
 422 {
 423         asm volatile(
 424                 "       .insn   s,0xb2b10000,0(0)\n" /* stfl */
 425                 "0:\n"
 426                 EX_TABLE(0b,0b));
 427         return S390_lowcore.stfl_fac_list;
 428 }
 429
 430 static inline int __stfle(unsigned long long *list, int doublewords)
 431 {
 432         typedef struct { unsigned long long _[doublewords]; } addrtype;
 433         register unsigned long __nr asm("0") = doublewords - 1;
 434
 435         asm volatile(".insn s,0xb2b00000,%0" /* stfle */
 436                      : "=m" (*(addrtype *) list), "+d" (__nr) : : "cc");
 437         return __nr + 1;
 438 }
 439
 440 static inline int stfle(unsigned long long *list, int doublewords)
 441 {
 442         if (!(stfl() & (1UL << 24)))
 443                 return -EOPNOTSUPP;
 444         return __stfle(list, doublewords);
 445 }
 446
 447 static inline unsigned short stap(void)
 448 {
 449         unsigned short cpu_address;
 450
 451         asm volatile("stap %0" : "=m" (cpu_address));
 452         return cpu_address;
 453 }
 454
 455 extern void (*_machine_restart)(char *command);
 456 extern void (*_machine_halt)(void);
 457 extern void (*_machine_power_off)(void);
 458
 459 #define arch_align_stack(x) (x)
 460
 461 static inline int tprot(unsigned long addr)
 462 {
 463         int rc = -EFAULT;
 464
 465         asm volatile(
 466                 "       tprot   0(%1),0\n"
 467                 "0:     ipm     %0\n"
 468                 "       srl     %0,28\n"
 469                 "1:\n"
 470                 EX_TABLE(0b,1b)
 471                 : "+d" (rc) : "a" (addr) : "cc");
 472         return rc;
 473 }
 474
 475 #endif /* __KERNEL__ */
 476
 477 #endif