arch/ppc/platforms/lopec.c

   1 /*
   2  * Setup routines for the Motorola LoPEC.
   3  *
   4  * Author: Dan Cox
   5  * Maintainer: Tom Rini <trini@kernel.crashing.org>
   6  *
   7  * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/delay.h>
  15 #include <linux/pci_ids.h>
  16 #include <linux/ioport.h>
  17 #include <linux/init.h>
  18 #include <linux/ide.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/initrd.h>
  21 #include <linux/console.h>
  22 #include <linux/root_dev.h>
  23 #include <linux/pci.h>
  24
  25 #include <asm/machdep.h>
  26 #include <asm/pci-bridge.h>
  27 #include <asm/io.h>
  28 #include <asm/open_pic.h>
  29 #include <asm/i8259.h>
  30 #include <asm/todc.h>
  31 #include <asm/bootinfo.h>
  32 #include <asm/mpc10x.h>
  33 #include <asm/hw_irq.h>
  34 #include <asm/prep_nvram.h>
  35 #include <asm/kgdb.h>
  36
  37 /*
  38  * Define all of the IRQ senses and polarities.  Taken from the
  39  * LoPEC Programmer's Reference Guide.
  40  */
  41 static u_char lopec_openpic_initsenses[16] __initdata = {
  42         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 0 */
  43         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 1 */
  44         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 2 */
  45         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 3 */
  46         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 4 */
  47         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 5 */
  48         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 6 */
  49         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 7 */
  50         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 8 */
  51         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 9 */
  52         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 10 */
  53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 11 */
  54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ 12 */
  55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ 13 */
  56         (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),       /* IRQ 14 */
  57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)       /* IRQ 15 */
  58 };
  59
  60 static inline int __init
  61 lopec_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  62 {
  63         int irq;
  64         static char pci_irq_table[][4] = {
  65                 {16, 0, 0, 0}, /* ID 11 - Winbond */
  66                 {22, 0, 0, 0}, /* ID 12 - SCSI */
  67                 {0, 0, 0, 0}, /* ID 13 - nothing */
  68                 {17, 0, 0, 0}, /* ID 14 - 82559 Ethernet */
  69                 {27, 0, 0, 0}, /* ID 15 - USB */
  70                 {23, 0, 0, 0}, /* ID 16 - PMC slot 1 */
  71                 {24, 0, 0, 0}, /* ID 17 - PMC slot 2 */
  72                 {25, 0, 0, 0}, /* ID 18 - PCI slot */
  73                 {0, 0, 0, 0}, /* ID 19 - nothing */
  74                 {0, 0, 0, 0}, /* ID 20 - nothing */
  75                 {0, 0, 0, 0}, /* ID 21 - nothing */
  76                 {0, 0, 0, 0}, /* ID 22 - nothing */
  77                 {0, 0, 0, 0}, /* ID 23 - nothing */
  78                 {0, 0, 0, 0}, /* ID 24 - PMC slot 1b */
  79                 {0, 0, 0, 0}, /* ID 25 - nothing */
  80                 {0, 0, 0, 0}  /* ID 26 - PMC Slot 2b */
  81         };
  82         const long min_idsel = 11, max_idsel = 26, irqs_per_slot = 4;
  83
  84         irq = PCI_IRQ_TABLE_LOOKUP;
  85         if (!irq)
  86                 return 0;
  87
  88         return irq;
  89 }
  90
  91 static void __init
  92 lopec_setup_winbond_83553(struct pci_controller *hose)
  93 {
  94         int devfn;
  95
  96         devfn = PCI_DEVFN(11,0);
  97
  98         /* IDE interrupt routing (primary 14, secondary 15) */
  99         early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
 100         /* PCI interrupt routing */
 101         early_write_config_word(hose, 0, devfn, 0x44, 0x0000);
 102
 103         /* ISA-PCI address decoder */
 104         early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);
 105
 106         /* RTC, kb, not used in PPC */
 107         early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
 108         early_write_config_byte(hose, 0, devfn, 0x4e, 0x04);
 109         devfn = PCI_DEVFN(11, 1);
 110         early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
 111         early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
 112 }
 113
 114 static void __init
 115 lopec_find_bridges(void)
 116 {
 117         struct pci_controller *hose;
 118
 119         hose = pcibios_alloc_controller();
 120         if (!hose)
 121                 return;
 122
 123         hose->first_busno = 0;
 124         hose->last_busno = 0xff;
 125
 126         if (mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B,
 127                                 MPC10X_MAPB_EUMB_BASE) == 0) {
 128
 129                 hose->mem_resources[0].end = 0xffffffff;
 130                 lopec_setup_winbond_83553(hose);
 131                 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 132                 ppc_md.pci_swizzle = common_swizzle;
 133                 ppc_md.pci_map_irq = lopec_map_irq;
 134         }
 135 }
 136
 137 static int
 138 lopec_show_cpuinfo(struct seq_file *m)
 139 {
 140         seq_printf(m, "machine\t\t: Motorola LoPEC\n");
 141         return 0;
 142 }
 143
 144 static void
 145 lopec_restart(char *cmd)
 146 {
 147 #define LOPEC_SYSSTAT1 0xffe00000
 148         /* force a hard reset, if possible */
 149         unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
 150         reg |= 0x80;
 151         *((unsigned char *) LOPEC_SYSSTAT1) = reg;
 152
 153         local_irq_disable();
 154         while(1);
 155 #undef LOPEC_SYSSTAT1
 156 }
 157
 158 static void
 159 lopec_halt(void)
 160 {
 161         local_irq_disable();
 162         while(1);
 163 }
 164
 165 static void
 166 lopec_power_off(void)
 167 {
 168         lopec_halt();
 169 }
 170
 171 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 172 int lopec_ide_ports_known = 0;
 173 static unsigned long lopec_ide_regbase[MAX_HWIFS];
 174 static unsigned long lopec_ide_ctl_regbase[MAX_HWIFS];
 175 static unsigned long lopec_idedma_regbase;
 176
 177 static void
 178 lopec_ide_probe(void)
 179 {
 180         struct pci_dev *dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
 181                                               PCI_DEVICE_ID_WINBOND_82C105,
 182                                               NULL);
 183         lopec_ide_ports_known = 1;
 184
 185         if (dev) {
 186                 lopec_ide_regbase[0] = dev->resource[0].start;
 187                 lopec_ide_regbase[1] = dev->resource[2].start;
 188                 lopec_ide_ctl_regbase[0] = dev->resource[1].start;
 189                 lopec_ide_ctl_regbase[1] = dev->resource[3].start;
 190                 lopec_idedma_regbase = dev->resource[4].start;
 191                 pci_dev_put(dev);
 192         }
 193 }
 194
 195 static int
 196 lopec_ide_default_irq(unsigned long base)
 197 {
 198         if (lopec_ide_ports_known == 0)
 199                 lopec_ide_probe();
 200
 201         if (base == lopec_ide_regbase[0])
 202                 return 14;
 203         else if (base == lopec_ide_regbase[1])
 204                 return 15;
 205         else
 206                 return 0;
 207 }
 208
 209 static unsigned long
 210 lopec_ide_default_io_base(int index)
 211 {
 212         if (lopec_ide_ports_known == 0)
 213                 lopec_ide_probe();
 214         return lopec_ide_regbase[index];
 215 }
 216
 217 static void __init
 218 lopec_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data,
 219                           unsigned long ctl, int *irq)
 220 {
 221         unsigned long reg = data;
 222         uint alt_status_base;
 223         int i;
 224
 225         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
 226                 hw->io_ports[i] = reg++;
 227
 228         if (data == lopec_ide_regbase[0]) {
 229                 alt_status_base = lopec_ide_ctl_regbase[0] + 2;
 230                 hw->irq = 14;
 231         } else if (data == lopec_ide_regbase[1]) {
 232                 alt_status_base = lopec_ide_ctl_regbase[1] + 2;
 233                 hw->irq = 15;
 234         } else {
 235                 alt_status_base = 0;
 236                 hw->irq = 0;
 237         }
 238
 239         if (ctl)
 240                 hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
 241         else
 242                 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
 243
 244         if (irq != NULL)
 245                 *irq = hw->irq;
 246
 247 }
 248 #endif /* BLK_DEV_IDE */
 249
 250 static void __init
 251 lopec_init_IRQ(void)
 252 {
 253         int i;
 254
 255         /*
 256          * Provide the open_pic code with the correct table of interrupts.
 257          */
 258         OpenPIC_InitSenses = lopec_openpic_initsenses;
 259         OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
 260
 261         mpc10x_set_openpic();
 262
 263         /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
 264         openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
 265                         &i8259_irq);
 266
 267         /*
 268          * The EPIC allows for a read in the range of 0xFEF00000 ->
 269          * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
 270          */
 271         i8259_init(0xfef00000, 0);
 272 }
 273
 274 static int __init
 275 lopec_request_io(void)
 276 {
 277         outb(0x00, 0x4d0);
 278         outb(0xc0, 0x4d1);
 279
 280         request_region(0x00, 0x20, "dma1");
 281         request_region(0x20, 0x20, "pic1");
 282         request_region(0x40, 0x20, "timer");
 283         request_region(0x80, 0x10, "dma page reg");
 284         request_region(0xa0, 0x20, "pic2");
 285         request_region(0xc0, 0x20, "dma2");
 286
 287         return 0;
 288 }
 289
 290 device_initcall(lopec_request_io);
 291
 292 static void __init
 293 lopec_map_io(void)
 294 {
 295         io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
 296         io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
 297 }
 298
 299 /*
 300  * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
 301  */
 302 static __inline__ void
 303 lopec_set_bat(void)
 304 {
 305         mb();
 306         mtspr(SPRN_DBAT1U, 0xf8000ffe);
 307         mtspr(SPRN_DBAT1L, 0xf800002a);
 308         mb();
 309 }
 310
 311 TODC_ALLOC();
 312
 313 static void __init
 314 lopec_setup_arch(void)
 315 {
 316
 317         TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
 318                   ioremap(0xffe80000, 0x8000), 8);
 319
 320         loops_per_jiffy = 100000000/HZ;
 321
 322         lopec_find_bridges();
 323
 324 #ifdef CONFIG_BLK_DEV_INITRD
 325         if (initrd_start)
 326                 ROOT_DEV = Root_RAM0;
 327         else
 328 #elif defined(CONFIG_ROOT_NFS)
 329                 ROOT_DEV = Root_NFS;
 330 #elif defined(CONFIG_BLK_DEV_IDEDISK)
 331                 ROOT_DEV = Root_HDA1;
 332 #else
 333                 ROOT_DEV = Root_SDA1;
 334 #endif
 335
 336 #ifdef CONFIG_PPCBUG_NVRAM
 337         /* Read in NVRAM data */
 338         init_prep_nvram();
 339
 340         /* if no bootargs, look in NVRAM */
 341         if ( cmd_line[0] == '\0' ) {
 342                 char *bootargs;
 343                  bootargs = prep_nvram_get_var("bootargs");
 344                  if (bootargs != NULL) {
 345                          strcpy(cmd_line, bootargs);
 346                          /* again.. */
 347                          strcpy(saved_command_line, cmd_line);
 348                 }
 349         }
 350 #endif
 351 }
 352
 353 void __init
 354 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 355               unsigned long r6, unsigned long r7)
 356 {
 357         parse_bootinfo(find_bootinfo());
 358         lopec_set_bat();
 359
 360         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 361         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 362         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 363         ISA_DMA_THRESHOLD = 0x00ffffff;
 364         DMA_MODE_READ = 0x44;
 365         DMA_MODE_WRITE = 0x48;
 366         ppc_do_canonicalize_irqs = 1;
 367
 368         ppc_md.setup_arch = lopec_setup_arch;
 369         ppc_md.show_cpuinfo = lopec_show_cpuinfo;
 370         ppc_md.init_IRQ = lopec_init_IRQ;
 371         ppc_md.get_irq = openpic_get_irq;
 372
 373         ppc_md.restart = lopec_restart;
 374         ppc_md.power_off = lopec_power_off;
 375         ppc_md.halt = lopec_halt;
 376
 377         ppc_md.setup_io_mappings = lopec_map_io;
 378
 379         ppc_md.time_init = todc_time_init;
 380         ppc_md.set_rtc_time = todc_set_rtc_time;
 381         ppc_md.get_rtc_time = todc_get_rtc_time;
 382         ppc_md.calibrate_decr = todc_calibrate_decr;
 383
 384         ppc_md.nvram_read_val = todc_direct_read_val;
 385         ppc_md.nvram_write_val = todc_direct_write_val;
 386
 387 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 388         ppc_ide_md.default_irq = lopec_ide_default_irq;
 389         ppc_ide_md.default_io_base = lopec_ide_default_io_base;
 390         ppc_ide_md.ide_init_hwif = lopec_ide_init_hwif_ports;
 391 #endif
 392 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 393         ppc_md.progress = gen550_progress;
 394 #endif
 395 }