arch/ppc/platforms/4xx/bamboo.c

   1 /*
   2  * Bamboo board specific routines
   3  *
   4  * Wade Farnsworth <wfarnsworth@mvista.com>
   5  * Copyright 2004 MontaVista Software Inc.
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of  the GNU General  Public License as published by the
   9  * Free Software Foundation;  either version 2 of the  License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/stddef.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/reboot.h>
  18 #include <linux/pci.h>
  19 #include <linux/kdev_t.h>
  20 #include <linux/types.h>
  21 #include <linux/major.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/console.h>
  24 #include <linux/delay.h>
  25 #include <linux/ide.h>
  26 #include <linux/initrd.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/tty.h>
  30 #include <linux/serial.h>
  31 #include <linux/serial_core.h>
  32 #include <linux/serial_8250.h>
  33 #include <linux/ethtool.h>
  34
  35 #include <asm/system.h>
  36 #include <asm/pgtable.h>
  37 #include <asm/page.h>
  38 #include <asm/dma.h>
  39 #include <asm/io.h>
  40 #include <asm/machdep.h>
  41 #include <asm/ocp.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/time.h>
  44 #include <asm/todc.h>
  45 #include <asm/bootinfo.h>
  46 #include <asm/ppc4xx_pic.h>
  47 #include <asm/ppcboot.h>
  48
  49 #include <syslib/gen550.h>
  50 #include <syslib/ibm440gx_common.h>
  51
  52 extern bd_t __res;
  53
  54 static struct ibm44x_clocks clocks __initdata;
  55
  56 /*
  57  * Bamboo external IRQ triggering/polarity settings
  58  */
  59 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
  60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
  61         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
  62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
  66         (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
  70 };
  71
  72 static void __init
  73 bamboo_calibrate_decr(void)
  74 {
  75         unsigned int freq;
  76
  77         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  78                 freq = BAMBOO_TMRCLK;
  79         else
  80                 freq = clocks.cpu;
  81
  82         ibm44x_calibrate_decr(freq);
  83
  84 }
  85
  86 static int
  87 bamboo_show_cpuinfo(struct seq_file *m)
  88 {
  89         seq_printf(m, "vendor\t\t: IBM\n");
  90         seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
  91
  92         return 0;
  93 }
  94
  95 static inline int
  96 bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  97 {
  98         static char pci_irq_table[][4] =
  99         /*
 100          *      PCI IDSEL/INTPIN->INTLINE
 101          *         A   B   C   D
 102          */
 103         {
 104                 { 28, 28, 28, 28 },     /* IDSEL 1 - PCI Slot 0 */
 105                 { 27, 27, 27, 27 },     /* IDSEL 2 - PCI Slot 1 */
 106                 { 26, 26, 26, 26 },     /* IDSEL 3 - PCI Slot 2 */
 107                 { 25, 25, 25, 25 },     /* IDSEL 4 - PCI Slot 3 */
 108         };
 109
 110         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 111         return PCI_IRQ_TABLE_LOOKUP;
 112 }
 113
 114 static void __init bamboo_set_emacdata(void)
 115 {
 116         u8 * base_addr;
 117         struct ocp_def *def;
 118         struct ocp_func_emac_data *emacdata;
 119         u8 val;
 120         int mode;
 121         u32 excluded = 0;
 122
 123         base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
 124         val = readb(base_addr);
 125         iounmap((void *) base_addr);
 126         if (BAMBOO_SEL_MII(val))
 127                 mode = PHY_MODE_MII;
 128         else if (BAMBOO_SEL_RMII(val))
 129                 mode = PHY_MODE_RMII;
 130         else
 131                 mode = PHY_MODE_SMII;
 132
 133         /*
 134          * SW2 on the Bamboo is used for ethernet configuration and is accessed
 135          * via the CONFIG2 register in the FPGA.  If the ANEG pin is set,
 136          * overwrite the supported features with the settings in SW2.
 137          *
 138          * This is used as a workaround for the improperly biased RJ-45 sockets
 139          * on the Rev. 0 Bamboo.  By default only 10baseT is functional.
 140          * Removing inductors L17 and L18 from the board allows 100baseT, but
 141          * disables 10baseT.  The Rev. 1 has no such limitations.
 142          */
 143
 144         base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
 145         val = readb(base_addr);
 146         iounmap((void *) base_addr);
 147         if (!BAMBOO_AUTONEGOTIATE(val)) {
 148                 excluded |= SUPPORTED_Autoneg;
 149                 if (BAMBOO_FORCE_100Mbps(val)) {
 150                         excluded |= SUPPORTED_10baseT_Full;
 151                         excluded |= SUPPORTED_10baseT_Half;
 152                         if (BAMBOO_FULL_DUPLEX_EN(val))
 153                                 excluded |= SUPPORTED_100baseT_Half;
 154                         else
 155                                 excluded |= SUPPORTED_100baseT_Full;
 156                 } else {
 157                         excluded |= SUPPORTED_100baseT_Full;
 158                         excluded |= SUPPORTED_100baseT_Half;
 159                         if (BAMBOO_FULL_DUPLEX_EN(val))
 160                                 excluded |= SUPPORTED_10baseT_Half;
 161                         else
 162                                 excluded |= SUPPORTED_10baseT_Full;
 163                 }
 164         }
 165
 166         /* Set mac_addr, phy mode and unsupported phy features for each EMAC */
 167
 168         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 169         emacdata = def->additions;
 170         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 171         emacdata->phy_mode = mode;
 172         emacdata->phy_feat_exc = excluded;
 173
 174         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
 175         emacdata = def->additions;
 176         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 177         emacdata->phy_mode = mode;
 178         emacdata->phy_feat_exc = excluded;
 179 }
 180
 181 static int
 182 bamboo_exclude_device(unsigned char bus, unsigned char devfn)
 183 {
 184         return (bus == 0 && devfn == 0);
 185 }
 186
 187 #define PCI_READW(offset) \
 188         (readw((void *)((u32)pci_reg_base+offset)))
 189
 190 #define PCI_WRITEW(value, offset) \
 191         (writew(value, (void *)((u32)pci_reg_base+offset)))
 192
 193 #define PCI_WRITEL(value, offset) \
 194         (writel(value, (void *)((u32)pci_reg_base+offset)))
 195
 196 static void __init
 197 bamboo_setup_pci(void)
 198 {
 199         void *pci_reg_base;
 200         unsigned long memory_size;
 201         memory_size = ppc_md.find_end_of_memory();
 202
 203         pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
 204
 205         /* Enable PCI I/O, Mem, and Busmaster cycles */
 206         PCI_WRITEW(PCI_READW(PCI_COMMAND) |
 207                    PCI_COMMAND_MEMORY |
 208                    PCI_COMMAND_MASTER, PCI_COMMAND);
 209
 210         /* Disable region first */
 211         PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
 212
 213         /* PLB starting addr: 0x00000000A0000000 */
 214         PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
 215
 216         /* PCI start addr, 0xA0000000 (PCI Address) */
 217         PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
 218         PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
 219
 220         /* Enable no pre-fetch, enable region */
 221         PCI_WRITEL(((0xffffffff -
 222                      (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
 223                       BAMBOO_PCIL0_PMM0MA);
 224
 225         /* Disable region one */
 226         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
 227         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
 228         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
 229         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
 230         PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
 231
 232         /* Disable region two */
 233         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
 234         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
 235         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
 236         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
 237         PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
 238
 239         /* Now configure the PCI->PLB windows, we only use PTM1
 240          *
 241          * For Inbound flow, set the window size to all available memory
 242          * This is required because if size is smaller,
 243          * then Eth/PCI DD would fail as PCI card not able to access
 244          * the memory allocated by DD.
 245          */
 246
 247         PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS);     /* disabled region 1 */
 248         PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA);     /* begin of address map */
 249
 250         memory_size = 1 << fls(memory_size - 1);
 251
 252         /* Size low + Enabled */
 253         PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
 254
 255         eieio();
 256         iounmap(pci_reg_base);
 257 }
 258
 259 static void __init
 260 bamboo_setup_hose(void)
 261 {
 262         unsigned int bar_response, bar;
 263         struct pci_controller *hose;
 264
 265         bamboo_setup_pci();
 266
 267         hose = pcibios_alloc_controller();
 268
 269         if (!hose)
 270                 return;
 271
 272         hose->first_busno = 0;
 273         hose->last_busno = 0xff;
 274
 275         hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
 276
 277         pci_init_resource(&hose->io_resource,
 278                         BAMBOO_PCI_LOWER_IO,
 279                         BAMBOO_PCI_UPPER_IO,
 280                         IORESOURCE_IO,
 281                         "PCI host bridge");
 282
 283         pci_init_resource(&hose->mem_resources[0],
 284                         BAMBOO_PCI_LOWER_MEM,
 285                         BAMBOO_PCI_UPPER_MEM,
 286                         IORESOURCE_MEM,
 287                         "PCI host bridge");
 288
 289         ppc_md.pci_exclude_device = bamboo_exclude_device;
 290
 291         hose->io_space.start = BAMBOO_PCI_LOWER_IO;
 292         hose->io_space.end = BAMBOO_PCI_UPPER_IO;
 293         hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
 294         hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
 295         isa_io_base =
 296                 (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
 297         hose->io_base_virt = (void *)isa_io_base;
 298
 299         setup_indirect_pci(hose,
 300                         BAMBOO_PCI_CFGA_PLB32,
 301                         BAMBOO_PCI_CFGD_PLB32);
 302         hose->set_cfg_type = 1;
 303
 304         /* Zero config bars */
 305         for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 306                 early_write_config_dword(hose, hose->first_busno,
 307                                          PCI_FUNC(hose->first_busno), bar,
 308                                          0x00000000);
 309                 early_read_config_dword(hose, hose->first_busno,
 310                                         PCI_FUNC(hose->first_busno), bar,
 311                                         &bar_response);
 312         }
 313
 314         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 315
 316         ppc_md.pci_swizzle = common_swizzle;
 317         ppc_md.pci_map_irq = bamboo_map_irq;
 318 }
 319
 320 TODC_ALLOC();
 321
 322 static void __init
 323 bamboo_early_serial_map(void)
 324 {
 325         struct uart_port port;
 326
 327         /* Setup ioremapped serial port access */
 328         memset(&port, 0, sizeof(port));
 329         port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
 330         port.irq = 0;
 331         port.uartclk = clocks.uart0;
 332         port.regshift = 0;
 333         port.iotype = UPIO_MEM;
 334         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 335         port.line = 0;
 336
 337         if (early_serial_setup(&port) != 0) {
 338                 printk("Early serial init of port 0 failed\n");
 339         }
 340
 341 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 342         /* Configure debug serial access */
 343         gen550_init(0, &port);
 344 #endif
 345
 346         port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
 347         port.irq = 1;
 348         port.uartclk = clocks.uart1;
 349         port.line = 1;
 350
 351         if (early_serial_setup(&port) != 0) {
 352                 printk("Early serial init of port 1 failed\n");
 353         }
 354
 355 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 356         /* Configure debug serial access */
 357         gen550_init(1, &port);
 358 #endif
 359
 360         port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
 361         port.irq = 3;
 362         port.uartclk = clocks.uart2;
 363         port.line = 2;
 364
 365         if (early_serial_setup(&port) != 0) {
 366                 printk("Early serial init of port 2 failed\n");
 367         }
 368
 369 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 370         /* Configure debug serial access */
 371         gen550_init(2, &port);
 372 #endif
 373
 374         port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
 375         port.irq = 4;
 376         port.uartclk = clocks.uart3;
 377         port.line = 3;
 378
 379         if (early_serial_setup(&port) != 0) {
 380                 printk("Early serial init of port 3 failed\n");
 381         }
 382 }
 383
 384 static void __init
 385 bamboo_setup_arch(void)
 386 {
 387
 388         bamboo_set_emacdata();
 389
 390         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 391         ocp_sys_info.opb_bus_freq = clocks.opb;
 392
 393         /* Setup TODC access */
 394         TODC_INIT(TODC_TYPE_DS1743,
 395                         0,
 396                         0,
 397                         ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
 398                         8);
 399
 400         /* init to some ~sane value until calibrate_delay() runs */
 401         loops_per_jiffy = 50000000/HZ;
 402
 403         /* Setup PCI host bridge */
 404         bamboo_setup_hose();
 405
 406 #ifdef CONFIG_BLK_DEV_INITRD
 407         if (initrd_start)
 408                 ROOT_DEV = Root_RAM0;
 409         else
 410 #endif
 411 #ifdef CONFIG_ROOT_NFS
 412                 ROOT_DEV = Root_NFS;
 413 #else
 414                 ROOT_DEV = Root_HDA1;
 415 #endif
 416
 417         bamboo_early_serial_map();
 418
 419         /* Identify the system */
 420         printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
 421 }
 422
 423 void __init platform_init(unsigned long r3, unsigned long r4,
 424                 unsigned long r5, unsigned long r6, unsigned long r7)
 425 {
 426         ibm44x_platform_init(r3, r4, r5, r6, r7);
 427
 428         ppc_md.setup_arch = bamboo_setup_arch;
 429         ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
 430         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 431
 432         ppc_md.calibrate_decr = bamboo_calibrate_decr;
 433         ppc_md.time_init = todc_time_init;
 434         ppc_md.set_rtc_time = todc_set_rtc_time;
 435         ppc_md.get_rtc_time = todc_get_rtc_time;
 436
 437         ppc_md.nvram_read_val = todc_direct_read_val;
 438         ppc_md.nvram_write_val = todc_direct_write_val;
 439 #ifdef CONFIG_KGDB
 440         ppc_md.early_serial_map = bamboo_early_serial_map;
 441 #endif
 442 }
 443