2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/smp.h>
26 #include <linux/interrupt.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
32 #include <linux/ratelimit.h>
34 #include <asm/ptrace.h>
35 #include <asm/signal.h>
37 #include <asm/pgtable.h>
39 #include <asm/machdep.h>
46 #define DBG(fmt...) printk(fmt)
51 static struct mpic *mpics;
52 static struct mpic *mpic_primary;
53 static DEFINE_RAW_SPINLOCK(mpic_lock);
55 #ifdef CONFIG_PPC32 /* XXX for now */
56 #ifdef CONFIG_IRQ_ALL_CPUS
57 #define distribute_irqs (1)
59 #define distribute_irqs (0)
63 #ifdef CONFIG_MPIC_WEIRD
64 static u32 mpic_infos[][MPIC_IDX_END] = {
65 [0] = { /* Original OpenPIC compatible MPIC */
68 MPIC_GREG_GLOBAL_CONF_0,
70 MPIC_GREG_IPI_VECTOR_PRI_0,
77 MPIC_TIMER_CURRENT_CNT,
79 MPIC_TIMER_VECTOR_PRI,
80 MPIC_TIMER_DESTINATION,
84 MPIC_CPU_IPI_DISPATCH_0,
85 MPIC_CPU_IPI_DISPATCH_STRIDE,
86 MPIC_CPU_CURRENT_TASK_PRI,
95 MPIC_VECPRI_VECTOR_MASK,
96 MPIC_VECPRI_POLARITY_POSITIVE,
97 MPIC_VECPRI_POLARITY_NEGATIVE,
98 MPIC_VECPRI_SENSE_LEVEL,
99 MPIC_VECPRI_SENSE_EDGE,
100 MPIC_VECPRI_POLARITY_MASK,
101 MPIC_VECPRI_SENSE_MASK,
104 [1] = { /* Tsi108/109 PIC */
106 TSI108_GREG_FEATURE_0,
107 TSI108_GREG_GLOBAL_CONF_0,
108 TSI108_GREG_VENDOR_ID,
109 TSI108_GREG_IPI_VECTOR_PRI_0,
110 TSI108_GREG_IPI_STRIDE,
111 TSI108_GREG_SPURIOUS,
112 TSI108_GREG_TIMER_FREQ,
116 TSI108_TIMER_CURRENT_CNT,
117 TSI108_TIMER_BASE_CNT,
118 TSI108_TIMER_VECTOR_PRI,
119 TSI108_TIMER_DESTINATION,
123 TSI108_CPU_IPI_DISPATCH_0,
124 TSI108_CPU_IPI_DISPATCH_STRIDE,
125 TSI108_CPU_CURRENT_TASK_PRI,
133 TSI108_IRQ_VECTOR_PRI,
134 TSI108_VECPRI_VECTOR_MASK,
135 TSI108_VECPRI_POLARITY_POSITIVE,
136 TSI108_VECPRI_POLARITY_NEGATIVE,
137 TSI108_VECPRI_SENSE_LEVEL,
138 TSI108_VECPRI_SENSE_EDGE,
139 TSI108_VECPRI_POLARITY_MASK,
140 TSI108_VECPRI_SENSE_MASK,
141 TSI108_IRQ_DESTINATION
145 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
147 #else /* CONFIG_MPIC_WEIRD */
149 #define MPIC_INFO(name) MPIC_##name
151 #endif /* CONFIG_MPIC_WEIRD */
153 static inline unsigned int mpic_processor_id(struct mpic *mpic)
155 unsigned int cpu = 0;
157 if (mpic->flags & MPIC_PRIMARY)
158 cpu = hard_smp_processor_id();
164 * Register accessor functions
168 static inline u32 _mpic_read(enum mpic_reg_type type,
169 struct mpic_reg_bank *rb,
173 #ifdef CONFIG_PPC_DCR
174 case mpic_access_dcr:
175 return dcr_read(rb->dhost, reg);
177 case mpic_access_mmio_be:
178 return in_be32(rb->base + (reg >> 2));
179 case mpic_access_mmio_le:
181 return in_le32(rb->base + (reg >> 2));
185 static inline void _mpic_write(enum mpic_reg_type type,
186 struct mpic_reg_bank *rb,
187 unsigned int reg, u32 value)
190 #ifdef CONFIG_PPC_DCR
191 case mpic_access_dcr:
192 dcr_write(rb->dhost, reg, value);
195 case mpic_access_mmio_be:
196 out_be32(rb->base + (reg >> 2), value);
198 case mpic_access_mmio_le:
200 out_le32(rb->base + (reg >> 2), value);
205 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
207 enum mpic_reg_type type = mpic->reg_type;
208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
209 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
212 type = mpic_access_mmio_be;
213 return _mpic_read(type, &mpic->gregs, offset);
216 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
219 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
224 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
230 offset += 0x1000 / 4;
232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
235 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
241 offset += 0x1000 / 4;
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
246 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
248 unsigned int cpu = mpic_processor_id(mpic);
250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
253 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
255 unsigned int cpu = mpic_processor_id(mpic);
257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
260 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
262 unsigned int isu = src_no >> mpic->isu_shift;
263 unsigned int idx = src_no & mpic->isu_mask;
266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
267 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
268 #ifdef CONFIG_MPIC_BROKEN_REGREAD
270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
271 mpic->isu_reg0_shadow[src_no];
276 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
277 unsigned int reg, u32 value)
279 unsigned int isu = src_no >> mpic->isu_shift;
280 unsigned int idx = src_no & mpic->isu_mask;
282 _mpic_write(mpic->reg_type, &mpic->isus[isu],
283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
285 #ifdef CONFIG_MPIC_BROKEN_REGREAD
287 mpic->isu_reg0_shadow[src_no] =
288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
292 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
293 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
294 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
295 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
296 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
298 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
299 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
300 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
301 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
305 * Low level utility functions
309 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
310 struct mpic_reg_bank *rb, unsigned int offset,
313 rb->base = ioremap(phys_addr + offset, size);
314 BUG_ON(rb->base == NULL);
317 #ifdef CONFIG_PPC_DCR
318 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
319 struct mpic_reg_bank *rb,
320 unsigned int offset, unsigned int size)
324 dbasep = of_get_property(node, "dcr-reg", NULL);
326 rb->dhost = dcr_map(node, *dbasep + offset, size);
327 BUG_ON(!DCR_MAP_OK(rb->dhost));
330 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
331 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
332 unsigned int offset, unsigned int size)
334 if (mpic->flags & MPIC_USES_DCR)
335 _mpic_map_dcr(mpic, node, rb, offset, size);
337 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
339 #else /* CONFIG_PPC_DCR */
340 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
341 #endif /* !CONFIG_PPC_DCR */
345 /* Check if we have one of those nice broken MPICs with a flipped endian on
346 * reads from IPI registers
348 static void __init mpic_test_broken_ipi(struct mpic *mpic)
352 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
353 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
355 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
356 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
357 mpic->flags |= MPIC_BROKEN_IPI;
361 #ifdef CONFIG_MPIC_U3_HT_IRQS
363 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
364 * to force the edge setting on the MPIC and do the ack workaround.
366 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
368 if (source >= 128 || !mpic->fixups)
370 return mpic->fixups[source].base != NULL;
374 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
376 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
378 if (fixup->applebase) {
379 unsigned int soff = (fixup->index >> 3) & ~3;
380 unsigned int mask = 1U << (fixup->index & 0x1f);
381 writel(mask, fixup->applebase + soff);
383 raw_spin_lock(&mpic->fixup_lock);
384 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
385 writel(fixup->data, fixup->base + 4);
386 raw_spin_unlock(&mpic->fixup_lock);
390 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
393 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
397 if (fixup->base == NULL)
400 DBG("startup_ht_interrupt(0x%x) index: %d\n",
401 source, fixup->index);
402 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
403 /* Enable and configure */
404 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
405 tmp = readl(fixup->base + 4);
409 writel(tmp, fixup->base + 4);
410 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
413 /* use the lowest bit inverted to the actual HW,
414 * set if this fixup was enabled, clear otherwise */
415 mpic->save_data[source].fixup_data = tmp | 1;
419 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
421 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
425 if (fixup->base == NULL)
428 DBG("shutdown_ht_interrupt(0x%x)\n", source);
431 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
432 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
433 tmp = readl(fixup->base + 4);
435 writel(tmp, fixup->base + 4);
436 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
439 /* use the lowest bit inverted to the actual HW,
440 * set if this fixup was enabled, clear otherwise */
441 mpic->save_data[source].fixup_data = tmp & ~1;
445 #ifdef CONFIG_PCI_MSI
446 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
453 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
454 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
455 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
456 if (id == PCI_CAP_ID_HT) {
457 id = readb(devbase + pos + 3);
458 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
466 base = devbase + pos;
468 flags = readb(base + HT_MSI_FLAGS);
469 if (!(flags & HT_MSI_FLAGS_FIXED)) {
470 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
471 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
474 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
475 PCI_SLOT(devfn), PCI_FUNC(devfn),
476 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
478 if (!(flags & HT_MSI_FLAGS_ENABLE))
479 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
482 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
489 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
490 unsigned int devfn, u32 vdid)
497 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
498 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
499 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
500 if (id == PCI_CAP_ID_HT) {
501 id = readb(devbase + pos + 3);
502 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
509 base = devbase + pos;
510 writeb(0x01, base + 2);
511 n = (readl(base + 4) >> 16) & 0xff;
513 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
515 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
517 for (i = 0; i <= n; i++) {
518 writeb(0x10 + 2 * i, base + 2);
519 tmp = readl(base + 4);
520 irq = (tmp >> 16) & 0xff;
521 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
522 /* mask it , will be unmasked later */
524 writel(tmp, base + 4);
525 mpic->fixups[irq].index = i;
526 mpic->fixups[irq].base = base;
527 /* Apple HT PIC has a non-standard way of doing EOIs */
528 if ((vdid & 0xffff) == 0x106b)
529 mpic->fixups[irq].applebase = devbase + 0x60;
531 mpic->fixups[irq].applebase = NULL;
532 writeb(0x11 + 2 * i, base + 2);
533 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
538 static void __init mpic_scan_ht_pics(struct mpic *mpic)
541 u8 __iomem *cfgspace;
543 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
545 /* Allocate fixups array */
546 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
547 BUG_ON(mpic->fixups == NULL);
550 raw_spin_lock_init(&mpic->fixup_lock);
552 /* Map U3 config space. We assume all IO-APICs are on the primary bus
553 * so we only need to map 64kB.
555 cfgspace = ioremap(0xf2000000, 0x10000);
556 BUG_ON(cfgspace == NULL);
558 /* Now we scan all slots. We do a very quick scan, we read the header
559 * type, vendor ID and device ID only, that's plenty enough
561 for (devfn = 0; devfn < 0x100; devfn++) {
562 u8 __iomem *devbase = cfgspace + (devfn << 8);
563 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
564 u32 l = readl(devbase + PCI_VENDOR_ID);
567 DBG("devfn %x, l: %x\n", devfn, l);
569 /* If no device, skip */
570 if (l == 0xffffffff || l == 0x00000000 ||
571 l == 0x0000ffff || l == 0xffff0000)
573 /* Check if is supports capability lists */
574 s = readw(devbase + PCI_STATUS);
575 if (!(s & PCI_STATUS_CAP_LIST))
578 mpic_scan_ht_pic(mpic, devbase, devfn, l);
579 mpic_scan_ht_msi(mpic, devbase, devfn);
582 /* next device, if function 0 */
583 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
588 #else /* CONFIG_MPIC_U3_HT_IRQS */
590 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
595 static void __init mpic_scan_ht_pics(struct mpic *mpic)
599 #endif /* CONFIG_MPIC_U3_HT_IRQS */
602 static int irq_choose_cpu(const struct cpumask *mask)
606 if (cpumask_equal(mask, cpu_all_mask)) {
607 static int irq_rover = 0;
608 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
611 /* Round-robin distribution... */
613 raw_spin_lock_irqsave(&irq_rover_lock, flags);
615 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
616 if (irq_rover >= nr_cpu_ids)
617 irq_rover = cpumask_first(cpu_online_mask);
621 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
623 cpuid = cpumask_first_and(mask, cpu_online_mask);
624 if (cpuid >= nr_cpu_ids)
628 return get_hard_smp_processor_id(cpuid);
631 static int irq_choose_cpu(const struct cpumask *mask)
633 return hard_smp_processor_id();
637 /* Find an mpic associated with a given linux interrupt */
638 static struct mpic *mpic_find(unsigned int irq)
640 if (irq < NUM_ISA_INTERRUPTS)
643 return irq_get_chip_data(irq);
646 /* Determine if the linux irq is an IPI */
647 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
649 unsigned int src = virq_to_hw(irq);
651 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
654 /* Determine if the linux irq is a timer */
655 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
657 unsigned int src = virq_to_hw(irq);
659 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
662 /* Convert a cpu mask from logical to physical cpu numbers. */
663 static inline u32 mpic_physmask(u32 cpumask)
668 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
669 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
674 /* Get the mpic structure from the IPI number */
675 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
677 return irq_data_get_irq_chip_data(d);
681 /* Get the mpic structure from the irq number */
682 static inline struct mpic * mpic_from_irq(unsigned int irq)
684 return irq_get_chip_data(irq);
687 /* Get the mpic structure from the irq data */
688 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
690 return irq_data_get_irq_chip_data(d);
694 static inline void mpic_eoi(struct mpic *mpic)
696 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
697 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
701 * Linux descriptor level callbacks
705 void mpic_unmask_irq(struct irq_data *d)
707 unsigned int loops = 100000;
708 struct mpic *mpic = mpic_from_irq_data(d);
709 unsigned int src = irqd_to_hwirq(d);
711 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
713 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
714 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
716 /* make sure mask gets to controller before we return to user */
719 printk(KERN_ERR "%s: timeout on hwirq %u\n",
723 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
726 void mpic_mask_irq(struct irq_data *d)
728 unsigned int loops = 100000;
729 struct mpic *mpic = mpic_from_irq_data(d);
730 unsigned int src = irqd_to_hwirq(d);
732 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
734 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
735 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
738 /* make sure mask gets to controller before we return to user */
741 printk(KERN_ERR "%s: timeout on hwirq %u\n",
745 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
748 void mpic_end_irq(struct irq_data *d)
750 struct mpic *mpic = mpic_from_irq_data(d);
753 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
755 /* We always EOI on end_irq() even for edge interrupts since that
756 * should only lower the priority, the MPIC should have properly
757 * latched another edge interrupt coming in anyway
763 #ifdef CONFIG_MPIC_U3_HT_IRQS
765 static void mpic_unmask_ht_irq(struct irq_data *d)
767 struct mpic *mpic = mpic_from_irq_data(d);
768 unsigned int src = irqd_to_hwirq(d);
772 if (irqd_is_level_type(d))
773 mpic_ht_end_irq(mpic, src);
776 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
778 struct mpic *mpic = mpic_from_irq_data(d);
779 unsigned int src = irqd_to_hwirq(d);
782 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
787 static void mpic_shutdown_ht_irq(struct irq_data *d)
789 struct mpic *mpic = mpic_from_irq_data(d);
790 unsigned int src = irqd_to_hwirq(d);
792 mpic_shutdown_ht_interrupt(mpic, src);
796 static void mpic_end_ht_irq(struct irq_data *d)
798 struct mpic *mpic = mpic_from_irq_data(d);
799 unsigned int src = irqd_to_hwirq(d);
802 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
804 /* We always EOI on end_irq() even for edge interrupts since that
805 * should only lower the priority, the MPIC should have properly
806 * latched another edge interrupt coming in anyway
809 if (irqd_is_level_type(d))
810 mpic_ht_end_irq(mpic, src);
813 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
817 static void mpic_unmask_ipi(struct irq_data *d)
819 struct mpic *mpic = mpic_from_ipi(d);
820 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
822 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
823 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
826 static void mpic_mask_ipi(struct irq_data *d)
828 /* NEVER disable an IPI... that's just plain wrong! */
831 static void mpic_end_ipi(struct irq_data *d)
833 struct mpic *mpic = mpic_from_ipi(d);
836 * IPIs are marked IRQ_PER_CPU. This has the side effect of
837 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
838 * applying to them. We EOI them late to avoid re-entering.
839 * We mark IPI's with IRQF_DISABLED as they must run with
845 #endif /* CONFIG_SMP */
847 static void mpic_unmask_tm(struct irq_data *d)
849 struct mpic *mpic = mpic_from_irq_data(d);
850 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
852 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src);
853 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
857 static void mpic_mask_tm(struct irq_data *d)
859 struct mpic *mpic = mpic_from_irq_data(d);
860 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
862 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
866 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
869 struct mpic *mpic = mpic_from_irq_data(d);
870 unsigned int src = irqd_to_hwirq(d);
872 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
873 int cpuid = irq_choose_cpu(cpumask);
875 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
877 u32 mask = cpumask_bits(cpumask)[0];
879 mask &= cpumask_bits(cpu_online_mask)[0];
881 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
882 mpic_physmask(mask));
888 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
890 /* Now convert sense value */
891 switch(type & IRQ_TYPE_SENSE_MASK) {
892 case IRQ_TYPE_EDGE_RISING:
893 return MPIC_INFO(VECPRI_SENSE_EDGE) |
894 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
895 case IRQ_TYPE_EDGE_FALLING:
896 case IRQ_TYPE_EDGE_BOTH:
897 return MPIC_INFO(VECPRI_SENSE_EDGE) |
898 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
899 case IRQ_TYPE_LEVEL_HIGH:
900 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
901 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
902 case IRQ_TYPE_LEVEL_LOW:
904 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
905 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
909 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
911 struct mpic *mpic = mpic_from_irq_data(d);
912 unsigned int src = irqd_to_hwirq(d);
913 unsigned int vecpri, vold, vnew;
915 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
916 mpic, d->irq, src, flow_type);
918 if (src >= mpic->irq_count)
921 if (flow_type == IRQ_TYPE_NONE)
922 if (mpic->senses && src < mpic->senses_count)
923 flow_type = mpic->senses[src];
924 if (flow_type == IRQ_TYPE_NONE)
925 flow_type = IRQ_TYPE_LEVEL_LOW;
927 irqd_set_trigger_type(d, flow_type);
929 if (mpic_is_ht_interrupt(mpic, src))
930 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
931 MPIC_VECPRI_SENSE_EDGE;
933 vecpri = mpic_type_to_vecpri(mpic, flow_type);
935 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
936 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
937 MPIC_INFO(VECPRI_SENSE_MASK));
940 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
942 return IRQ_SET_MASK_OK_NOCOPY;;
945 void mpic_set_vector(unsigned int virq, unsigned int vector)
947 struct mpic *mpic = mpic_from_irq(virq);
948 unsigned int src = virq_to_hw(virq);
951 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
952 mpic, virq, src, vector);
954 if (src >= mpic->irq_count)
957 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
958 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
960 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
963 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
965 struct mpic *mpic = mpic_from_irq(virq);
966 unsigned int src = virq_to_hw(virq);
968 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
969 mpic, virq, src, cpuid);
971 if (src >= mpic->irq_count)
974 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
977 static struct irq_chip mpic_irq_chip = {
978 .irq_mask = mpic_mask_irq,
979 .irq_unmask = mpic_unmask_irq,
980 .irq_eoi = mpic_end_irq,
981 .irq_set_type = mpic_set_irq_type,
985 static struct irq_chip mpic_ipi_chip = {
986 .irq_mask = mpic_mask_ipi,
987 .irq_unmask = mpic_unmask_ipi,
988 .irq_eoi = mpic_end_ipi,
990 #endif /* CONFIG_SMP */
992 static struct irq_chip mpic_tm_chip = {
993 .irq_mask = mpic_mask_tm,
994 .irq_unmask = mpic_unmask_tm,
995 .irq_eoi = mpic_end_irq,
998 #ifdef CONFIG_MPIC_U3_HT_IRQS
999 static struct irq_chip mpic_irq_ht_chip = {
1000 .irq_startup = mpic_startup_ht_irq,
1001 .irq_shutdown = mpic_shutdown_ht_irq,
1002 .irq_mask = mpic_mask_irq,
1003 .irq_unmask = mpic_unmask_ht_irq,
1004 .irq_eoi = mpic_end_ht_irq,
1005 .irq_set_type = mpic_set_irq_type,
1007 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1010 static int mpic_host_match(struct irq_host *h, struct device_node *node)
1012 /* Exact match, unless mpic node is NULL */
1013 return h->of_node == NULL || h->of_node == node;
1016 static int mpic_host_map(struct irq_host *h, unsigned int virq,
1019 struct mpic *mpic = h->host_data;
1020 struct irq_chip *chip;
1022 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1024 if (hw == mpic->spurious_vec)
1026 if (mpic->protected && test_bit(hw, mpic->protected))
1030 else if (hw >= mpic->ipi_vecs[0]) {
1031 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
1033 DBG("mpic: mapping as IPI\n");
1034 irq_set_chip_data(virq, mpic);
1035 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1039 #endif /* CONFIG_SMP */
1041 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1042 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
1044 DBG("mpic: mapping as timer\n");
1045 irq_set_chip_data(virq, mpic);
1046 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1047 handle_fasteoi_irq);
1051 if (hw >= mpic->irq_count)
1054 mpic_msi_reserve_hwirq(mpic, hw);
1057 chip = &mpic->hc_irq;
1059 #ifdef CONFIG_MPIC_U3_HT_IRQS
1060 /* Check for HT interrupts, override vecpri */
1061 if (mpic_is_ht_interrupt(mpic, hw))
1062 chip = &mpic->hc_ht_irq;
1063 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1065 DBG("mpic: mapping to irq chip @%p\n", chip);
1067 irq_set_chip_data(virq, mpic);
1068 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1070 /* Set default irq type */
1071 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1073 /* If the MPIC was reset, then all vectors have already been
1074 * initialized. Otherwise, a per source lazy initialization
1077 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1078 mpic_set_vector(virq, hw);
1079 mpic_set_destination(virq, mpic_processor_id(mpic));
1080 mpic_irq_set_priority(virq, 8);
1086 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1087 const u32 *intspec, unsigned int intsize,
1088 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1091 struct mpic *mpic = h->host_data;
1092 static unsigned char map_mpic_senses[4] = {
1093 IRQ_TYPE_EDGE_RISING,
1095 IRQ_TYPE_LEVEL_HIGH,
1096 IRQ_TYPE_EDGE_FALLING,
1099 *out_hwirq = intspec[0];
1100 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1102 * Freescale MPIC with extended intspec:
1103 * First two cells are as usual. Third specifies
1104 * an "interrupt type". Fourth is type-specific data.
1106 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1108 switch (intspec[2]) {
1110 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1113 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1116 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1119 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1122 *out_hwirq = mpic->timer_vecs[intspec[0]];
1125 pr_debug("%s: unknown irq type %u\n",
1126 __func__, intspec[2]);
1130 *out_flags = map_mpic_senses[intspec[1] & 3];
1131 } else if (intsize > 1) {
1134 /* Apple invented a new race of encoding on machines with
1135 * an HT APIC. They encode, among others, the index within
1136 * the HT APIC. We don't care about it here since thankfully,
1137 * it appears that they have the APIC already properly
1138 * configured, and thus our current fixup code that reads the
1139 * APIC config works fine. However, we still need to mask out
1140 * bits in the specifier to make sure we only get bit 0 which
1141 * is the level/edge bit (the only sense bit exposed by Apple),
1142 * as their bit 1 means something else.
1144 if (machine_is(powermac))
1146 *out_flags = map_mpic_senses[intspec[1] & mask];
1148 *out_flags = IRQ_TYPE_NONE;
1150 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1151 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1156 static struct irq_host_ops mpic_host_ops = {
1157 .match = mpic_host_match,
1158 .map = mpic_host_map,
1159 .xlate = mpic_host_xlate,
1162 static int mpic_reset_prohibited(struct device_node *node)
1164 return node && of_get_property(node, "pic-no-reset", NULL);
1168 * Exported functions
1171 struct mpic * __init mpic_alloc(struct device_node *node,
1172 phys_addr_t phys_addr,
1174 unsigned int isu_size,
1175 unsigned int irq_count,
1183 u64 paddr = phys_addr;
1185 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1191 mpic->hc_irq = mpic_irq_chip;
1192 mpic->hc_irq.name = name;
1193 if (flags & MPIC_PRIMARY)
1194 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1195 #ifdef CONFIG_MPIC_U3_HT_IRQS
1196 mpic->hc_ht_irq = mpic_irq_ht_chip;
1197 mpic->hc_ht_irq.name = name;
1198 if (flags & MPIC_PRIMARY)
1199 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1200 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1203 mpic->hc_ipi = mpic_ipi_chip;
1204 mpic->hc_ipi.name = name;
1205 #endif /* CONFIG_SMP */
1207 mpic->hc_tm = mpic_tm_chip;
1208 mpic->hc_tm.name = name;
1210 mpic->flags = flags;
1211 mpic->isu_size = isu_size;
1212 mpic->irq_count = irq_count;
1213 mpic->num_sources = 0; /* so far */
1215 if (flags & MPIC_LARGE_VECTORS)
1220 mpic->timer_vecs[0] = intvec_top - 12;
1221 mpic->timer_vecs[1] = intvec_top - 11;
1222 mpic->timer_vecs[2] = intvec_top - 10;
1223 mpic->timer_vecs[3] = intvec_top - 9;
1224 mpic->timer_vecs[4] = intvec_top - 8;
1225 mpic->timer_vecs[5] = intvec_top - 7;
1226 mpic->timer_vecs[6] = intvec_top - 6;
1227 mpic->timer_vecs[7] = intvec_top - 5;
1228 mpic->ipi_vecs[0] = intvec_top - 4;
1229 mpic->ipi_vecs[1] = intvec_top - 3;
1230 mpic->ipi_vecs[2] = intvec_top - 2;
1231 mpic->ipi_vecs[3] = intvec_top - 1;
1232 mpic->spurious_vec = intvec_top;
1234 /* Check for "big-endian" in device-tree */
1235 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1236 mpic->flags |= MPIC_BIG_ENDIAN;
1237 if (node && of_device_is_compatible(node, "fsl,mpic"))
1238 mpic->flags |= MPIC_FSL;
1240 /* Look for protected sources */
1243 unsigned int bits, mapsize;
1245 of_get_property(node, "protected-sources", &psize);
1248 bits = intvec_top + 1;
1249 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1250 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1251 BUG_ON(mpic->protected == NULL);
1252 for (i = 0; i < psize; i++) {
1253 if (psrc[i] > intvec_top)
1255 __set_bit(psrc[i], mpic->protected);
1260 #ifdef CONFIG_MPIC_WEIRD
1261 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1264 /* default register type */
1265 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1266 mpic_access_mmio_be : mpic_access_mmio_le;
1268 /* If no physical address is passed in, a device-node is mandatory */
1269 BUG_ON(paddr == 0 && node == NULL);
1271 /* If no physical address passed in, check if it's dcr based */
1272 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1273 #ifdef CONFIG_PPC_DCR
1274 mpic->flags |= MPIC_USES_DCR;
1275 mpic->reg_type = mpic_access_dcr;
1278 #endif /* CONFIG_PPC_DCR */
1281 /* If the MPIC is not DCR based, and no physical address was passed
1282 * in, try to obtain one
1284 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1285 const u32 *reg = of_get_property(node, "reg", NULL);
1286 BUG_ON(reg == NULL);
1287 paddr = of_translate_address(node, reg);
1288 BUG_ON(paddr == OF_BAD_ADDR);
1291 /* Map the global registers */
1292 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1293 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1297 /* When using a device-node, reset requests are only honored if the MPIC
1298 * is allowed to reset.
1300 if (mpic_reset_prohibited(node))
1301 mpic->flags |= MPIC_NO_RESET;
1303 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1304 printk(KERN_DEBUG "mpic: Resetting\n");
1305 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1306 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1307 | MPIC_GREG_GCONF_RESET);
1308 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1309 & MPIC_GREG_GCONF_RESET)
1314 if (flags & MPIC_ENABLE_COREINT)
1315 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1316 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1317 | MPIC_GREG_GCONF_COREINT);
1319 if (flags & MPIC_ENABLE_MCK)
1320 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1321 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1322 | MPIC_GREG_GCONF_MCK);
1324 /* Read feature register, calculate num CPUs and, for non-ISU
1325 * MPICs, num sources as well. On ISU MPICs, sources are counted
1328 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1329 mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1330 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1331 if (isu_size == 0) {
1332 if (flags & MPIC_BROKEN_FRR_NIRQS)
1333 mpic->num_sources = mpic->irq_count;
1336 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1337 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1340 /* Map the per-CPU registers */
1341 for (i = 0; i < mpic->num_cpus; i++) {
1342 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1343 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1347 /* Initialize main ISU if none provided */
1348 if (mpic->isu_size == 0) {
1349 mpic->isu_size = mpic->num_sources;
1350 mpic_map(mpic, node, paddr, &mpic->isus[0],
1351 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1353 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1354 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1356 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1357 isu_size ? isu_size : mpic->num_sources,
1359 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1360 if (mpic->irqhost == NULL)
1363 mpic->irqhost->host_data = mpic;
1365 /* Display version */
1366 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1380 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1382 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1383 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1384 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1389 if (flags & MPIC_PRIMARY) {
1390 mpic_primary = mpic;
1391 irq_set_default_host(mpic->irqhost);
1397 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1400 unsigned int isu_first = isu_num * mpic->isu_size;
1402 BUG_ON(isu_num >= MPIC_MAX_ISU);
1404 mpic_map(mpic, mpic->irqhost->of_node,
1405 paddr, &mpic->isus[isu_num], 0,
1406 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1408 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1409 mpic->num_sources = isu_first + mpic->isu_size;
1412 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1414 mpic->senses = senses;
1415 mpic->senses_count = count;
1418 void __init mpic_init(struct mpic *mpic)
1423 BUG_ON(mpic->num_sources == 0);
1425 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1427 /* Set current processor priority to max */
1428 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1430 /* Initialize timers to our reserved vectors and mask them for now */
1431 for (i = 0; i < 4; i++) {
1432 mpic_write(mpic->tmregs,
1433 i * MPIC_INFO(TIMER_STRIDE) +
1434 MPIC_INFO(TIMER_DESTINATION),
1435 1 << hard_smp_processor_id());
1436 mpic_write(mpic->tmregs,
1437 i * MPIC_INFO(TIMER_STRIDE) +
1438 MPIC_INFO(TIMER_VECTOR_PRI),
1440 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1441 (mpic->timer_vecs[0] + i));
1444 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1445 mpic_test_broken_ipi(mpic);
1446 for (i = 0; i < 4; i++) {
1449 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1450 (mpic->ipi_vecs[0] + i));
1453 /* Initialize interrupt sources */
1454 if (mpic->irq_count == 0)
1455 mpic->irq_count = mpic->num_sources;
1457 /* Do the HT PIC fixups on U3 broken mpic */
1458 DBG("MPIC flags: %x\n", mpic->flags);
1459 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1460 mpic_scan_ht_pics(mpic);
1461 mpic_u3msi_init(mpic);
1464 mpic_pasemi_msi_init(mpic);
1466 cpu = mpic_processor_id(mpic);
1468 if (!(mpic->flags & MPIC_NO_RESET)) {
1469 for (i = 0; i < mpic->num_sources; i++) {
1470 /* start with vector = source number, and masked */
1471 u32 vecpri = MPIC_VECPRI_MASK | i |
1472 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1474 /* check if protected */
1475 if (mpic->protected && test_bit(i, mpic->protected))
1478 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1479 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1483 /* Init spurious vector */
1484 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1486 /* Disable 8259 passthrough, if supported */
1487 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1488 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1489 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1490 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1492 if (mpic->flags & MPIC_NO_BIAS)
1493 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1494 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1495 | MPIC_GREG_GCONF_NO_BIAS);
1497 /* Set current processor priority to 0 */
1498 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1501 /* allocate memory to save mpic state */
1502 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1504 BUG_ON(mpic->save_data == NULL);
1508 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1512 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1513 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1514 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1515 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1518 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1520 unsigned long flags;
1523 raw_spin_lock_irqsave(&mpic_lock, flags);
1524 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1526 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1528 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1529 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1530 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1533 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1535 struct mpic *mpic = mpic_find(irq);
1536 unsigned int src = virq_to_hw(irq);
1537 unsigned long flags;
1543 raw_spin_lock_irqsave(&mpic_lock, flags);
1544 if (mpic_is_ipi(mpic, irq)) {
1545 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1546 ~MPIC_VECPRI_PRIORITY_MASK;
1547 mpic_ipi_write(src - mpic->ipi_vecs[0],
1548 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1549 } else if (mpic_is_tm(mpic, irq)) {
1550 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1551 ~MPIC_VECPRI_PRIORITY_MASK;
1552 mpic_tm_write(src - mpic->timer_vecs[0],
1553 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1555 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1556 & ~MPIC_VECPRI_PRIORITY_MASK;
1557 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1558 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1560 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1563 void mpic_setup_this_cpu(void)
1566 struct mpic *mpic = mpic_primary;
1567 unsigned long flags;
1568 u32 msk = 1 << hard_smp_processor_id();
1571 BUG_ON(mpic == NULL);
1573 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1575 raw_spin_lock_irqsave(&mpic_lock, flags);
1577 /* let the mpic know we want intrs. default affinity is 0xffffffff
1578 * until changed via /proc. That's how it's done on x86. If we want
1579 * it differently, then we should make sure we also change the default
1580 * values of irq_desc[].affinity in irq.c.
1582 if (distribute_irqs) {
1583 for (i = 0; i < mpic->num_sources ; i++)
1584 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1585 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1588 /* Set current processor priority to 0 */
1589 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1591 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1592 #endif /* CONFIG_SMP */
1595 int mpic_cpu_get_priority(void)
1597 struct mpic *mpic = mpic_primary;
1599 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1602 void mpic_cpu_set_priority(int prio)
1604 struct mpic *mpic = mpic_primary;
1606 prio &= MPIC_CPU_TASKPRI_MASK;
1607 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1610 void mpic_teardown_this_cpu(int secondary)
1612 struct mpic *mpic = mpic_primary;
1613 unsigned long flags;
1614 u32 msk = 1 << hard_smp_processor_id();
1617 BUG_ON(mpic == NULL);
1619 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1620 raw_spin_lock_irqsave(&mpic_lock, flags);
1622 /* let the mpic know we don't want intrs. */
1623 for (i = 0; i < mpic->num_sources ; i++)
1624 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1625 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1627 /* Set current processor priority to max */
1628 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1629 /* We need to EOI the IPI since not all platforms reset the MPIC
1630 * on boot and new interrupts wouldn't get delivered otherwise.
1634 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1638 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1642 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1644 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1646 if (unlikely(src == mpic->spurious_vec)) {
1647 if (mpic->flags & MPIC_SPV_EOI)
1651 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1652 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1653 mpic->name, (int)src);
1658 return irq_linear_revmap(mpic->irqhost, src);
1661 unsigned int mpic_get_one_irq(struct mpic *mpic)
1663 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1666 unsigned int mpic_get_irq(void)
1668 struct mpic *mpic = mpic_primary;
1670 BUG_ON(mpic == NULL);
1672 return mpic_get_one_irq(mpic);
1675 unsigned int mpic_get_coreint_irq(void)
1678 struct mpic *mpic = mpic_primary;
1681 BUG_ON(mpic == NULL);
1683 src = mfspr(SPRN_EPR);
1685 if (unlikely(src == mpic->spurious_vec)) {
1686 if (mpic->flags & MPIC_SPV_EOI)
1690 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1691 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1692 mpic->name, (int)src);
1696 return irq_linear_revmap(mpic->irqhost, src);
1702 unsigned int mpic_get_mcirq(void)
1704 struct mpic *mpic = mpic_primary;
1706 BUG_ON(mpic == NULL);
1708 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1712 void mpic_request_ipis(void)
1714 struct mpic *mpic = mpic_primary;
1716 BUG_ON(mpic == NULL);
1718 printk(KERN_INFO "mpic: requesting IPIs...\n");
1720 for (i = 0; i < 4; i++) {
1721 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1722 mpic->ipi_vecs[0] + i);
1723 if (vipi == NO_IRQ) {
1724 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1727 smp_request_message_ipi(vipi, i);
1731 void smp_mpic_message_pass(int cpu, int msg)
1733 struct mpic *mpic = mpic_primary;
1736 BUG_ON(mpic == NULL);
1738 /* make sure we're sending something that translates to an IPI */
1739 if ((unsigned int)msg > 3) {
1740 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1741 smp_processor_id(), msg);
1746 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1749 physmask = 1 << get_hard_smp_processor_id(cpu);
1751 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1752 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1755 int __init smp_mpic_probe(void)
1759 DBG("smp_mpic_probe()...\n");
1761 nr_cpus = cpumask_weight(cpu_possible_mask);
1763 DBG("nr_cpus: %d\n", nr_cpus);
1766 mpic_request_ipis();
1771 void __devinit smp_mpic_setup_cpu(int cpu)
1773 mpic_setup_this_cpu();
1776 void mpic_reset_core(int cpu)
1778 struct mpic *mpic = mpic_primary;
1780 int cpuid = get_hard_smp_processor_id(cpu);
1782 /* Set target bit for core reset */
1783 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1784 pir |= (1 << cpuid);
1785 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1786 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1788 /* Restore target bit after reset complete */
1789 pir &= ~(1 << cpuid);
1790 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1791 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1793 #endif /* CONFIG_SMP */
1796 static void mpic_suspend_one(struct mpic *mpic)
1800 for (i = 0; i < mpic->num_sources; i++) {
1801 mpic->save_data[i].vecprio =
1802 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1803 mpic->save_data[i].dest =
1804 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1808 static int mpic_suspend(void)
1810 struct mpic *mpic = mpics;
1813 mpic_suspend_one(mpic);
1820 static void mpic_resume_one(struct mpic *mpic)
1824 for (i = 0; i < mpic->num_sources; i++) {
1825 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1826 mpic->save_data[i].vecprio);
1827 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1828 mpic->save_data[i].dest);
1830 #ifdef CONFIG_MPIC_U3_HT_IRQS
1832 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1835 /* we use the lowest bit in an inverted meaning */
1836 if ((mpic->save_data[i].fixup_data & 1) == 0)
1839 /* Enable and configure */
1840 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1842 writel(mpic->save_data[i].fixup_data & ~1,
1847 } /* end for loop */
1850 static void mpic_resume(void)
1852 struct mpic *mpic = mpics;
1855 mpic_resume_one(mpic);
1860 static struct syscore_ops mpic_syscore_ops = {
1861 .resume = mpic_resume,
1862 .suspend = mpic_suspend,
1865 static int mpic_init_sys(void)
1867 register_syscore_ops(&mpic_syscore_ops);
1871 device_initcall(mpic_init_sys);