2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
27 #include <linux/module.h>
29 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
35 #include <asm/pmac_feature.h>
49 /* Workaround flags for 32bit powermac machines */
50 unsigned int of_irq_workarounds;
51 struct device_node *of_irq_dflt_pic;
53 /* Default addresses */
54 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
56 #define GC_LEVEL_MASK 0x3ff00000
57 #define OHARE_LEVEL_MASK 0x1ff00000
58 #define HEATHROW_LEVEL_MASK 0x1ff00000
61 static int max_real_irqs;
62 static u32 level_mask[4];
64 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
66 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
67 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
68 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
69 static int pmac_irq_cascade = -1;
70 static struct irq_host *pmac_pic_host;
72 static void __pmac_retrigger(unsigned int irq_nr)
74 if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
75 __set_bit(irq_nr, ppc_lost_interrupts);
76 irq_nr = pmac_irq_cascade;
79 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
80 atomic_inc(&ppc_n_lost_interrupts);
85 static void pmac_mask_and_ack_irq(struct irq_data *d)
87 unsigned int src = irq_map[d->irq].hwirq;
88 unsigned long bit = 1UL << (src & 0x1f);
92 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
93 __clear_bit(src, ppc_cached_irq_mask);
94 if (__test_and_clear_bit(src, ppc_lost_interrupts))
95 atomic_dec(&ppc_n_lost_interrupts);
96 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
97 out_le32(&pmac_irq_hw[i]->ack, bit);
99 /* make sure ack gets to controller before we enable
102 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
103 != (ppc_cached_irq_mask[i] & bit));
104 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
107 static void pmac_ack_irq(struct irq_data *d)
109 unsigned int src = irq_map[d->irq].hwirq;
110 unsigned long bit = 1UL << (src & 0x1f);
114 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
115 if (__test_and_clear_bit(src, ppc_lost_interrupts))
116 atomic_dec(&ppc_n_lost_interrupts);
117 out_le32(&pmac_irq_hw[i]->ack, bit);
118 (void)in_le32(&pmac_irq_hw[i]->ack);
119 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
122 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
124 unsigned long bit = 1UL << (irq_nr & 0x1f);
127 if ((unsigned)irq_nr >= max_irqs)
130 /* enable unmasked interrupts */
131 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
134 /* make sure mask gets to controller before we
137 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
138 != (ppc_cached_irq_mask[i] & bit));
141 * Unfortunately, setting the bit in the enable register
142 * when the device interrupt is already on *doesn't* set
143 * the bit in the flag register or request another interrupt.
145 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
146 __pmac_retrigger(irq_nr);
149 /* When an irq gets requested for the first client, if it's an
150 * edge interrupt, we clear any previous one on the controller
152 static unsigned int pmac_startup_irq(struct irq_data *d)
155 unsigned int src = irq_map[d->irq].hwirq;
156 unsigned long bit = 1UL << (src & 0x1f);
159 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
160 if (!irqd_is_level_type(d))
161 out_le32(&pmac_irq_hw[i]->ack, bit);
162 __set_bit(src, ppc_cached_irq_mask);
163 __pmac_set_irq_mask(src, 0);
164 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
169 static void pmac_mask_irq(struct irq_data *d)
172 unsigned int src = irq_map[d->irq].hwirq;
174 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
175 __clear_bit(src, ppc_cached_irq_mask);
176 __pmac_set_irq_mask(src, 1);
177 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
180 static void pmac_unmask_irq(struct irq_data *d)
183 unsigned int src = irq_map[d->irq].hwirq;
185 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
186 __set_bit(src, ppc_cached_irq_mask);
187 __pmac_set_irq_mask(src, 0);
188 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
191 static int pmac_retrigger(struct irq_data *d)
195 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
196 __pmac_retrigger(irq_map[d->irq].hwirq);
197 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
201 static struct irq_chip pmac_pic = {
203 .irq_startup = pmac_startup_irq,
204 .irq_mask = pmac_mask_irq,
205 .irq_ack = pmac_ack_irq,
206 .irq_mask_ack = pmac_mask_and_ack_irq,
207 .irq_unmask = pmac_unmask_irq,
208 .irq_retrigger = pmac_retrigger,
211 static irqreturn_t gatwick_action(int cpl, void *dev_id)
217 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
218 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
220 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
221 /* We must read level interrupts from the level register */
222 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
223 bits &= ppc_cached_irq_mask[i];
226 irq += __ilog2(bits);
227 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
228 generic_handle_irq(irq);
229 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
232 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
236 static unsigned int pmac_pic_get_irq(void)
239 unsigned long bits = 0;
243 void psurge_smp_message_recv(void);
245 /* IPI's are a hack on the powersurge -- Cort */
246 if ( smp_processor_id() != 0 ) {
247 psurge_smp_message_recv();
248 return NO_IRQ_IGNORE; /* ignore, already handled */
250 #endif /* CONFIG_SMP */
251 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
252 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
254 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
255 /* We must read level interrupts from the level register */
256 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
257 bits &= ppc_cached_irq_mask[i];
260 irq += __ilog2(bits);
263 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
264 if (unlikely(irq < 0))
266 return irq_linear_revmap(pmac_pic_host, irq);
270 static struct irqaction xmon_action = {
277 static struct irqaction gatwick_cascade_action = {
278 .handler = gatwick_action,
279 .flags = IRQF_DISABLED,
283 static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
285 /* We match all, we don't always have a node anyway */
289 static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
297 /* Mark level interrupts, set delayed disable for edge ones and set
300 level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
302 irq_set_status_flags(virq, IRQ_LEVEL);
303 irq_set_chip_and_handler(virq, &pmac_pic,
304 level ? handle_level_irq : handle_edge_irq);
308 static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct,
309 const u32 *intspec, unsigned int intsize,
310 irq_hw_number_t *out_hwirq,
311 unsigned int *out_flags)
314 *out_flags = IRQ_TYPE_NONE;
315 *out_hwirq = *intspec;
319 static struct irq_host_ops pmac_pic_host_ops = {
320 .match = pmac_pic_host_match,
321 .map = pmac_pic_host_map,
322 .xlate = pmac_pic_host_xlate,
325 static void __init pmac_pic_probe_oldstyle(void)
328 struct device_node *master = NULL;
329 struct device_node *slave = NULL;
333 /* Set our get_irq function */
334 ppc_md.get_irq = pmac_pic_get_irq;
337 * Find the interrupt controller type & node
340 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
341 max_irqs = max_real_irqs = 32;
342 level_mask[0] = GC_LEVEL_MASK;
343 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
344 max_irqs = max_real_irqs = 32;
345 level_mask[0] = OHARE_LEVEL_MASK;
347 /* We might have a second cascaded ohare */
348 slave = of_find_node_by_name(NULL, "pci106b,7");
351 level_mask[1] = OHARE_LEVEL_MASK;
353 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
354 max_irqs = max_real_irqs = 64;
355 level_mask[0] = HEATHROW_LEVEL_MASK;
358 /* We might have a second cascaded heathrow */
359 slave = of_find_node_by_name(master, "mac-io");
361 /* Check ordering of master & slave */
362 if (of_device_is_compatible(master, "gatwick")) {
363 struct device_node *tmp;
364 BUG_ON(slave == NULL);
370 /* We found a slave */
373 level_mask[2] = HEATHROW_LEVEL_MASK;
377 BUG_ON(master == NULL);
380 * Allocate an irq host
382 pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs,
385 BUG_ON(pmac_pic_host == NULL);
386 irq_set_default_host(pmac_pic_host);
388 /* Get addresses of first controller if we have a node for it */
389 BUG_ON(of_address_to_resource(master, 0, &r));
391 /* Map interrupts of primary controller */
392 addr = (u8 __iomem *) ioremap(r.start, 0x40);
394 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
396 if (max_real_irqs > 32)
397 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
401 printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n",
402 master->full_name, max_real_irqs);
404 /* Map interrupts of cascaded controller */
405 if (slave && !of_address_to_resource(slave, 0, &r)) {
406 addr = (u8 __iomem *)ioremap(r.start, 0x40);
407 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
411 (volatile struct pmac_irq_hw __iomem *)
413 pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
415 printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
416 " cascade: %d\n", slave->full_name,
417 max_irqs - max_real_irqs, pmac_irq_cascade);
421 /* Disable all interrupts in all controllers */
422 for (i = 0; i * 32 < max_irqs; ++i)
423 out_le32(&pmac_irq_hw[i]->enable, 0);
425 /* Hookup cascade irq */
426 if (slave && pmac_irq_cascade != NO_IRQ)
427 setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
429 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
431 setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
435 int of_irq_map_oldworld(struct device_node *device, int index,
436 struct of_irq *out_irq)
438 const u32 *ints = NULL;
442 * Old machines just have a list of interrupt numbers
443 * and no interrupt-controller nodes. We also have dodgy
444 * cases where the APPL,interrupts property is completely
445 * missing behind pci-pci bridges and we have to get it
446 * from the parent (the bridge itself, as apple just wired
447 * everything together on these)
450 ints = of_get_property(device, "AAPL,interrupts", &intlen);
453 device = device->parent;
454 if (device && strcmp(device->type, "pci") != 0)
459 intlen /= sizeof(u32);
464 out_irq->controller = NULL;
465 out_irq->specifier[0] = ints[index];
470 #endif /* CONFIG_PPC32 */
472 static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
474 struct irq_chip *chip = irq_desc_get_chip(desc);
475 struct mpic *mpic = irq_desc_get_handler_data(desc);
476 unsigned int cascade_irq = mpic_get_one_irq(mpic);
478 if (cascade_irq != NO_IRQ)
479 generic_handle_irq(cascade_irq);
481 chip->irq_eoi(&desc->irq_data);
484 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
486 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
487 struct device_node* pswitch;
490 pswitch = of_find_node_by_name(NULL, "programmer-switch");
492 nmi_irq = irq_of_parse_and_map(pswitch, 0);
493 if (nmi_irq != NO_IRQ) {
494 mpic_irq_set_priority(nmi_irq, 9);
495 setup_irq(nmi_irq, &xmon_action);
497 of_node_put(pswitch);
499 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
502 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
505 const char *name = master ? " MPIC 1 " : " MPIC 2 ";
508 unsigned int flags = master ? MPIC_PRIMARY : 0;
511 rc = of_address_to_resource(np, 0, &r);
515 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
517 flags |= MPIC_WANTS_RESET;
518 if (of_get_property(np, "big-endian", NULL))
519 flags |= MPIC_BIG_ENDIAN;
521 /* Primary Big Endian means HT interrupts. This is quite dodgy
522 * but works until I find a better way
524 if (master && (flags & MPIC_BIG_ENDIAN))
525 flags |= MPIC_U3_HT_IRQS;
527 mpic = mpic_alloc(np, r.start, flags, 0, 0, name);
536 static int __init pmac_pic_probe_mpic(void)
538 struct mpic *mpic1, *mpic2;
539 struct device_node *np, *master = NULL, *slave = NULL;
540 unsigned int cascade;
542 /* We can have up to 2 MPICs cascaded */
543 for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
545 if (master == NULL &&
546 of_get_property(np, "interrupts", NULL) == NULL)
547 master = of_node_get(np);
548 else if (slave == NULL)
549 slave = of_node_get(np);
554 /* Check for bogus setups */
555 if (master == NULL && slave != NULL) {
560 /* Not found, default to good old pmac pic */
564 /* Set master handler */
565 ppc_md.get_irq = mpic_get_irq;
568 mpic1 = pmac_setup_one_mpic(master, 1);
569 BUG_ON(mpic1 == NULL);
571 /* Install NMI if any */
572 pmac_pic_setup_mpic_nmi(mpic1);
576 /* No slave, let's go out */
580 /* Get/Map slave interrupt */
581 cascade = irq_of_parse_and_map(slave, 0);
582 if (cascade == NO_IRQ) {
583 printk(KERN_ERR "Failed to map cascade IRQ\n");
587 mpic2 = pmac_setup_one_mpic(slave, 0);
589 printk(KERN_ERR "Failed to setup slave MPIC\n");
593 irq_set_handler_data(cascade, mpic2);
594 irq_set_chained_handler(cascade, pmac_u3_cascade);
601 void __init pmac_pic_init(void)
603 /* We configure the OF parsing based on our oldworld vs. newworld
604 * platform type and wether we were booted by BootX.
608 of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
609 if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
610 of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
612 /* If we don't have phandles on a newworld, then try to locate a
613 * default interrupt controller (happens when booting with BootX).
614 * We do a first match here, hopefully, that only ever happens on
615 * machines with one controller.
617 if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
618 struct device_node *np;
620 for_each_node_with_property(np, "interrupt-controller") {
621 /* Skip /chosen/interrupt-controller */
622 if (strcmp(np->name, "chosen") == 0)
624 /* It seems like at least one person wants
625 * to use BootX on a machine with an AppleKiwi
626 * controller which happens to pretend to be an
627 * interrupt controller too. */
628 if (strcmp(np->name, "AppleKiwi") == 0)
630 /* I think we found one ! */
631 of_irq_dflt_pic = np;
635 #endif /* CONFIG_PPC32 */
637 /* We first try to detect Apple's new Core99 chipset, since mac-io
638 * is quite different on those machines and contains an IBM MPIC2.
640 if (pmac_pic_probe_mpic() == 0)
644 pmac_pic_probe_oldstyle();
648 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
650 * These procedures are used in implementing sleep on the powerbooks.
651 * sleep_save_intrs() saves the states of all interrupt enables
652 * and disables all interrupts except for the nominated one.
653 * sleep_restore_intrs() restores the states of all interrupt enables.
655 unsigned long sleep_save_mask[2];
657 /* This used to be passed by the PMU driver but that link got
658 * broken with the new driver model. We use this tweak for now...
659 * We really want to do things differently though...
661 static int pmacpic_find_viaint(void)
665 #ifdef CONFIG_ADB_PMU
666 struct device_node *np;
668 if (pmu_get_model() != PMU_OHARE_BASED)
670 np = of_find_node_by_name(NULL, "via-pmu");
673 viaint = irq_of_parse_and_map(np, 0);
676 #endif /* CONFIG_ADB_PMU */
680 static int pmacpic_suspend(void)
682 int viaint = pmacpic_find_viaint();
684 sleep_save_mask[0] = ppc_cached_irq_mask[0];
685 sleep_save_mask[1] = ppc_cached_irq_mask[1];
686 ppc_cached_irq_mask[0] = 0;
687 ppc_cached_irq_mask[1] = 0;
689 set_bit(viaint, ppc_cached_irq_mask);
690 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
691 if (max_real_irqs > 32)
692 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
693 (void)in_le32(&pmac_irq_hw[0]->event);
694 /* make sure mask gets to controller before we return to caller */
696 (void)in_le32(&pmac_irq_hw[0]->enable);
701 static void pmacpic_resume(void)
705 out_le32(&pmac_irq_hw[0]->enable, 0);
706 if (max_real_irqs > 32)
707 out_le32(&pmac_irq_hw[1]->enable, 0);
709 for (i = 0; i < max_real_irqs; ++i)
710 if (test_bit(i, sleep_save_mask))
711 pmac_unmask_irq(irq_get_irq_data(i));
714 static struct syscore_ops pmacpic_syscore_ops = {
715 .suspend = pmacpic_suspend,
716 .resume = pmacpic_resume,
719 static int __init init_pmacpic_syscore(void)
721 register_syscore_ops(&pmacpic_syscore_ops);
725 machine_subsys_initcall(powermac, init_pmacpic_syscore);
727 #endif /* CONFIG_PM && CONFIG_PPC32 */