arch/powerpc/platforms/chrp/pegasos_eth.c

   1 /*
   2  *  Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de>
   3  *  Thanks to :
   4  *      Dale Farnsworth <dale@farnsworth.org>
   5  *      Mark A. Greer <mgreer@mvista.com>
   6  *      Nicolas DET <nd@bplan-gmbh.de>
   7  *      Benjamin Herrenschmidt <benh@kernel.crashing.org>
   8  *  And anyone else who helped me on this.
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/device.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mv643xx.h>
  17 #include <linux/pci.h>
  18
  19 #define PEGASOS2_MARVELL_REGBASE                (0xf1000000)
  20 #define PEGASOS2_MARVELL_REGSIZE                (0x00004000)
  21 #define PEGASOS2_SRAM_BASE                      (0xf2000000)
  22 #define PEGASOS2_SRAM_SIZE                      (256*1024)
  23
  24 #define PEGASOS2_SRAM_BASE_ETH_PORT0                    (PEGASOS2_SRAM_BASE)
  25 #define PEGASOS2_SRAM_BASE_ETH_PORT1                    (PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) )
  26
  27
  28 #define PEGASOS2_SRAM_RXRING_SIZE               (PEGASOS2_SRAM_SIZE/4)
  29 #define PEGASOS2_SRAM_TXRING_SIZE               (PEGASOS2_SRAM_SIZE/4)
  30
  31 #undef BE_VERBOSE
  32
  33 static struct resource mv643xx_eth_shared_resources[] = {
  34         [0] = {
  35                 .name   = "ethernet shared base",
  36                 .start  = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
  37                 .end    = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
  38                                         MV643XX_ETH_SHARED_REGS_SIZE - 1,
  39                 .flags  = IORESOURCE_MEM,
  40         },
  41 };
  42
  43 static struct platform_device mv643xx_eth_shared_device = {
  44         .name           = MV643XX_ETH_SHARED_NAME,
  45         .id             = 0,
  46         .num_resources  = ARRAY_SIZE(mv643xx_eth_shared_resources),
  47         .resource       = mv643xx_eth_shared_resources,
  48 };
  49
  50 static struct resource mv643xx_eth_port1_resources[] = {
  51         [0] = {
  52                 .name   = "eth port1 irq",
  53                 .start  = 9,
  54                 .end    = 9,
  55                 .flags  = IORESOURCE_IRQ,
  56         },
  57 };
  58
  59 static struct mv643xx_eth_platform_data eth_port1_pd = {
  60         .shared         = &mv643xx_eth_shared_device,
  61         .port_number    = 1,
  62         .phy_addr       = MV643XX_ETH_PHY_ADDR(7),
  63
  64         .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1,
  65         .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
  66         .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
  67
  68         .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE,
  69         .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
  70         .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
  71 };
  72
  73 static struct platform_device eth_port1_device = {
  74         .name           = MV643XX_ETH_NAME,
  75         .id             = 1,
  76         .num_resources  = ARRAY_SIZE(mv643xx_eth_port1_resources),
  77         .resource       = mv643xx_eth_port1_resources,
  78         .dev = {
  79                 .platform_data = &eth_port1_pd,
  80         },
  81 };
  82
  83 static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
  84         &mv643xx_eth_shared_device,
  85         &eth_port1_device,
  86 };
  87
  88 /***********/
  89 /***********/
  90 #define MV_READ(offset,val)     { val = readl(mv643xx_reg_base + offset); }
  91 #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
  92
  93 static void __iomem *mv643xx_reg_base;
  94
  95 static int Enable_SRAM(void)
  96 {
  97         u32 ALong;
  98
  99         if (mv643xx_reg_base == NULL)
 100                 mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE,
 101                                         PEGASOS2_MARVELL_REGSIZE);
 102
 103         if (mv643xx_reg_base == NULL)
 104                 return -ENOMEM;
 105
 106 #ifdef BE_VERBOSE
 107         printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n",
 108                 (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base);
 109 #endif
 110
 111         MV_WRITE(MV64340_SRAM_CONFIG, 0);
 112
 113         MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16);
 114
 115         MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
 116         ALong &= ~(1 << 19);
 117         MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong);
 118
 119         ALong = 0x02;
 120         ALong |= PEGASOS2_SRAM_BASE & 0xffff0000;
 121         MV_WRITE(MV643XX_ETH_BAR_4, ALong);
 122
 123         MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000);
 124
 125         MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
 126         ALong &= ~(1 << 4);
 127         MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
 128
 129 #ifdef BE_VERBOSE
 130         printk("Pegasos II/Marvell MV64361: register unmapped\n");
 131         printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE);
 132 #endif
 133
 134         iounmap(mv643xx_reg_base);
 135         mv643xx_reg_base = NULL;
 136
 137         return 1;
 138 }
 139
 140
 141 /***********/
 142 /***********/
 143 static int __init mv643xx_eth_add_pds(void)
 144 {
 145         int ret = 0;
 146         static struct pci_device_id pci_marvell_mv64360[] = {
 147                 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) },
 148                 { }
 149         };
 150
 151 #ifdef BE_VERBOSE
 152         printk("Pegasos II/Marvell MV64361: init\n");
 153 #endif
 154
 155         if (pci_dev_present(pci_marvell_mv64360)) {
 156                 ret = platform_add_devices(mv643xx_eth_pd_devs,
 157                                 ARRAY_SIZE(mv643xx_eth_pd_devs));
 158
 159                 if ( Enable_SRAM() < 0)
 160                 {
 161                         eth_port1_pd.tx_sram_addr = 0;
 162                         eth_port1_pd.tx_sram_size = 0;
 163                         eth_port1_pd.rx_sram_addr = 0;
 164                         eth_port1_pd.rx_sram_size = 0;
 165
 166 #ifdef BE_VERBOSE
 167                         printk("Pegasos II/Marvell MV64361: Can't enable the "
 168                                 "SRAM\n");
 169 #endif
 170                 }
 171         }
 172
 173 #ifdef BE_VERBOSE
 174         printk("Pegasos II/Marvell MV64361: init is over\n");
 175 #endif
 176
 177         return ret;
 178 }
 179
 180 device_initcall(mv643xx_eth_add_pds);