arch/powerpc/platforms/86xx/mpc86xx_hpcn.c

   1 /*
   2  * MPC86xx HPCN board specific routines
   3  *
   4  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   5  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   6  *
   7  * Copyright 2006 Freescale Semiconductor Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/stddef.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/kdev_t.h>
  20 #include <linux/delay.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/root_dev.h>
  23
  24 #include <asm/system.h>
  25 #include <asm/time.h>
  26 #include <asm/machdep.h>
  27 #include <asm/pci-bridge.h>
  28 #include <asm/mpc86xx.h>
  29 #include <asm/prom.h>
  30 #include <mm/mmu_decl.h>
  31 #include <asm/udbg.h>
  32 #include <asm/i8259.h>
  33
  34 #include <asm/mpic.h>
  35
  36 #include <sysdev/fsl_soc.h>
  37
  38 #include "mpc86xx.h"
  39 #include "mpc8641_hpcn.h"
  40
  41 #ifndef CONFIG_PCI
  42 unsigned long isa_io_base = 0;
  43 unsigned long isa_mem_base = 0;
  44 unsigned long pci_dram_offset = 0;
  45 #endif
  46
  47
  48 /*
  49  * Internal interrupts are all Level Sensitive, and Positive Polarity
  50  */
  51
  52 static u_char mpc86xx_hpcn_openpic_initsenses[] __initdata = {
  53         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: Reserved */
  54         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: MCM */
  55         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
  56         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
  57         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
  58         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
  59         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
  60         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
  61         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCIE1 */
  62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: PCIE2 */
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: Reserved */
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: Reserved */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: DUART2 */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 1 Transmit */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 1 Receive */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: TSEC 3 transmit */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: TSEC 3 receive */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: TSEC 3 error */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 1 Receive/Transmit Error */
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 2 Transmit */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 2 Receive */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: TSEC 4 transmit */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: TSEC 4 receive */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: TSEC 4 error */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 2 Receive/Transmit Error */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Unused */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART1 */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
  81         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
  82         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
  83         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: Unused */
  84         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
  85         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 32: SRIO error/write-port unit */
  86         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 33: SRIO outbound doorbell */
  87         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 34: SRIO inbound doorbell */
  88         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 35: Unused */
  89         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 36: Unused */
  90         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 37: SRIO outbound message unit 1 */
  91         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 38: SRIO inbound message unit 1 */
  92         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 39: SRIO outbound message unit 2 */
  93         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 40: SRIO inbound message unit 2 */
  94         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 41: Unused */
  95         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 42: Unused */
  96         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 43: Unused */
  97         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 44: Unused */
  98         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 45: Unused */
  99         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 46: Unused */
 100         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 47: Unused */
 101         0x0,                                            /* External  0: */
 102         0x0,                                            /* External  1: */
 103         0x0,                                            /* External  2: */
 104         0x0,                                            /* External  3: */
 105         0x0,                                            /* External  4: */
 106         0x0,                                            /* External  5: */
 107         0x0,                                            /* External  6: */
 108         0x0,                                            /* External  7: */
 109         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External  8: Pixis FPGA */
 110         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* External  9: ULI 8259 INTR Cascade */
 111         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 10: Quad ETH PHY */
 112         0x0,                                            /* External 11: */
 113         0x0,
 114         0x0,
 115         0x0,
 116         0x0,
 117 };
 118
 119
 120 void __init
 121 mpc86xx_hpcn_init_irq(void)
 122 {
 123         struct mpic *mpic1;
 124         phys_addr_t openpic_paddr;
 125
 126         /* Determine the Physical Address of the OpenPIC regs */
 127         openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
 128
 129         /* Alloc mpic structure and per isu has 16 INT entries. */
 130         mpic1 = mpic_alloc(openpic_paddr,
 131                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 132                         16, MPC86xx_OPENPIC_IRQ_OFFSET, 0, 250,
 133                         mpc86xx_hpcn_openpic_initsenses,
 134                         sizeof(mpc86xx_hpcn_openpic_initsenses),
 135                         " MPIC     ");
 136         BUG_ON(mpic1 == NULL);
 137
 138         /* 48 Internal Interrupts */
 139         mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10200);
 140         mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10400);
 141         mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10600);
 142
 143         /* 16 External interrupts */
 144         mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10000);
 145
 146         mpic_init(mpic1);
 147
 148 #ifdef CONFIG_PCI
 149         mpic_setup_cascade(MPC86xx_IRQ_EXT9, i8259_irq_cascade, NULL);
 150         i8259_init(0, I8259_OFFSET);
 151 #endif
 152 }
 153
 154
 155
 156 #ifdef CONFIG_PCI
 157 /*
 158  * interrupt routing
 159  */
 160
 161 int
 162 mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 163 {
 164         static char pci_irq_table[][4] = {
 165                 /*
 166                  *      PCI IDSEL/INTPIN->INTLINE
 167                  *       A      B      C      D
 168                  */
 169                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 17 -- PCI Slot 1 */
 170                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 18 -- PCI Slot 2 */
 171                 {0, 0, 0, 0},                   /* IDSEL 19 */
 172                 {0, 0, 0, 0},                   /* IDSEL 20 */
 173                 {0, 0, 0, 0},                   /* IDSEL 21 */
 174                 {0, 0, 0, 0},                   /* IDSEL 22 */
 175                 {0, 0, 0, 0},                   /* IDSEL 23 */
 176                 {0, 0, 0, 0},                   /* IDSEL 24 */
 177                 {0, 0, 0, 0},                   /* IDSEL 25 */
 178                 {PIRQD, PIRQA, PIRQB, PIRQC},   /* IDSEL 26 -- PCI Bridge*/
 179                 {PIRQC, 0, 0, 0},               /* IDSEL 27 -- LAN */
 180                 {PIRQE, PIRQF, PIRQH, PIRQ7},   /* IDSEL 28 -- USB 1.1 */
 181                 {PIRQE, PIRQF, PIRQG, 0},       /* IDSEL 29 -- Audio & Modem */
 182                 {PIRQH, 0, 0, 0},               /* IDSEL 30 -- LPC & PMU*/
 183                 {PIRQD, 0, 0, 0},               /* IDSEL 31 -- ATA */
 184         };
 185
 186         const long min_idsel = 17, max_idsel = 31, irqs_per_slot = 4;
 187         return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
 188 }
 189
 190 static void __devinit quirk_ali1575(struct pci_dev *dev)
 191 {
 192         unsigned short temp;
 193
 194         /*
 195          * ALI1575 interrupts route table setup:
 196          *
 197          * IRQ pin   IRQ#
 198          * PIRQA ---- 3
 199          * PIRQB ---- 4
 200          * PIRQC ---- 5
 201          * PIRQD ---- 6
 202          * PIRQE ---- 9
 203          * PIRQF ---- 10
 204          * PIRQG ---- 11
 205          * PIRQH ---- 12
 206          *
 207          * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
 208          *                PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
 209          */
 210         pci_write_config_dword(dev, 0x48, 0xb9317542);
 211
 212         /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
 213         pci_write_config_byte(dev, 0x86, 0x0c);
 214
 215         /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
 216         pci_write_config_byte(dev, 0x87, 0x0d);
 217
 218         /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
 219         pci_write_config_byte(dev, 0x88, 0x0f);
 220
 221         /* USB 2.0 controller, interrupt: PIRQ7 */
 222         pci_write_config_byte(dev, 0x74, 0x06);
 223
 224         /* Audio controller, interrupt: PIRQE */
 225         pci_write_config_byte(dev, 0x8a, 0x0c);
 226
 227         /* Modem controller, interrupt: PIRQF */
 228         pci_write_config_byte(dev, 0x8b, 0x0d);
 229
 230         /* HD audio controller, interrupt: PIRQG */
 231         pci_write_config_byte(dev, 0x8c, 0x0e);
 232
 233         /* Serial ATA interrupt: PIRQD */
 234         pci_write_config_byte(dev, 0x8d, 0x0b);
 235
 236         /* SMB interrupt: PIRQH */
 237         pci_write_config_byte(dev, 0x8e, 0x0f);
 238
 239         /* PMU ACPI SCI interrupt: PIRQH */
 240         pci_write_config_byte(dev, 0x8f, 0x0f);
 241
 242         /* Primary PATA IDE IRQ: 14
 243          * Secondary PATA IDE IRQ: 15
 244          */
 245         pci_write_config_byte(dev, 0x44, 0x3d);
 246         pci_write_config_byte(dev, 0x75, 0x0f);
 247
 248         /* Set IRQ14 and IRQ15 to legacy IRQs */
 249         pci_read_config_word(dev, 0x46, &temp);
 250         temp |= 0xc000;
 251         pci_write_config_word(dev, 0x46, temp);
 252
 253         /* Set i8259 interrupt trigger
 254          * IRQ 3:  Level
 255          * IRQ 4:  Level
 256          * IRQ 5:  Level
 257          * IRQ 6:  Level
 258          * IRQ 7:  Level
 259          * IRQ 9:  Level
 260          * IRQ 10: Level
 261          * IRQ 11: Level
 262          * IRQ 12: Level
 263          * IRQ 14: Edge
 264          * IRQ 15: Edge
 265          */
 266         outb(0xfa, 0x4d0);
 267         outb(0x1e, 0x4d1);
 268 }
 269
 270 static void __devinit quirk_uli5288(struct pci_dev *dev)
 271 {
 272         unsigned char c;
 273
 274         pci_read_config_byte(dev,0x83,&c);
 275         c |= 0x80;
 276         pci_write_config_byte(dev, 0x83, c);
 277
 278         pci_write_config_byte(dev, 0x09, 0x01);
 279         pci_write_config_byte(dev, 0x0a, 0x06);
 280
 281         pci_read_config_byte(dev,0x83,&c);
 282         c &= 0x7f;
 283         pci_write_config_byte(dev, 0x83, c);
 284
 285         pci_read_config_byte(dev,0x84,&c);
 286         c |= 0x01;
 287         pci_write_config_byte(dev, 0x84, c);
 288 }
 289
 290 static void __devinit quirk_uli5229(struct pci_dev *dev)
 291 {
 292         unsigned short temp;
 293         pci_write_config_word(dev, 0x04, 0x0405);
 294         pci_read_config_word(dev, 0x4a, &temp);
 295         temp |= 0x1000;
 296         pci_write_config_word(dev, 0x4a, temp);
 297 }
 298
 299 static void __devinit early_uli5249(struct pci_dev *dev)
 300 {
 301         unsigned char temp;
 302         pci_write_config_word(dev, 0x04, 0x0007);
 303         pci_read_config_byte(dev, 0x7c, &temp);
 304         pci_write_config_byte(dev, 0x7c, 0x80);
 305         pci_write_config_byte(dev, 0x09, 0x01);
 306         pci_write_config_byte(dev, 0x7c, temp);
 307         dev->class |= 0x1;
 308 }
 309
 310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
 311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
 312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
 313 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
 314 #endif /* CONFIG_PCI */
 315
 316
 317 static void __init
 318 mpc86xx_hpcn_setup_arch(void)
 319 {
 320         struct device_node *np;
 321
 322         if (ppc_md.progress)
 323                 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
 324
 325         np = of_find_node_by_type(NULL, "cpu");
 326         if (np != 0) {
 327                 unsigned int *fp;
 328
 329                 fp = (int *)get_property(np, "clock-frequency", NULL);
 330                 if (fp != 0)
 331                         loops_per_jiffy = *fp / HZ;
 332                 else
 333                         loops_per_jiffy = 50000000 / HZ;
 334                 of_node_put(np);
 335         }
 336
 337 #ifdef CONFIG_PCI
 338         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
 339                 add_bridge(np);
 340
 341         ppc_md.pci_swizzle = common_swizzle;
 342         ppc_md.pci_map_irq = mpc86xx_map_irq;
 343         ppc_md.pci_exclude_device = mpc86xx_exclude_device;
 344 #endif
 345
 346         printk("MPC86xx HPCN board from Freescale Semiconductor\n");
 347
 348 #ifdef  CONFIG_ROOT_NFS
 349         ROOT_DEV = Root_NFS;
 350 #else
 351         ROOT_DEV = Root_HDA1;
 352 #endif
 353
 354 #ifdef CONFIG_SMP
 355         mpc86xx_smp_init();
 356 #endif
 357 }
 358
 359
 360 void
 361 mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
 362 {
 363         struct device_node *root;
 364         uint memsize = total_memory;
 365         const char *model = "";
 366         uint svid = mfspr(SPRN_SVR);
 367
 368         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 369
 370         root = of_find_node_by_path("/");
 371         if (root)
 372                 model = get_property(root, "model", NULL);
 373         seq_printf(m, "Machine\t\t: %s\n", model);
 374         of_node_put(root);
 375
 376         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 377         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 378 }
 379
 380
 381 /*
 382  * Called very early, device-tree isn't unflattened
 383  */
 384 static int __init mpc86xx_hpcn_probe(void)
 385 {
 386         unsigned long root = of_get_flat_dt_root();
 387
 388         if (of_flat_dt_is_compatible(root, "mpc86xx"))
 389                 return 1;       /* Looks good */
 390
 391         return 0;
 392 }
 393
 394
 395 void
 396 mpc86xx_restart(char *cmd)
 397 {
 398         void __iomem *rstcr;
 399
 400         rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
 401
 402         local_irq_disable();
 403
 404         /* Assert reset request to Reset Control Register */
 405         out_be32(rstcr, 0x2);
 406
 407         /* not reached */
 408 }
 409
 410
 411 long __init
 412 mpc86xx_time_init(void)
 413 {
 414         unsigned int temp;
 415
 416         /* Set the time base to zero */
 417         mtspr(SPRN_TBWL, 0);
 418         mtspr(SPRN_TBWU, 0);
 419
 420         temp = mfspr(SPRN_HID0);
 421         temp |= HID0_TBEN;
 422         mtspr(SPRN_HID0, temp);
 423         asm volatile("isync");
 424
 425         return 0;
 426 }
 427
 428
 429 define_machine(mpc86xx_hpcn) {
 430         .name                   = "MPC86xx HPCN",
 431         .probe                  = mpc86xx_hpcn_probe,
 432         .setup_arch             = mpc86xx_hpcn_setup_arch,
 433         .init_IRQ               = mpc86xx_hpcn_init_irq,
 434         .show_cpuinfo           = mpc86xx_hpcn_show_cpuinfo,
 435         .get_irq                = mpic_get_irq,
 436         .restart                = mpc86xx_restart,
 437         .time_init              = mpc86xx_time_init,
 438         .calibrate_decr         = generic_calibrate_decr,
 439         .progress               = udbg_progress,
 440 };