arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c

   1 /*
   2  * LocalPlus Bus FIFO driver for the Freescale MPC52xx.
   3  *
   4  * Copyright (C) 2009 Secret Lab Technologies Ltd.
   5  *
   6  * This file is released under the GPLv2
   7  *
   8  * Todo:
   9  * - Add support for multiple requests to be queued.
  10  */
  11
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/of.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/module.h>
  18 #include <asm/io.h>
  19 #include <asm/prom.h>
  20 #include <asm/mpc52xx.h>
  21 #include <asm/time.h>
  22
  23 #include <sysdev/bestcomm/bestcomm.h>
  24 #include <sysdev/bestcomm/bestcomm_priv.h>
  25 #include <sysdev/bestcomm/gen_bd.h>
  26
  27 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
  28 MODULE_DESCRIPTION("MPC5200 LocalPlus FIFO device driver");
  29 MODULE_LICENSE("GPL");
  30
  31 #define LPBFIFO_REG_PACKET_SIZE         (0x00)
  32 #define LPBFIFO_REG_START_ADDRESS       (0x04)
  33 #define LPBFIFO_REG_CONTROL             (0x08)
  34 #define LPBFIFO_REG_ENABLE              (0x0C)
  35 #define LPBFIFO_REG_BYTES_DONE_STATUS   (0x14)
  36 #define LPBFIFO_REG_FIFO_DATA           (0x40)
  37 #define LPBFIFO_REG_FIFO_STATUS         (0x44)
  38 #define LPBFIFO_REG_FIFO_CONTROL        (0x48)
  39 #define LPBFIFO_REG_FIFO_ALARM          (0x4C)
  40
  41 struct mpc52xx_lpbfifo {
  42         struct device *dev;
  43         phys_addr_t regs_phys;
  44         void __iomem *regs;
  45         int irq;
  46         spinlock_t lock;
  47
  48         struct bcom_task *bcom_tx_task;
  49         struct bcom_task *bcom_rx_task;
  50         struct bcom_task *bcom_cur_task;
  51
  52         /* Current state data */
  53         struct mpc52xx_lpbfifo_request *req;
  54         int dma_irqs_enabled;
  55 };
  56
  57 /* The MPC5200 has only one fifo, so only need one instance structure */
  58 static struct mpc52xx_lpbfifo lpbfifo;
  59
  60 /**
  61  * mpc52xx_lpbfifo_kick - Trigger the next block of data to be transferred
  62  */
  63 static void mpc52xx_lpbfifo_kick(struct mpc52xx_lpbfifo_request *req)
  64 {
  65         size_t transfer_size = req->size - req->pos;
  66         struct bcom_bd *bd;
  67         void __iomem *reg;
  68         u32 *data;
  69         int i;
  70         int bit_fields;
  71         int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
  72         int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
  73         int poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA;
  74
  75         /* Set and clear the reset bits; is good practice in User Manual */
  76         out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
  77
  78         /* set master enable bit */
  79         out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000001);
  80         if (!dma) {
  81                 /* While the FIFO can be setup for transfer sizes as large as
  82                  * 16M-1, the FIFO itself is only 512 bytes deep and it does
  83                  * not generate interrupts for FIFO full events (only transfer
  84                  * complete will raise an IRQ).  Therefore when not using
  85                  * Bestcomm to drive the FIFO it needs to either be polled, or
  86                  * transfers need to constrained to the size of the fifo.
  87                  *
  88                  * This driver restricts the size of the transfer
  89                  */
  90                 if (transfer_size > 512)
  91                         transfer_size = 512;
  92
  93                 /* Load the FIFO with data */
  94                 if (write) {
  95                         reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA;
  96                         data = req->data + req->pos;
  97                         for (i = 0; i < transfer_size; i += 4)
  98                                 out_be32(reg, *data++);
  99                 }
 100
 101                 /* Unmask both error and completion irqs */
 102                 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x00000301);
 103         } else {
 104                 /* Choose the correct direction
 105                  *
 106                  * Configure the watermarks so DMA will always complete correctly.
 107                  * It may be worth experimenting with the ALARM value to see if
 108                  * there is a performance impacit.  However, if it is wrong there
 109                  * is a risk of DMA not transferring the last chunk of data
 110                  */
 111                 if (write) {
 112                         out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1e4);
 113                         out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 7);
 114                         lpbfifo.bcom_cur_task = lpbfifo.bcom_tx_task;
 115                 } else {
 116                         out_be32(lpbfifo.regs + LPBFIFO_REG_FIFO_ALARM, 0x1ff);
 117                         out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 0);
 118                         lpbfifo.bcom_cur_task = lpbfifo.bcom_rx_task;
 119
 120                         if (poll_dma) {
 121                                 if (lpbfifo.dma_irqs_enabled) {
 122                                         disable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task));
 123                                         lpbfifo.dma_irqs_enabled = 0;
 124                                 }
 125                         } else {
 126                                 if (!lpbfifo.dma_irqs_enabled) {
 127                                         enable_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task));
 128                                         lpbfifo.dma_irqs_enabled = 1;
 129                                 }
 130                         }
 131                 }
 132
 133                 bd = bcom_prepare_next_buffer(lpbfifo.bcom_cur_task);
 134                 bd->status = transfer_size;
 135                 if (!write) {
 136                         /*
 137                          * In the DMA read case, the DMA doesn't complete,
 138                          * possibly due to incorrect watermarks in the ALARM
 139                          * and CONTROL regs. For now instead of trying to
 140                          * determine the right watermarks that will make this
 141                          * work, just increase the number of bytes the FIFO is
 142                          * expecting.
 143                          *
 144                          * When submitting another operation, the FIFO will get
 145                          * reset, so the condition of the FIFO waiting for a
 146                          * non-existent 4 bytes will get cleared.
 147                          */
 148                         transfer_size += 4; /* BLECH! */
 149                 }
 150                 bd->data[0] = req->data_phys + req->pos;
 151                 bcom_submit_next_buffer(lpbfifo.bcom_cur_task, NULL);
 152
 153                 /* error irq & master enabled bit */
 154                 bit_fields = 0x00000201;
 155
 156                 /* Unmask irqs */
 157                 if (write && (!poll_dma))
 158                         bit_fields |= 0x00000100; /* completion irq too */
 159                 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, bit_fields);
 160         }
 161
 162         /* Set transfer size, width, chip select and READ mode */
 163         out_be32(lpbfifo.regs + LPBFIFO_REG_START_ADDRESS,
 164                  req->offset + req->pos);
 165         out_be32(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, transfer_size);
 166
 167         bit_fields = req->cs << 24 | 0x000008;
 168         if (!write)
 169                 bit_fields |= 0x010000; /* read mode */
 170         out_be32(lpbfifo.regs + LPBFIFO_REG_CONTROL, bit_fields);
 171
 172         /* Kick it off */
 173         out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01);
 174         if (dma)
 175                 bcom_enable(lpbfifo.bcom_cur_task);
 176 }
 177
 178 /**
 179  * mpc52xx_lpbfifo_irq - IRQ handler for LPB FIFO
 180  *
 181  * On transmit, the dma completion irq triggers before the fifo completion
 182  * triggers.  Handle the dma completion here instead of the LPB FIFO Bestcomm
 183  * task completion irq because everything is not really done until the LPB FIFO
 184  * completion irq triggers.
 185  *
 186  * In other words:
 187  * For DMA, on receive, the "Fat Lady" is the bestcom completion irq. on
 188  * transmit, the fifo completion irq is the "Fat Lady". The opera (or in this
 189  * case the DMA/FIFO operation) is not finished until the "Fat Lady" sings.
 190  *
 191  * Reasons for entering this routine:
 192  * 1) PIO mode rx and tx completion irq
 193  * 2) DMA interrupt mode tx completion irq
 194  * 3) DMA polled mode tx
 195  *
 196  * Exit conditions:
 197  * 1) Transfer aborted
 198  * 2) FIFO complete without DMA; more data to do
 199  * 3) FIFO complete without DMA; all data transferred
 200  * 4) FIFO complete using DMA
 201  *
 202  * Condition 1 can occur regardless of whether or not DMA is used.
 203  * It requires executing the callback to report the error and exiting
 204  * immediately.
 205  *
 206  * Condition 2 requires programming the FIFO with the next block of data
 207  *
 208  * Condition 3 requires executing the callback to report completion
 209  *
 210  * Condition 4 means the same as 3, except that we also retrieve the bcom
 211  * buffer so DMA doesn't get clogged up.
 212  *
 213  * To make things trickier, the spinlock must be dropped before
 214  * executing the callback, otherwise we could end up with a deadlock
 215  * or nested spinlock condition.  The out path is non-trivial, so
 216  * extra fiddling is done to make sure all paths lead to the same
 217  * outbound code.
 218  */
 219 static irqreturn_t mpc52xx_lpbfifo_irq(int irq, void *dev_id)
 220 {
 221         struct mpc52xx_lpbfifo_request *req;
 222         u32 status = in_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS);
 223         void __iomem *reg;
 224         u32 *data;
 225         int count, i;
 226         int do_callback = 0;
 227         u32 ts;
 228         unsigned long flags;
 229         int dma, write, poll_dma;
 230
 231         spin_lock_irqsave(&lpbfifo.lock, flags);
 232         ts = get_tbl();
 233
 234         req = lpbfifo.req;
 235         if (!req) {
 236                 spin_unlock_irqrestore(&lpbfifo.lock, flags);
 237                 pr_err("bogus LPBFIFO IRQ\n");
 238                 return IRQ_HANDLED;
 239         }
 240
 241         dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
 242         write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
 243         poll_dma = req->flags & MPC52XX_LPBFIFO_FLAG_POLL_DMA;
 244
 245         if (dma && !write) {
 246                 spin_unlock_irqrestore(&lpbfifo.lock, flags);
 247                 pr_err("bogus LPBFIFO IRQ (dma and not writting)\n");
 248                 return IRQ_HANDLED;
 249         }
 250
 251         if ((status & 0x01) == 0) {
 252                 goto out;
 253         }
 254
 255         /* check abort bit */
 256         if (status & 0x10) {
 257                 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
 258                 do_callback = 1;
 259                 goto out;
 260         }
 261
 262         /* Read result from hardware */
 263         count = in_be32(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS);
 264         count &= 0x00ffffff;
 265
 266         if (!dma && !write) {
 267                 /* copy the data out of the FIFO */
 268                 reg = lpbfifo.regs + LPBFIFO_REG_FIFO_DATA;
 269                 data = req->data + req->pos;
 270                 for (i = 0; i < count; i += 4)
 271                         *data++ = in_be32(reg);
 272         }
 273
 274         /* Update transfer position and count */
 275         req->pos += count;
 276
 277         /* Decide what to do next */
 278         if (req->size - req->pos)
 279                 mpc52xx_lpbfifo_kick(req); /* more work to do */
 280         else
 281                 do_callback = 1;
 282
 283  out:
 284         /* Clear the IRQ */
 285         out_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS, 0x01);
 286
 287         if (dma && (status & 0x11)) {
 288                 /*
 289                  * Count the DMA as complete only when the FIFO completion
 290                  * status or abort bits are set.
 291                  *
 292                  * (status & 0x01) should always be the case except sometimes
 293                  * when using polled DMA.
 294                  *
 295                  * (status & 0x10) {transfer aborted}: This case needs more
 296                  * testing.
 297                  */
 298                 bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL);
 299         }
 300         req->last_byte = ((u8 *)req->data)[req->size - 1];
 301
 302         /* When the do_callback flag is set; it means the transfer is finished
 303          * so set the FIFO as idle */
 304         if (do_callback)
 305                 lpbfifo.req = NULL;
 306
 307         if (irq != 0) /* don't increment on polled case */
 308                 req->irq_count++;
 309
 310         req->irq_ticks += get_tbl() - ts;
 311         spin_unlock_irqrestore(&lpbfifo.lock, flags);
 312
 313         /* Spinlock is released; it is now safe to call the callback */
 314         if (do_callback && req->callback)
 315                 req->callback(req);
 316
 317         return IRQ_HANDLED;
 318 }
 319
 320 /**
 321  * mpc52xx_lpbfifo_bcom_irq - IRQ handler for LPB FIFO Bestcomm task
 322  *
 323  * Only used when receiving data.
 324  */
 325 static irqreturn_t mpc52xx_lpbfifo_bcom_irq(int irq, void *dev_id)
 326 {
 327         struct mpc52xx_lpbfifo_request *req;
 328         unsigned long flags;
 329         u32 status;
 330         u32 ts;
 331
 332         spin_lock_irqsave(&lpbfifo.lock, flags);
 333         ts = get_tbl();
 334
 335         req = lpbfifo.req;
 336         if (!req || (req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA)) {
 337                 spin_unlock_irqrestore(&lpbfifo.lock, flags);
 338                 return IRQ_HANDLED;
 339         }
 340
 341         if (irq != 0) /* don't increment on polled case */
 342                 req->irq_count++;
 343
 344         if (!bcom_buffer_done(lpbfifo.bcom_cur_task)) {
 345                 spin_unlock_irqrestore(&lpbfifo.lock, flags);
 346
 347                 req->buffer_not_done_cnt++;
 348                 if ((req->buffer_not_done_cnt % 1000) == 0)
 349                         pr_err("transfer stalled\n");
 350
 351                 return IRQ_HANDLED;
 352         }
 353
 354         bcom_retrieve_buffer(lpbfifo.bcom_cur_task, &status, NULL);
 355
 356         req->last_byte = ((u8 *)req->data)[req->size - 1];
 357
 358         req->pos = status & 0x00ffffff;
 359
 360         /* Mark the FIFO as idle */
 361         lpbfifo.req = NULL;
 362
 363         /* Release the lock before calling out to the callback. */
 364         req->irq_ticks += get_tbl() - ts;
 365         spin_unlock_irqrestore(&lpbfifo.lock, flags);
 366
 367         if (req->callback)
 368                 req->callback(req);
 369
 370         return IRQ_HANDLED;
 371 }
 372
 373 /**
 374  * mpc52xx_lpbfifo_bcom_poll - Poll for DMA completion
 375  */
 376 void mpc52xx_lpbfifo_poll(void)
 377 {
 378         struct mpc52xx_lpbfifo_request *req = lpbfifo.req;
 379         int dma = !(req->flags & MPC52XX_LPBFIFO_FLAG_NO_DMA);
 380         int write = req->flags & MPC52XX_LPBFIFO_FLAG_WRITE;
 381
 382         /*
 383          * For more information, see comments on the "Fat Lady"
 384          */
 385         if (dma && write)
 386                 mpc52xx_lpbfifo_irq(0, NULL);
 387         else
 388                 mpc52xx_lpbfifo_bcom_irq(0, NULL);
 389 }
 390 EXPORT_SYMBOL(mpc52xx_lpbfifo_poll);
 391
 392 /**
 393  * mpc52xx_lpbfifo_submit - Submit an LPB FIFO transfer request.
 394  * @req: Pointer to request structure
 395  */
 396 int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req)
 397 {
 398         unsigned long flags;
 399
 400         if (!lpbfifo.regs)
 401                 return -ENODEV;
 402
 403         spin_lock_irqsave(&lpbfifo.lock, flags);
 404
 405         /* If the req pointer is already set, then a transfer is in progress */
 406         if (lpbfifo.req) {
 407                 spin_unlock_irqrestore(&lpbfifo.lock, flags);
 408                 return -EBUSY;
 409         }
 410
 411         /* Setup the transfer */
 412         lpbfifo.req = req;
 413         req->irq_count = 0;
 414         req->irq_ticks = 0;
 415         req->buffer_not_done_cnt = 0;
 416         req->pos = 0;
 417
 418         mpc52xx_lpbfifo_kick(req);
 419         spin_unlock_irqrestore(&lpbfifo.lock, flags);
 420         return 0;
 421 }
 422 EXPORT_SYMBOL(mpc52xx_lpbfifo_submit);
 423
 424 void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req)
 425 {
 426         unsigned long flags;
 427
 428         spin_lock_irqsave(&lpbfifo.lock, flags);
 429         if (lpbfifo.req == req) {
 430                 /* Put it into reset and clear the state */
 431                 bcom_gen_bd_rx_reset(lpbfifo.bcom_rx_task);
 432                 bcom_gen_bd_tx_reset(lpbfifo.bcom_tx_task);
 433                 out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
 434                 lpbfifo.req = NULL;
 435         }
 436         spin_unlock_irqrestore(&lpbfifo.lock, flags);
 437 }
 438 EXPORT_SYMBOL(mpc52xx_lpbfifo_abort);
 439
 440 static int __devinit mpc52xx_lpbfifo_probe(struct platform_device *op)
 441 {
 442         struct resource res;
 443         int rc = -ENOMEM;
 444
 445         if (lpbfifo.dev != NULL)
 446                 return -ENOSPC;
 447
 448         lpbfifo.irq = irq_of_parse_and_map(op->dev.of_node, 0);
 449         if (!lpbfifo.irq)
 450                 return -ENODEV;
 451
 452         if (of_address_to_resource(op->dev.of_node, 0, &res))
 453                 return -ENODEV;
 454         lpbfifo.regs_phys = res.start;
 455         lpbfifo.regs = of_iomap(op->dev.of_node, 0);
 456         if (!lpbfifo.regs)
 457                 return -ENOMEM;
 458
 459         spin_lock_init(&lpbfifo.lock);
 460
 461         /* Put FIFO into reset */
 462         out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
 463
 464         /* Register the interrupt handler */
 465         rc = request_irq(lpbfifo.irq, mpc52xx_lpbfifo_irq, 0,
 466                          "mpc52xx-lpbfifo", &lpbfifo);
 467         if (rc)
 468                 goto err_irq;
 469
 470         /* Request the Bestcomm receive (fifo --> memory) task and IRQ */
 471         lpbfifo.bcom_rx_task =
 472                 bcom_gen_bd_rx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
 473                                     BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC,
 474                                     16*1024*1024);
 475         if (!lpbfifo.bcom_rx_task)
 476                 goto err_bcom_rx;
 477
 478         rc = request_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task),
 479                          mpc52xx_lpbfifo_bcom_irq, 0,
 480                          "mpc52xx-lpbfifo-rx", &lpbfifo);
 481         if (rc)
 482                 goto err_bcom_rx_irq;
 483
 484         lpbfifo.dma_irqs_enabled = 1;
 485
 486         /* Request the Bestcomm transmit (memory --> fifo) task and IRQ */
 487         lpbfifo.bcom_tx_task =
 488                 bcom_gen_bd_tx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
 489                                     BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC);
 490         if (!lpbfifo.bcom_tx_task)
 491                 goto err_bcom_tx;
 492
 493         lpbfifo.dev = &op->dev;
 494         return 0;
 495
 496  err_bcom_tx:
 497         free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
 498  err_bcom_rx_irq:
 499         bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
 500  err_bcom_rx:
 501  err_irq:
 502         iounmap(lpbfifo.regs);
 503         lpbfifo.regs = NULL;
 504
 505         dev_err(&op->dev, "mpc52xx_lpbfifo_probe() failed\n");
 506         return -ENODEV;
 507 }
 508
 509
 510 static int __devexit mpc52xx_lpbfifo_remove(struct platform_device *op)
 511 {
 512         if (lpbfifo.dev != &op->dev)
 513                 return 0;
 514
 515         /* Put FIFO in reset */
 516         out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
 517
 518         /* Release the bestcomm transmit task */
 519         free_irq(bcom_get_task_irq(lpbfifo.bcom_tx_task), &lpbfifo);
 520         bcom_gen_bd_tx_release(lpbfifo.bcom_tx_task);
 521
 522         /* Release the bestcomm receive task */
 523         free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
 524         bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
 525
 526         free_irq(lpbfifo.irq, &lpbfifo);
 527         iounmap(lpbfifo.regs);
 528         lpbfifo.regs = NULL;
 529         lpbfifo.dev = NULL;
 530
 531         return 0;
 532 }
 533
 534 static struct of_device_id mpc52xx_lpbfifo_match[] __devinitconst = {
 535         { .compatible = "fsl,mpc5200-lpbfifo", },
 536         {},
 537 };
 538
 539 static struct platform_driver mpc52xx_lpbfifo_driver = {
 540         .driver = {
 541                 .name = "mpc52xx-lpbfifo",
 542                 .owner = THIS_MODULE,
 543                 .of_match_table = mpc52xx_lpbfifo_match,
 544         },
 545         .probe = mpc52xx_lpbfifo_probe,
 546         .remove = __devexit_p(mpc52xx_lpbfifo_remove),
 547 };
 548
 549 /***********************************************************************
 550  * Module init/exit
 551  */
 552 static int __init mpc52xx_lpbfifo_init(void)
 553 {
 554         return platform_driver_register(&mpc52xx_lpbfifo_driver);
 555 }
 556 module_init(mpc52xx_lpbfifo_init);
 557
 558 static void __exit mpc52xx_lpbfifo_exit(void)
 559 {
 560         platform_driver_unregister(&mpc52xx_lpbfifo_driver);
 561 }
 562 module_exit(mpc52xx_lpbfifo_exit);