arch/powerpc/mm/hash_utils_64.c

   1 /*
   2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
   3  *   {mikejc|engebret}@us.ibm.com
   4  *
   5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
   6  *
   7  * SMP scalability work:
   8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *
  10  *    Module name: htab.c
  11  *
  12  *    Description:
  13  *      PowerPC Hashed Page Table functions
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version
  18  * 2 of the License, or (at your option) any later version.
  19  */
  20
  21 #undef DEBUG
  22 #undef DEBUG_LOW
  23
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/sched.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/stat.h>
  29 #include <linux/sysctl.h>
  30 #include <linux/ctype.h>
  31 #include <linux/cache.h>
  32 #include <linux/init.h>
  33 #include <linux/signal.h>
  34 #include <linux/memblock.h>
  35
  36 #include <asm/processor.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/mmu.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/page.h>
  41 #include <asm/types.h>
  42 #include <asm/system.h>
  43 #include <asm/uaccess.h>
  44 #include <asm/machdep.h>
  45 #include <asm/prom.h>
  46 #include <asm/abs_addr.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/io.h>
  49 #include <asm/eeh.h>
  50 #include <asm/tlb.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/cputable.h>
  53 #include <asm/sections.h>
  54 #include <asm/spu.h>
  55 #include <asm/udbg.h>
  56 #include <asm/code-patching.h>
  57
  58 #ifdef DEBUG
  59 #define DBG(fmt...) udbg_printf(fmt)
  60 #else
  61 #define DBG(fmt...)
  62 #endif
  63
  64 #ifdef DEBUG_LOW
  65 #define DBG_LOW(fmt...) udbg_printf(fmt)
  66 #else
  67 #define DBG_LOW(fmt...)
  68 #endif
  69
  70 #define KB (1024)
  71 #define MB (1024*KB)
  72 #define GB (1024L*MB)
  73
  74 /*
  75  * Note:  pte   --> Linux PTE
  76  *        HPTE  --> PowerPC Hashed Page Table Entry
  77  *
  78  * Execution context:
  79  *   htab_initialize is called with the MMU off (of course), but
  80  *   the kernel has been copied down to zero so it can directly
  81  *   reference global data.  At this point it is very difficult
  82  *   to print debug info.
  83  *
  84  */
  85
  86 #ifdef CONFIG_U3_DART
  87 extern unsigned long dart_tablebase;
  88 #endif /* CONFIG_U3_DART */
  89
  90 static unsigned long _SDR1;
  91 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  92
  93 struct hash_pte *htab_address;
  94 unsigned long htab_size_bytes;
  95 unsigned long htab_hash_mask;
  96 EXPORT_SYMBOL_GPL(htab_hash_mask);
  97 int mmu_linear_psize = MMU_PAGE_4K;
  98 int mmu_virtual_psize = MMU_PAGE_4K;
  99 int mmu_vmalloc_psize = MMU_PAGE_4K;
 100 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 101 int mmu_vmemmap_psize = MMU_PAGE_4K;
 102 #endif
 103 int mmu_io_psize = MMU_PAGE_4K;
 104 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
 105 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
 106 u16 mmu_slb_size = 64;
 107 EXPORT_SYMBOL_GPL(mmu_slb_size);
 108 #ifdef CONFIG_PPC_64K_PAGES
 109 int mmu_ci_restrictions;
 110 #endif
 111 #ifdef CONFIG_DEBUG_PAGEALLOC
 112 static u8 *linear_map_hash_slots;
 113 static unsigned long linear_map_hash_count;
 114 static DEFINE_SPINLOCK(linear_map_hash_lock);
 115 #endif /* CONFIG_DEBUG_PAGEALLOC */
 116
 117 /* There are definitions of page sizes arrays to be used when none
 118  * is provided by the firmware.
 119  */
 120
 121 /* Pre-POWER4 CPUs (4k pages only)
 122  */
 123 static struct mmu_psize_def mmu_psize_defaults_old[] = {
 124         [MMU_PAGE_4K] = {
 125                 .shift  = 12,
 126                 .sllp   = 0,
 127                 .penc   = 0,
 128                 .avpnm  = 0,
 129                 .tlbiel = 0,
 130         },
 131 };
 132
 133 /* POWER4, GPUL, POWER5
 134  *
 135  * Support for 16Mb large pages
 136  */
 137 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
 138         [MMU_PAGE_4K] = {
 139                 .shift  = 12,
 140                 .sllp   = 0,
 141                 .penc   = 0,
 142                 .avpnm  = 0,
 143                 .tlbiel = 1,
 144         },
 145         [MMU_PAGE_16M] = {
 146                 .shift  = 24,
 147                 .sllp   = SLB_VSID_L,
 148                 .penc   = 0,
 149                 .avpnm  = 0x1UL,
 150                 .tlbiel = 0,
 151         },
 152 };
 153
 154 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
 155 {
 156         unsigned long rflags = pteflags & 0x1fa;
 157
 158         /* _PAGE_EXEC -> NOEXEC */
 159         if ((pteflags & _PAGE_EXEC) == 0)
 160                 rflags |= HPTE_R_N;
 161
 162         /* PP bits. PAGE_USER is already PP bit 0x2, so we only
 163          * need to add in 0x1 if it's a read-only user page
 164          */
 165         if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
 166                                          (pteflags & _PAGE_DIRTY)))
 167                 rflags |= 1;
 168
 169         /* Always add C */
 170         return rflags | HPTE_R_C;
 171 }
 172
 173 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 174                       unsigned long pstart, unsigned long prot,
 175                       int psize, int ssize)
 176 {
 177         unsigned long vaddr, paddr;
 178         unsigned int step, shift;
 179         int ret = 0;
 180
 181         shift = mmu_psize_defs[psize].shift;
 182         step = 1 << shift;
 183
 184         prot = htab_convert_pte_flags(prot);
 185
 186         DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
 187             vstart, vend, pstart, prot, psize, ssize);
 188
 189         for (vaddr = vstart, paddr = pstart; vaddr < vend;
 190              vaddr += step, paddr += step) {
 191                 unsigned long hash, hpteg;
 192                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
 193                 unsigned long va = hpt_va(vaddr, vsid, ssize);
 194                 unsigned long tprot = prot;
 195
 196                 /* Make kernel text executable */
 197                 if (overlaps_kernel_text(vaddr, vaddr + step))
 198                         tprot &= ~HPTE_R_N;
 199
 200                 hash = hpt_hash(va, shift, ssize);
 201                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 202
 203                 BUG_ON(!ppc_md.hpte_insert);
 204                 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
 205                                          HPTE_V_BOLTED, psize, ssize);
 206
 207                 if (ret < 0)
 208                         break;
 209 #ifdef CONFIG_DEBUG_PAGEALLOC
 210                 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
 211                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
 212 #endif /* CONFIG_DEBUG_PAGEALLOC */
 213         }
 214         return ret < 0 ? ret : 0;
 215 }
 216
 217 #ifdef CONFIG_MEMORY_HOTPLUG
 218 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
 219                       int psize, int ssize)
 220 {
 221         unsigned long vaddr;
 222         unsigned int step, shift;
 223
 224         shift = mmu_psize_defs[psize].shift;
 225         step = 1 << shift;
 226
 227         if (!ppc_md.hpte_removebolted) {
 228                 printk(KERN_WARNING "Platform doesn't implement "
 229                                 "hpte_removebolted\n");
 230                 return -EINVAL;
 231         }
 232
 233         for (vaddr = vstart; vaddr < vend; vaddr += step)
 234                 ppc_md.hpte_removebolted(vaddr, psize, ssize);
 235
 236         return 0;
 237 }
 238 #endif /* CONFIG_MEMORY_HOTPLUG */
 239
 240 static int __init htab_dt_scan_seg_sizes(unsigned long node,
 241                                          const char *uname, int depth,
 242                                          void *data)
 243 {
 244         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 245         u32 *prop;
 246         unsigned long size = 0;
 247
 248         /* We are scanning "cpu" nodes only */
 249         if (type == NULL || strcmp(type, "cpu") != 0)
 250                 return 0;
 251
 252         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
 253                                           &size);
 254         if (prop == NULL)
 255                 return 0;
 256         for (; size >= 4; size -= 4, ++prop) {
 257                 if (prop[0] == 40) {
 258                         DBG("1T segment support detected\n");
 259                         cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
 260                         return 1;
 261                 }
 262         }
 263         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
 264         return 0;
 265 }
 266
 267 static void __init htab_init_seg_sizes(void)
 268 {
 269         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
 270 }
 271
 272 static int __init htab_dt_scan_page_sizes(unsigned long node,
 273                                           const char *uname, int depth,
 274                                           void *data)
 275 {
 276         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 277         u32 *prop;
 278         unsigned long size = 0;
 279
 280         /* We are scanning "cpu" nodes only */
 281         if (type == NULL || strcmp(type, "cpu") != 0)
 282                 return 0;
 283
 284         prop = (u32 *)of_get_flat_dt_prop(node,
 285                                           "ibm,segment-page-sizes", &size);
 286         if (prop != NULL) {
 287                 DBG("Page sizes from device-tree:\n");
 288                 size /= 4;
 289                 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
 290                 while(size > 0) {
 291                         unsigned int shift = prop[0];
 292                         unsigned int slbenc = prop[1];
 293                         unsigned int lpnum = prop[2];
 294                         unsigned int lpenc = 0;
 295                         struct mmu_psize_def *def;
 296                         int idx = -1;
 297
 298                         size -= 3; prop += 3;
 299                         while(size > 0 && lpnum) {
 300                                 if (prop[0] == shift)
 301                                         lpenc = prop[1];
 302                                 prop += 2; size -= 2;
 303                                 lpnum--;
 304                         }
 305                         switch(shift) {
 306                         case 0xc:
 307                                 idx = MMU_PAGE_4K;
 308                                 break;
 309                         case 0x10:
 310                                 idx = MMU_PAGE_64K;
 311                                 break;
 312                         case 0x14:
 313                                 idx = MMU_PAGE_1M;
 314                                 break;
 315                         case 0x18:
 316                                 idx = MMU_PAGE_16M;
 317                                 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
 318                                 break;
 319                         case 0x22:
 320                                 idx = MMU_PAGE_16G;
 321                                 break;
 322                         }
 323                         if (idx < 0)
 324                                 continue;
 325                         def = &mmu_psize_defs[idx];
 326                         def->shift = shift;
 327                         if (shift <= 23)
 328                                 def->avpnm = 0;
 329                         else
 330                                 def->avpnm = (1 << (shift - 23)) - 1;
 331                         def->sllp = slbenc;
 332                         def->penc = lpenc;
 333                         /* We don't know for sure what's up with tlbiel, so
 334                          * for now we only set it for 4K and 64K pages
 335                          */
 336                         if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
 337                                 def->tlbiel = 1;
 338                         else
 339                                 def->tlbiel = 0;
 340
 341                         DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
 342                             "tlbiel=%d, penc=%d\n",
 343                             idx, shift, def->sllp, def->avpnm, def->tlbiel,
 344                             def->penc);
 345                 }
 346                 return 1;
 347         }
 348         return 0;
 349 }
 350
 351 #ifdef CONFIG_HUGETLB_PAGE
 352 /* Scan for 16G memory blocks that have been set aside for huge pages
 353  * and reserve those blocks for 16G huge pages.
 354  */
 355 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
 356                                         const char *uname, int depth,
 357                                         void *data) {
 358         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 359         unsigned long *addr_prop;
 360         u32 *page_count_prop;
 361         unsigned int expected_pages;
 362         long unsigned int phys_addr;
 363         long unsigned int block_size;
 364
 365         /* We are scanning "memory" nodes only */
 366         if (type == NULL || strcmp(type, "memory") != 0)
 367                 return 0;
 368
 369         /* This property is the log base 2 of the number of virtual pages that
 370          * will represent this memory block. */
 371         page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
 372         if (page_count_prop == NULL)
 373                 return 0;
 374         expected_pages = (1 << page_count_prop[0]);
 375         addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
 376         if (addr_prop == NULL)
 377                 return 0;
 378         phys_addr = addr_prop[0];
 379         block_size = addr_prop[1];
 380         if (block_size != (16 * GB))
 381                 return 0;
 382         printk(KERN_INFO "Huge page(16GB) memory: "
 383                         "addr = 0x%lX size = 0x%lX pages = %d\n",
 384                         phys_addr, block_size, expected_pages);
 385         if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
 386                 memblock_reserve(phys_addr, block_size * expected_pages);
 387                 add_gpage(phys_addr, block_size, expected_pages);
 388         }
 389         return 0;
 390 }
 391 #endif /* CONFIG_HUGETLB_PAGE */
 392
 393 static void __init htab_init_page_sizes(void)
 394 {
 395         int rc;
 396
 397         /* Default to 4K pages only */
 398         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
 399                sizeof(mmu_psize_defaults_old));
 400
 401         /*
 402          * Try to find the available page sizes in the device-tree
 403          */
 404         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
 405         if (rc != 0)  /* Found */
 406                 goto found;
 407
 408         /*
 409          * Not in the device-tree, let's fallback on known size
 410          * list for 16M capable GP & GR
 411          */
 412         if (mmu_has_feature(MMU_FTR_16M_PAGE))
 413                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
 414                        sizeof(mmu_psize_defaults_gp));
 415  found:
 416 #ifndef CONFIG_DEBUG_PAGEALLOC
 417         /*
 418          * Pick a size for the linear mapping. Currently, we only support
 419          * 16M, 1M and 4K which is the default
 420          */
 421         if (mmu_psize_defs[MMU_PAGE_16M].shift)
 422                 mmu_linear_psize = MMU_PAGE_16M;
 423         else if (mmu_psize_defs[MMU_PAGE_1M].shift)
 424                 mmu_linear_psize = MMU_PAGE_1M;
 425 #endif /* CONFIG_DEBUG_PAGEALLOC */
 426
 427 #ifdef CONFIG_PPC_64K_PAGES
 428         /*
 429          * Pick a size for the ordinary pages. Default is 4K, we support
 430          * 64K for user mappings and vmalloc if supported by the processor.
 431          * We only use 64k for ioremap if the processor
 432          * (and firmware) support cache-inhibited large pages.
 433          * If not, we use 4k and set mmu_ci_restrictions so that
 434          * hash_page knows to switch processes that use cache-inhibited
 435          * mappings to 4k pages.
 436          */
 437         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
 438                 mmu_virtual_psize = MMU_PAGE_64K;
 439                 mmu_vmalloc_psize = MMU_PAGE_64K;
 440                 if (mmu_linear_psize == MMU_PAGE_4K)
 441                         mmu_linear_psize = MMU_PAGE_64K;
 442                 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
 443                         /*
 444                          * Don't use 64k pages for ioremap on pSeries, since
 445                          * that would stop us accessing the HEA ethernet.
 446                          */
 447                         if (!machine_is(pseries))
 448                                 mmu_io_psize = MMU_PAGE_64K;
 449                 } else
 450                         mmu_ci_restrictions = 1;
 451         }
 452 #endif /* CONFIG_PPC_64K_PAGES */
 453
 454 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 455         /* We try to use 16M pages for vmemmap if that is supported
 456          * and we have at least 1G of RAM at boot
 457          */
 458         if (mmu_psize_defs[MMU_PAGE_16M].shift &&
 459             memblock_phys_mem_size() >= 0x40000000)
 460                 mmu_vmemmap_psize = MMU_PAGE_16M;
 461         else if (mmu_psize_defs[MMU_PAGE_64K].shift)
 462                 mmu_vmemmap_psize = MMU_PAGE_64K;
 463         else
 464                 mmu_vmemmap_psize = MMU_PAGE_4K;
 465 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
 466
 467         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
 468                "virtual = %d, io = %d"
 469 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 470                ", vmemmap = %d"
 471 #endif
 472                "\n",
 473                mmu_psize_defs[mmu_linear_psize].shift,
 474                mmu_psize_defs[mmu_virtual_psize].shift,
 475                mmu_psize_defs[mmu_io_psize].shift
 476 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 477                ,mmu_psize_defs[mmu_vmemmap_psize].shift
 478 #endif
 479                );
 480
 481 #ifdef CONFIG_HUGETLB_PAGE
 482         /* Reserve 16G huge page memory sections for huge pages */
 483         of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
 484 #endif /* CONFIG_HUGETLB_PAGE */
 485 }
 486
 487 static int __init htab_dt_scan_pftsize(unsigned long node,
 488                                        const char *uname, int depth,
 489                                        void *data)
 490 {
 491         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 492         u32 *prop;
 493
 494         /* We are scanning "cpu" nodes only */
 495         if (type == NULL || strcmp(type, "cpu") != 0)
 496                 return 0;
 497
 498         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
 499         if (prop != NULL) {
 500                 /* pft_size[0] is the NUMA CEC cookie */
 501                 ppc64_pft_size = prop[1];
 502                 return 1;
 503         }
 504         return 0;
 505 }
 506
 507 static unsigned long __init htab_get_table_size(void)
 508 {
 509         unsigned long mem_size, rnd_mem_size, pteg_count, psize;
 510
 511         /* If hash size isn't already provided by the platform, we try to
 512          * retrieve it from the device-tree. If it's not there neither, we
 513          * calculate it now based on the total RAM size
 514          */
 515         if (ppc64_pft_size == 0)
 516                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
 517         if (ppc64_pft_size)
 518                 return 1UL << ppc64_pft_size;
 519
 520         /* round mem_size up to next power of 2 */
 521         mem_size = memblock_phys_mem_size();
 522         rnd_mem_size = 1UL << __ilog2(mem_size);
 523         if (rnd_mem_size < mem_size)
 524                 rnd_mem_size <<= 1;
 525
 526         /* # pages / 2 */
 527         psize = mmu_psize_defs[mmu_virtual_psize].shift;
 528         pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11);
 529
 530         return pteg_count << 7;
 531 }
 532
 533 #ifdef CONFIG_MEMORY_HOTPLUG
 534 int create_section_mapping(unsigned long start, unsigned long end)
 535 {
 536         return htab_bolt_mapping(start, end, __pa(start),
 537                                  pgprot_val(PAGE_KERNEL), mmu_linear_psize,
 538                                  mmu_kernel_ssize);
 539 }
 540
 541 int remove_section_mapping(unsigned long start, unsigned long end)
 542 {
 543         return htab_remove_mapping(start, end, mmu_linear_psize,
 544                         mmu_kernel_ssize);
 545 }
 546 #endif /* CONFIG_MEMORY_HOTPLUG */
 547
 548 #define FUNCTION_TEXT(A)        ((*(unsigned long *)(A)))
 549
 550 static void __init htab_finish_init(void)
 551 {
 552         extern unsigned int *htab_call_hpte_insert1;
 553         extern unsigned int *htab_call_hpte_insert2;
 554         extern unsigned int *htab_call_hpte_remove;
 555         extern unsigned int *htab_call_hpte_updatepp;
 556
 557 #ifdef CONFIG_PPC_HAS_HASH_64K
 558         extern unsigned int *ht64_call_hpte_insert1;
 559         extern unsigned int *ht64_call_hpte_insert2;
 560         extern unsigned int *ht64_call_hpte_remove;
 561         extern unsigned int *ht64_call_hpte_updatepp;
 562
 563         patch_branch(ht64_call_hpte_insert1,
 564                 FUNCTION_TEXT(ppc_md.hpte_insert),
 565                 BRANCH_SET_LINK);
 566         patch_branch(ht64_call_hpte_insert2,
 567                 FUNCTION_TEXT(ppc_md.hpte_insert),
 568                 BRANCH_SET_LINK);
 569         patch_branch(ht64_call_hpte_remove,
 570                 FUNCTION_TEXT(ppc_md.hpte_remove),
 571                 BRANCH_SET_LINK);
 572         patch_branch(ht64_call_hpte_updatepp,
 573                 FUNCTION_TEXT(ppc_md.hpte_updatepp),
 574                 BRANCH_SET_LINK);
 575
 576 #endif /* CONFIG_PPC_HAS_HASH_64K */
 577
 578         patch_branch(htab_call_hpte_insert1,
 579                 FUNCTION_TEXT(ppc_md.hpte_insert),
 580                 BRANCH_SET_LINK);
 581         patch_branch(htab_call_hpte_insert2,
 582                 FUNCTION_TEXT(ppc_md.hpte_insert),
 583                 BRANCH_SET_LINK);
 584         patch_branch(htab_call_hpte_remove,
 585                 FUNCTION_TEXT(ppc_md.hpte_remove),
 586                 BRANCH_SET_LINK);
 587         patch_branch(htab_call_hpte_updatepp,
 588                 FUNCTION_TEXT(ppc_md.hpte_updatepp),
 589                 BRANCH_SET_LINK);
 590 }
 591
 592 static void __init htab_initialize(void)
 593 {
 594         unsigned long table;
 595         unsigned long pteg_count;
 596         unsigned long prot;
 597         unsigned long base = 0, size = 0, limit;
 598         struct memblock_region *reg;
 599
 600         DBG(" -> htab_initialize()\n");
 601
 602         /* Initialize segment sizes */
 603         htab_init_seg_sizes();
 604
 605         /* Initialize page sizes */
 606         htab_init_page_sizes();
 607
 608         if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
 609                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
 610                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
 611                 printk(KERN_INFO "Using 1TB segments\n");
 612         }
 613
 614         /*
 615          * Calculate the required size of the htab.  We want the number of
 616          * PTEGs to equal one half the number of real pages.
 617          */
 618         htab_size_bytes = htab_get_table_size();
 619         pteg_count = htab_size_bytes >> 7;
 620
 621         htab_hash_mask = pteg_count - 1;
 622
 623         if (firmware_has_feature(FW_FEATURE_LPAR)) {
 624                 /* Using a hypervisor which owns the htab */
 625                 htab_address = NULL;
 626                 _SDR1 = 0;
 627         } else {
 628                 /* Find storage for the HPT.  Must be contiguous in
 629                  * the absolute address space. On cell we want it to be
 630                  * in the first 2 Gig so we can use it for IOMMU hacks.
 631                  */
 632                 if (machine_is(cell))
 633                         limit = 0x80000000;
 634                 else
 635                         limit = MEMBLOCK_ALLOC_ANYWHERE;
 636
 637                 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
 638
 639                 DBG("Hash table allocated at %lx, size: %lx\n", table,
 640                     htab_size_bytes);
 641
 642                 htab_address = abs_to_virt(table);
 643
 644                 /* htab absolute addr + encoded htabsize */
 645                 _SDR1 = table + __ilog2(pteg_count) - 11;
 646
 647                 /* Initialize the HPT with no entries */
 648                 memset((void *)table, 0, htab_size_bytes);
 649
 650                 /* Set SDR1 */
 651                 mtspr(SPRN_SDR1, _SDR1);
 652         }
 653
 654         prot = pgprot_val(PAGE_KERNEL);
 655
 656 #ifdef CONFIG_DEBUG_PAGEALLOC
 657         linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
 658         linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count,
 659                                                     1, ppc64_rma_size));
 660         memset(linear_map_hash_slots, 0, linear_map_hash_count);
 661 #endif /* CONFIG_DEBUG_PAGEALLOC */
 662
 663         /* On U3 based machines, we need to reserve the DART area and
 664          * _NOT_ map it to avoid cache paradoxes as it's remapped non
 665          * cacheable later on
 666          */
 667
 668         /* create bolted the linear mapping in the hash table */
 669         for_each_memblock(memory, reg) {
 670                 base = (unsigned long)__va(reg->base);
 671                 size = reg->size;
 672
 673                 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
 674                     base, size, prot);
 675
 676 #ifdef CONFIG_U3_DART
 677                 /* Do not map the DART space. Fortunately, it will be aligned
 678                  * in such a way that it will not cross two memblock regions and
 679                  * will fit within a single 16Mb page.
 680                  * The DART space is assumed to be a full 16Mb region even if
 681                  * we only use 2Mb of that space. We will use more of it later
 682                  * for AGP GART. We have to use a full 16Mb large page.
 683                  */
 684                 DBG("DART base: %lx\n", dart_tablebase);
 685
 686                 if (dart_tablebase != 0 && dart_tablebase >= base
 687                     && dart_tablebase < (base + size)) {
 688                         unsigned long dart_table_end = dart_tablebase + 16 * MB;
 689                         if (base != dart_tablebase)
 690                                 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
 691                                                         __pa(base), prot,
 692                                                         mmu_linear_psize,
 693                                                         mmu_kernel_ssize));
 694                         if ((base + size) > dart_table_end)
 695                                 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
 696                                                         base + size,
 697                                                         __pa(dart_table_end),
 698                                                          prot,
 699                                                          mmu_linear_psize,
 700                                                          mmu_kernel_ssize));
 701                         continue;
 702                 }
 703 #endif /* CONFIG_U3_DART */
 704                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
 705                                 prot, mmu_linear_psize, mmu_kernel_ssize));
 706         }
 707         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 708
 709         /*
 710          * If we have a memory_limit and we've allocated TCEs then we need to
 711          * explicitly map the TCE area at the top of RAM. We also cope with the
 712          * case that the TCEs start below memory_limit.
 713          * tce_alloc_start/end are 16MB aligned so the mapping should work
 714          * for either 4K or 16MB pages.
 715          */
 716         if (tce_alloc_start) {
 717                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
 718                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
 719
 720                 if (base + size >= tce_alloc_start)
 721                         tce_alloc_start = base + size + 1;
 722
 723                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
 724                                          __pa(tce_alloc_start), prot,
 725                                          mmu_linear_psize, mmu_kernel_ssize));
 726         }
 727
 728         htab_finish_init();
 729
 730         DBG(" <- htab_initialize()\n");
 731 }
 732 #undef KB
 733 #undef MB
 734
 735 void __init early_init_mmu(void)
 736 {
 737         /* Setup initial STAB address in the PACA */
 738         get_paca()->stab_real = __pa((u64)&initial_stab);
 739         get_paca()->stab_addr = (u64)&initial_stab;
 740
 741         /* Initialize the MMU Hash table and create the linear mapping
 742          * of memory. Has to be done before stab/slb initialization as
 743          * this is currently where the page size encoding is obtained
 744          */
 745         htab_initialize();
 746
 747         /* Initialize stab / SLB management except on iSeries
 748          */
 749         if (mmu_has_feature(MMU_FTR_SLB))
 750                 slb_initialize();
 751         else if (!firmware_has_feature(FW_FEATURE_ISERIES))
 752                 stab_initialize(get_paca()->stab_real);
 753 }
 754
 755 #ifdef CONFIG_SMP
 756 void __cpuinit early_init_mmu_secondary(void)
 757 {
 758         /* Initialize hash table for that CPU */
 759         if (!firmware_has_feature(FW_FEATURE_LPAR))
 760                 mtspr(SPRN_SDR1, _SDR1);
 761
 762         /* Initialize STAB/SLB. We use a virtual address as it works
 763          * in real mode on pSeries and we want a virtual address on
 764          * iSeries anyway
 765          */
 766         if (mmu_has_feature(MMU_FTR_SLB))
 767                 slb_initialize();
 768         else
 769                 stab_initialize(get_paca()->stab_addr);
 770 }
 771 #endif /* CONFIG_SMP */
 772
 773 /*
 774  * Called by asm hashtable.S for doing lazy icache flush
 775  */
 776 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
 777 {
 778         struct page *page;
 779
 780         if (!pfn_valid(pte_pfn(pte)))
 781                 return pp;
 782
 783         page = pte_page(pte);
 784
 785         /* page is dirty */
 786         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
 787                 if (trap == 0x400) {
 788                         flush_dcache_icache_page(page);
 789                         set_bit(PG_arch_1, &page->flags);
 790                 } else
 791                         pp |= HPTE_R_N;
 792         }
 793         return pp;
 794 }
 795
 796 #ifdef CONFIG_PPC_MM_SLICES
 797 unsigned int get_paca_psize(unsigned long addr)
 798 {
 799         unsigned long index, slices;
 800
 801         if (addr < SLICE_LOW_TOP) {
 802                 slices = get_paca()->context.low_slices_psize;
 803                 index = GET_LOW_SLICE_INDEX(addr);
 804         } else {
 805                 slices = get_paca()->context.high_slices_psize;
 806                 index = GET_HIGH_SLICE_INDEX(addr);
 807         }
 808         return (slices >> (index * 4)) & 0xF;
 809 }
 810
 811 #else
 812 unsigned int get_paca_psize(unsigned long addr)
 813 {
 814         return get_paca()->context.user_psize;
 815 }
 816 #endif
 817
 818 /*
 819  * Demote a segment to using 4k pages.
 820  * For now this makes the whole process use 4k pages.
 821  */
 822 #ifdef CONFIG_PPC_64K_PAGES
 823 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
 824 {
 825         if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
 826                 return;
 827         slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
 828 #ifdef CONFIG_SPU_BASE
 829         spu_flush_all_slbs(mm);
 830 #endif
 831         if (get_paca_psize(addr) != MMU_PAGE_4K) {
 832                 get_paca()->context = mm->context;
 833                 slb_flush_and_rebolt();
 834         }
 835 }
 836 #endif /* CONFIG_PPC_64K_PAGES */
 837
 838 #ifdef CONFIG_PPC_SUBPAGE_PROT
 839 /*
 840  * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
 841  * Userspace sets the subpage permissions using the subpage_prot system call.
 842  *
 843  * Result is 0: full permissions, _PAGE_RW: read-only,
 844  * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
 845  */
 846 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
 847 {
 848         struct subpage_prot_table *spt = &mm->context.spt;
 849         u32 spp = 0;
 850         u32 **sbpm, *sbpp;
 851
 852         if (ea >= spt->maxaddr)
 853                 return 0;
 854         if (ea < 0x100000000) {
 855                 /* addresses below 4GB use spt->low_prot */
 856                 sbpm = spt->low_prot;
 857         } else {
 858                 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
 859                 if (!sbpm)
 860                         return 0;
 861         }
 862         sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
 863         if (!sbpp)
 864                 return 0;
 865         spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
 866
 867         /* extract 2-bit bitfield for this 4k subpage */
 868         spp >>= 30 - 2 * ((ea >> 12) & 0xf);
 869
 870         /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
 871         spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
 872         return spp;
 873 }
 874
 875 #else /* CONFIG_PPC_SUBPAGE_PROT */
 876 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
 877 {
 878         return 0;
 879 }
 880 #endif
 881
 882 void hash_failure_debug(unsigned long ea, unsigned long access,
 883                         unsigned long vsid, unsigned long trap,
 884                         int ssize, int psize, unsigned long pte)
 885 {
 886         if (!printk_ratelimit())
 887                 return;
 888         pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
 889                 ea, access, current->comm);
 890         pr_info("    trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
 891                 trap, vsid, ssize, psize, pte);
 892 }
 893
 894 /* Result code is:
 895  *  0 - handled
 896  *  1 - normal page fault
 897  * -1 - critical hash insertion error
 898  * -2 - access not permitted by subpage protection mechanism
 899  */
 900 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 901 {
 902         pgd_t *pgdir;
 903         unsigned long vsid;
 904         struct mm_struct *mm;
 905         pte_t *ptep;
 906         unsigned hugeshift;
 907         const struct cpumask *tmp;
 908         int rc, user_region = 0, local = 0;
 909         int psize, ssize;
 910
 911         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
 912                 ea, access, trap);
 913
 914         if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
 915                 DBG_LOW(" out of pgtable range !\n");
 916                 return 1;
 917         }
 918
 919         /* Get region & vsid */
 920         switch (REGION_ID(ea)) {
 921         case USER_REGION_ID:
 922                 user_region = 1;
 923                 mm = current->mm;
 924                 if (! mm) {
 925                         DBG_LOW(" user region with no mm !\n");
 926                         return 1;
 927                 }
 928                 psize = get_slice_psize(mm, ea);
 929                 ssize = user_segment_size(ea);
 930                 vsid = get_vsid(mm->context.id, ea, ssize);
 931                 break;
 932         case VMALLOC_REGION_ID:
 933                 mm = &init_mm;
 934                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
 935                 if (ea < VMALLOC_END)
 936                         psize = mmu_vmalloc_psize;
 937                 else
 938                         psize = mmu_io_psize;
 939                 ssize = mmu_kernel_ssize;
 940                 break;
 941         default:
 942                 /* Not a valid range
 943                  * Send the problem up to do_page_fault
 944                  */
 945                 return 1;
 946         }
 947         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
 948
 949         /* Get pgdir */
 950         pgdir = mm->pgd;
 951         if (pgdir == NULL)
 952                 return 1;
 953
 954         /* Check CPU locality */
 955         tmp = cpumask_of(smp_processor_id());
 956         if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
 957                 local = 1;
 958
 959 #ifndef CONFIG_PPC_64K_PAGES
 960         /* If we use 4K pages and our psize is not 4K, then we might
 961          * be hitting a special driver mapping, and need to align the
 962          * address before we fetch the PTE.
 963          *
 964          * It could also be a hugepage mapping, in which case this is
 965          * not necessary, but it's not harmful, either.
 966          */
 967         if (psize != MMU_PAGE_4K)
 968                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
 969 #endif /* CONFIG_PPC_64K_PAGES */
 970
 971         /* Get PTE and page size from page tables */
 972         ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift);
 973         if (ptep == NULL || !pte_present(*ptep)) {
 974                 DBG_LOW(" no PTE !\n");
 975                 return 1;
 976         }
 977
 978         /* Add _PAGE_PRESENT to the required access perm */
 979         access |= _PAGE_PRESENT;
 980
 981         /* Pre-check access permissions (will be re-checked atomically
 982          * in __hash_page_XX but this pre-check is a fast path
 983          */
 984         if (access & ~pte_val(*ptep)) {
 985                 DBG_LOW(" no access !\n");
 986                 return 1;
 987         }
 988
 989 #ifdef CONFIG_HUGETLB_PAGE
 990         if (hugeshift)
 991                 return __hash_page_huge(ea, access, vsid, ptep, trap, local,
 992                                         ssize, hugeshift, psize);
 993 #endif /* CONFIG_HUGETLB_PAGE */
 994
 995 #ifndef CONFIG_PPC_64K_PAGES
 996         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
 997 #else
 998         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
 999                 pte_val(*(ptep + PTRS_PER_PTE)));
1000 #endif
1001         /* Do actual hashing */
1002 #ifdef CONFIG_PPC_64K_PAGES
1003         /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1004         if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1005                 demote_segment_4k(mm, ea);
1006                 psize = MMU_PAGE_4K;
1007         }
1008
1009         /* If this PTE is non-cacheable and we have restrictions on
1010          * using non cacheable large pages, then we switch to 4k
1011          */
1012         if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
1013             (pte_val(*ptep) & _PAGE_NO_CACHE)) {
1014                 if (user_region) {
1015                         demote_segment_4k(mm, ea);
1016                         psize = MMU_PAGE_4K;
1017                 } else if (ea < VMALLOC_END) {
1018                         /*
1019                          * some driver did a non-cacheable mapping
1020                          * in vmalloc space, so switch vmalloc
1021                          * to 4k pages
1022                          */
1023                         printk(KERN_ALERT "Reducing vmalloc segment "
1024                                "to 4kB pages because of "
1025                                "non-cacheable mapping\n");
1026                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1027 #ifdef CONFIG_SPU_BASE
1028                         spu_flush_all_slbs(mm);
1029 #endif
1030                 }
1031         }
1032         if (user_region) {
1033                 if (psize != get_paca_psize(ea)) {
1034                         get_paca()->context = mm->context;
1035                         slb_flush_and_rebolt();
1036                 }
1037         } else if (get_paca()->vmalloc_sllp !=
1038                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1039                 get_paca()->vmalloc_sllp =
1040                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
1041                 slb_vmalloc_update();
1042         }
1043 #endif /* CONFIG_PPC_64K_PAGES */
1044
1045 #ifdef CONFIG_PPC_HAS_HASH_64K
1046         if (psize == MMU_PAGE_64K)
1047                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1048         else
1049 #endif /* CONFIG_PPC_HAS_HASH_64K */
1050         {
1051                 int spp = subpage_protection(mm, ea);
1052                 if (access & spp)
1053                         rc = -2;
1054                 else
1055                         rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1056                                             local, ssize, spp);
1057         }
1058
1059         /* Dump some info in case of hash insertion failure, they should
1060          * never happen so it is really useful to know if/when they do
1061          */
1062         if (rc == -1)
1063                 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1064                                    pte_val(*ptep));
1065 #ifndef CONFIG_PPC_64K_PAGES
1066         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1067 #else
1068         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1069                 pte_val(*(ptep + PTRS_PER_PTE)));
1070 #endif
1071         DBG_LOW(" -> rc=%d\n", rc);
1072         return rc;
1073 }
1074 EXPORT_SYMBOL_GPL(hash_page);
1075
1076 void hash_preload(struct mm_struct *mm, unsigned long ea,
1077                   unsigned long access, unsigned long trap)
1078 {
1079         unsigned long vsid;
1080         pgd_t *pgdir;
1081         pte_t *ptep;
1082         unsigned long flags;
1083         int rc, ssize, local = 0;
1084
1085         BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1086
1087 #ifdef CONFIG_PPC_MM_SLICES
1088         /* We only prefault standard pages for now */
1089         if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1090                 return;
1091 #endif
1092
1093         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1094                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1095
1096         /* Get Linux PTE if available */
1097         pgdir = mm->pgd;
1098         if (pgdir == NULL)
1099                 return;
1100         ptep = find_linux_pte(pgdir, ea);
1101         if (!ptep)
1102                 return;
1103
1104 #ifdef CONFIG_PPC_64K_PAGES
1105         /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1106          * a 64K kernel), then we don't preload, hash_page() will take
1107          * care of it once we actually try to access the page.
1108          * That way we don't have to duplicate all of the logic for segment
1109          * page size demotion here
1110          */
1111         if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1112                 return;
1113 #endif /* CONFIG_PPC_64K_PAGES */
1114
1115         /* Get VSID */
1116         ssize = user_segment_size(ea);
1117         vsid = get_vsid(mm->context.id, ea, ssize);
1118
1119         /* Hash doesn't like irqs */
1120         local_irq_save(flags);
1121
1122         /* Is that local to this CPU ? */
1123         if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1124                 local = 1;
1125
1126         /* Hash it in */
1127 #ifdef CONFIG_PPC_HAS_HASH_64K
1128         if (mm->context.user_psize == MMU_PAGE_64K)
1129                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1130         else
1131 #endif /* CONFIG_PPC_HAS_HASH_64K */
1132                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1133                                     subpage_protection(mm, ea));
1134
1135         /* Dump some info in case of hash insertion failure, they should
1136          * never happen so it is really useful to know if/when they do
1137          */
1138         if (rc == -1)
1139                 hash_failure_debug(ea, access, vsid, trap, ssize,
1140                                    mm->context.user_psize, pte_val(*ptep));
1141
1142         local_irq_restore(flags);
1143 }
1144
1145 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1146  *          do not forget to update the assembly call site !
1147  */
1148 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1149                      int local)
1150 {
1151         unsigned long hash, index, shift, hidx, slot;
1152
1153         DBG_LOW("flush_hash_page(va=%016lx)\n", va);
1154         pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1155                 hash = hpt_hash(va, shift, ssize);
1156                 hidx = __rpte_to_hidx(pte, index);
1157                 if (hidx & _PTEIDX_SECONDARY)
1158                         hash = ~hash;
1159                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1160                 slot += hidx & _PTEIDX_GROUP_IX;
1161                 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1162                 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1163         } pte_iterate_hashed_end();
1164 }
1165
1166 void flush_hash_range(unsigned long number, int local)
1167 {
1168         if (ppc_md.flush_hash_range)
1169                 ppc_md.flush_hash_range(number, local);
1170         else {
1171                 int i;
1172                 struct ppc64_tlb_batch *batch =
1173                         &__get_cpu_var(ppc64_tlb_batch);
1174
1175                 for (i = 0; i < number; i++)
1176                         flush_hash_page(batch->vaddr[i], batch->pte[i],
1177                                         batch->psize, batch->ssize, local);
1178         }
1179 }
1180
1181 /*
1182  * low_hash_fault is called when we the low level hash code failed
1183  * to instert a PTE due to an hypervisor error
1184  */
1185 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1186 {
1187         if (user_mode(regs)) {
1188 #ifdef CONFIG_PPC_SUBPAGE_PROT
1189                 if (rc == -2)
1190                         _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1191                 else
1192 #endif
1193                         _exception(SIGBUS, regs, BUS_ADRERR, address);
1194         } else
1195                 bad_page_fault(regs, address, SIGBUS);
1196 }
1197
1198 #ifdef CONFIG_DEBUG_PAGEALLOC
1199 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1200 {
1201         unsigned long hash, hpteg;
1202         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1203         unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1204         unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1205         int ret;
1206
1207         hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1208         hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1209
1210         ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1211                                  mode, HPTE_V_BOLTED,
1212                                  mmu_linear_psize, mmu_kernel_ssize);
1213         BUG_ON (ret < 0);
1214         spin_lock(&linear_map_hash_lock);
1215         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1216         linear_map_hash_slots[lmi] = ret | 0x80;
1217         spin_unlock(&linear_map_hash_lock);
1218 }
1219
1220 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1221 {
1222         unsigned long hash, hidx, slot;
1223         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1224         unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1225
1226         hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1227         spin_lock(&linear_map_hash_lock);
1228         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1229         hidx = linear_map_hash_slots[lmi] & 0x7f;
1230         linear_map_hash_slots[lmi] = 0;
1231         spin_unlock(&linear_map_hash_lock);
1232         if (hidx & _PTEIDX_SECONDARY)
1233                 hash = ~hash;
1234         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1235         slot += hidx & _PTEIDX_GROUP_IX;
1236         ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1237 }
1238
1239 void kernel_map_pages(struct page *page, int numpages, int enable)
1240 {
1241         unsigned long flags, vaddr, lmi;
1242         int i;
1243
1244         local_irq_save(flags);
1245         for (i = 0; i < numpages; i++, page++) {
1246                 vaddr = (unsigned long)page_address(page);
1247                 lmi = __pa(vaddr) >> PAGE_SHIFT;
1248                 if (lmi >= linear_map_hash_count)
1249                         continue;
1250                 if (enable)
1251                         kernel_map_linear_page(vaddr, lmi);
1252                 else
1253                         kernel_unmap_linear_page(vaddr, lmi);
1254         }
1255         local_irq_restore(flags);
1256 }
1257 #endif /* CONFIG_DEBUG_PAGEALLOC */
1258
1259 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
1260                                 phys_addr_t first_memblock_size)
1261 {
1262         /* We don't currently support the first MEMBLOCK not mapping 0
1263          * physical on those processors
1264          */
1265         BUG_ON(first_memblock_base != 0);
1266
1267         /* On LPAR systems, the first entry is our RMA region,
1268          * non-LPAR 64-bit hash MMU systems don't have a limitation
1269          * on real mode access, but using the first entry works well
1270          * enough. We also clamp it to 1G to avoid some funky things
1271          * such as RTAS bugs etc...
1272          */
1273         ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1274
1275         /* Finally limit subsequent allocations */
1276         memblock_set_current_limit(ppc64_rma_size);
1277 }