arch/powerpc/kernel/vdso32/sigtramp.S

   1 /*
   2  * Signal trampolines for 32 bits processes in a ppc64 kernel for
   3  * use in the vDSO
   4  *
   5  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
   6  * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13 #include <asm/processor.h>
  14 #include <asm/ppc_asm.h>
  15 #include <asm/unistd.h>
  16 #include <asm/vdso.h>
  17
  18         .text
  19
  20 /* The nop here is a hack.  The dwarf2 unwind routines subtract 1 from
  21    the return address to get an address in the middle of the presumed
  22    call instruction.  Since we don't have a call here, we artifically
  23    extend the range covered by the unwind info by adding a nop before
  24    the real start.  */
  25         nop
  26 V_FUNCTION_BEGIN(__kernel_sigtramp32)
  27 .Lsig_start = . - 4
  28         li      r0,__NR_sigreturn
  29         sc
  30 .Lsig_end:
  31 V_FUNCTION_END(__kernel_sigtramp32)
  32
  33 .Lsigrt_start:
  34         nop
  35 V_FUNCTION_BEGIN(__kernel_sigtramp_rt32)
  36         li      r0,__NR_rt_sigreturn
  37         sc
  38 .Lsigrt_end:
  39 V_FUNCTION_END(__kernel_sigtramp_rt32)
  40
  41         .section .eh_frame,"a",@progbits
  42
  43 /* Register r1 can be found at offset 4 of a pt_regs structure.
  44    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
  45 #define cfa_save \
  46   .byte 0x0f;                   /* DW_CFA_def_cfa_expression */         \
  47   .uleb128 9f - 1f;             /*   length */                          \
  48 1:                                                                      \
  49   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  50   .byte 0x06;                   /*     DW_OP_deref */                   \
  51   .byte 0x23; .uleb128 RSIZE;   /*     DW_OP_plus_uconst */             \
  52   .byte 0x06;                   /*     DW_OP_deref */                   \
  53 9:
  54
  55 /* Register REGNO can be found at offset OFS of a pt_regs structure.
  56    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
  57 #define rsave(regno, ofs) \
  58   .byte 0x10;                   /* DW_CFA_expression */                 \
  59   .uleb128 regno;               /*   regno */                           \
  60   .uleb128 9f - 1f;             /*   length */                          \
  61 1:                                                                      \
  62   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  63   .byte 0x06;                   /*     DW_OP_deref */                   \
  64   .ifne ofs;                                                            \
  65     .byte 0x23; .uleb128 ofs;   /*     DW_OP_plus_uconst */             \
  66   .endif;                                                               \
  67 9:
  68
  69 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
  70    of the VMX reg struct.  The VMX reg struct is at offset VREGS of
  71    the pt_regs struct.  This macro is for REGNO == 0, and contains
  72    'subroutines' that the other macros jump to.  */
  73 #define vsave_msr0(regno) \
  74   .byte 0x10;                   /* DW_CFA_expression */                 \
  75   .uleb128 regno + 77;          /*   regno */                           \
  76   .uleb128 9f - 1f;             /*   length */                          \
  77 1:                                                                      \
  78   .byte 0x30 + regno;           /*     DW_OP_lit0 */                    \
  79 2:                                                                      \
  80   .byte 0x40;                   /*     DW_OP_lit16 */                   \
  81   .byte 0x1e;                   /*     DW_OP_mul */                     \
  82 3:                                                                      \
  83   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  84   .byte 0x06;                   /*     DW_OP_deref */                   \
  85   .byte 0x12;                   /*     DW_OP_dup */                     \
  86   .byte 0x23;                   /*     DW_OP_plus_uconst */             \
  87     .uleb128 33*RSIZE;          /*       msr offset */                  \
  88   .byte 0x06;                   /*     DW_OP_deref */                   \
  89   .byte 0x0c; .long 1 << 25;    /*     DW_OP_const4u */                 \
  90   .byte 0x1a;                   /*     DW_OP_and */                     \
  91   .byte 0x12;                   /*     DW_OP_dup, ret 0 if bra taken */ \
  92   .byte 0x30;                   /*     DW_OP_lit0 */                    \
  93   .byte 0x29;                   /*     DW_OP_eq */                      \
  94   .byte 0x28; .short 0x7fff;    /*     DW_OP_bra to end */              \
  95   .byte 0x13;                   /*     DW_OP_drop, pop the 0 */         \
  96   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */             \
  97   .byte 0x22;                   /*     DW_OP_plus */                    \
  98   .byte 0x2f; .short 0x7fff;    /*     DW_OP_skip to end */             \
  99 9:
 100
 101 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
 102    of the VMX reg struct.  REGNO is 1 thru 31.  */
 103 #define vsave_msr1(regno) \
 104   .byte 0x10;                   /* DW_CFA_expression */                 \
 105   .uleb128 regno + 77;          /*   regno */                           \
 106   .uleb128 9f - 1f;             /*   length */                          \
 107 1:                                                                      \
 108   .byte 0x30 + regno;           /*     DW_OP_lit n */                   \
 109   .byte 0x2f; .short 2b - 9f;   /*     DW_OP_skip */                    \
 110 9:
 111
 112 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
 113    the VMX save block.  */
 114 #define vsave_msr2(regno, ofs) \
 115   .byte 0x10;                   /* DW_CFA_expression */                 \
 116   .uleb128 regno + 77;          /*   regno */                           \
 117   .uleb128 9f - 1f;             /*   length */                          \
 118 1:                                                                      \
 119   .byte 0x0a; .short ofs;       /*     DW_OP_const2u */                 \
 120   .byte 0x2f; .short 3b - 9f;   /*     DW_OP_skip */                    \
 121 9:
 122
 123 /* VMX register REGNO is at offset OFS of the VMX save area.  */
 124 #define vsave(regno, ofs) \
 125   .byte 0x10;                   /* DW_CFA_expression */                 \
 126   .uleb128 regno + 77;          /*   regno */                           \
 127   .uleb128 9f - 1f;             /*   length */                          \
 128 1:                                                                      \
 129   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
 130   .byte 0x06;                   /*     DW_OP_deref */                   \
 131   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */             \
 132   .byte 0x23; .uleb128 ofs;     /*     DW_OP_plus_uconst */             \
 133 9:
 134
 135 /* This is where the pt_regs pointer can be found on the stack.  */
 136 #define PTREGS 64+28
 137
 138 /* Size of regs.  */
 139 #define RSIZE 4
 140
 141 /* This is the offset of the VMX regs.  */
 142 #define VREGS 48*RSIZE+34*8
 143
 144 /* Describe where general purpose regs are saved.  */
 145 #define EH_FRAME_GEN \
 146   cfa_save;                                                             \
 147   rsave ( 0,  0*RSIZE);                                                 \
 148   rsave ( 2,  2*RSIZE);                                                 \
 149   rsave ( 3,  3*RSIZE);                                                 \
 150   rsave ( 4,  4*RSIZE);                                                 \
 151   rsave ( 5,  5*RSIZE);                                                 \
 152   rsave ( 6,  6*RSIZE);                                                 \
 153   rsave ( 7,  7*RSIZE);                                                 \
 154   rsave ( 8,  8*RSIZE);                                                 \
 155   rsave ( 9,  9*RSIZE);                                                 \
 156   rsave (10, 10*RSIZE);                                                 \
 157   rsave (11, 11*RSIZE);                                                 \
 158   rsave (12, 12*RSIZE);                                                 \
 159   rsave (13, 13*RSIZE);                                                 \
 160   rsave (14, 14*RSIZE);                                                 \
 161   rsave (15, 15*RSIZE);                                                 \
 162   rsave (16, 16*RSIZE);                                                 \
 163   rsave (17, 17*RSIZE);                                                 \
 164   rsave (18, 18*RSIZE);                                                 \
 165   rsave (19, 19*RSIZE);                                                 \
 166   rsave (20, 20*RSIZE);                                                 \
 167   rsave (21, 21*RSIZE);                                                 \
 168   rsave (22, 22*RSIZE);                                                 \
 169   rsave (23, 23*RSIZE);                                                 \
 170   rsave (24, 24*RSIZE);                                                 \
 171   rsave (25, 25*RSIZE);                                                 \
 172   rsave (26, 26*RSIZE);                                                 \
 173   rsave (27, 27*RSIZE);                                                 \
 174   rsave (28, 28*RSIZE);                                                 \
 175   rsave (29, 29*RSIZE);                                                 \
 176   rsave (30, 30*RSIZE);                                                 \
 177   rsave (31, 31*RSIZE);                                                 \
 178   rsave (67, 32*RSIZE);         /* ap, used as temp for nip */          \
 179   rsave (65, 36*RSIZE);         /* lr */                                \
 180   rsave (70, 38*RSIZE)          /* cr */
 181
 182 /* Describe where the FP regs are saved.  */
 183 #define EH_FRAME_FP \
 184   rsave (32, 48*RSIZE +  0*8);                                          \
 185   rsave (33, 48*RSIZE +  1*8);                                          \
 186   rsave (34, 48*RSIZE +  2*8);                                          \
 187   rsave (35, 48*RSIZE +  3*8);                                          \
 188   rsave (36, 48*RSIZE +  4*8);                                          \
 189   rsave (37, 48*RSIZE +  5*8);                                          \
 190   rsave (38, 48*RSIZE +  6*8);                                          \
 191   rsave (39, 48*RSIZE +  7*8);                                          \
 192   rsave (40, 48*RSIZE +  8*8);                                          \
 193   rsave (41, 48*RSIZE +  9*8);                                          \
 194   rsave (42, 48*RSIZE + 10*8);                                          \
 195   rsave (43, 48*RSIZE + 11*8);                                          \
 196   rsave (44, 48*RSIZE + 12*8);                                          \
 197   rsave (45, 48*RSIZE + 13*8);                                          \
 198   rsave (46, 48*RSIZE + 14*8);                                          \
 199   rsave (47, 48*RSIZE + 15*8);                                          \
 200   rsave (48, 48*RSIZE + 16*8);                                          \
 201   rsave (49, 48*RSIZE + 17*8);                                          \
 202   rsave (50, 48*RSIZE + 18*8);                                          \
 203   rsave (51, 48*RSIZE + 19*8);                                          \
 204   rsave (52, 48*RSIZE + 20*8);                                          \
 205   rsave (53, 48*RSIZE + 21*8);                                          \
 206   rsave (54, 48*RSIZE + 22*8);                                          \
 207   rsave (55, 48*RSIZE + 23*8);                                          \
 208   rsave (56, 48*RSIZE + 24*8);                                          \
 209   rsave (57, 48*RSIZE + 25*8);                                          \
 210   rsave (58, 48*RSIZE + 26*8);                                          \
 211   rsave (59, 48*RSIZE + 27*8);                                          \
 212   rsave (60, 48*RSIZE + 28*8);                                          \
 213   rsave (61, 48*RSIZE + 29*8);                                          \
 214   rsave (62, 48*RSIZE + 30*8);                                          \
 215   rsave (63, 48*RSIZE + 31*8)
 216
 217 /* Describe where the VMX regs are saved.  */
 218 #ifdef CONFIG_ALTIVEC
 219 #define EH_FRAME_VMX \
 220   vsave_msr0 ( 0);                                                      \
 221   vsave_msr1 ( 1);                                                      \
 222   vsave_msr1 ( 2);                                                      \
 223   vsave_msr1 ( 3);                                                      \
 224   vsave_msr1 ( 4);                                                      \
 225   vsave_msr1 ( 5);                                                      \
 226   vsave_msr1 ( 6);                                                      \
 227   vsave_msr1 ( 7);                                                      \
 228   vsave_msr1 ( 8);                                                      \
 229   vsave_msr1 ( 9);                                                      \
 230   vsave_msr1 (10);                                                      \
 231   vsave_msr1 (11);                                                      \
 232   vsave_msr1 (12);                                                      \
 233   vsave_msr1 (13);                                                      \
 234   vsave_msr1 (14);                                                      \
 235   vsave_msr1 (15);                                                      \
 236   vsave_msr1 (16);                                                      \
 237   vsave_msr1 (17);                                                      \
 238   vsave_msr1 (18);                                                      \
 239   vsave_msr1 (19);                                                      \
 240   vsave_msr1 (20);                                                      \
 241   vsave_msr1 (21);                                                      \
 242   vsave_msr1 (22);                                                      \
 243   vsave_msr1 (23);                                                      \
 244   vsave_msr1 (24);                                                      \
 245   vsave_msr1 (25);                                                      \
 246   vsave_msr1 (26);                                                      \
 247   vsave_msr1 (27);                                                      \
 248   vsave_msr1 (28);                                                      \
 249   vsave_msr1 (29);                                                      \
 250   vsave_msr1 (30);                                                      \
 251   vsave_msr1 (31);                                                      \
 252   vsave_msr2 (33, 32*16+12);                                            \
 253   vsave      (32, 32*16)
 254 #else
 255 #define EH_FRAME_VMX
 256 #endif
 257
 258 .Lcie:
 259         .long .Lcie_end - .Lcie_start
 260 .Lcie_start:
 261         .long 0                 /* CIE ID */
 262         .byte 1                 /* Version number */
 263         .string "zRS"           /* NUL-terminated augmentation string */
 264         .uleb128 4              /* Code alignment factor */
 265         .sleb128 -4             /* Data alignment factor */
 266         .byte 67                /* Return address register column, ap */
 267         .uleb128 1              /* Augmentation value length */
 268         .byte 0x1b              /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
 269         .byte 0x0c,1,0          /* DW_CFA_def_cfa: r1 ofs 0 */
 270         .balign 4
 271 .Lcie_end:
 272
 273         .long .Lfde0_end - .Lfde0_start
 274 .Lfde0_start:
 275         .long .Lfde0_start - .Lcie      /* CIE pointer. */
 276         .long .Lsig_start - .           /* PC start, length */
 277         .long .Lsig_end - .Lsig_start
 278         .uleb128 0                      /* Augmentation */
 279         EH_FRAME_GEN
 280         EH_FRAME_FP
 281         EH_FRAME_VMX
 282         .balign 4
 283 .Lfde0_end:
 284
 285 /* We have a different stack layout for rt_sigreturn.  */
 286 #undef PTREGS
 287 #define PTREGS 64+16+128+20+28
 288
 289         .long .Lfde1_end - .Lfde1_start
 290 .Lfde1_start:
 291         .long .Lfde1_start - .Lcie      /* CIE pointer. */
 292         .long .Lsigrt_start - .         /* PC start, length */
 293         .long .Lsigrt_end - .Lsigrt_start
 294         .uleb128 0                      /* Augmentation */
 295         EH_FRAME_GEN
 296         EH_FRAME_FP
 297         EH_FRAME_VMX
 298         .balign 4
 299 .Lfde1_end: