1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
17 /* Force re-assigning all resources (ignore firmware
20 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
22 /* Re-assign all bus numbers */
23 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
25 /* Do not try to assign, just use existing setup */
26 PPC_PCI_PROBE_ONLY = 0x00000004,
28 /* Don't bother with ISA alignment unless the bridge has
29 * ISA forwarding enabled
31 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
33 /* Enable domain numbers in /proc */
34 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
35 /* ... except for domain 0 */
36 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
39 extern unsigned int ppc_pci_flags;
41 static inline void ppc_pci_set_flags(int flags)
43 ppc_pci_flags = flags;
46 static inline void ppc_pci_add_flags(int flags)
48 ppc_pci_flags |= flags;
51 static inline int ppc_pci_has_flag(int flag)
53 return (ppc_pci_flags & flag);
56 static inline void ppc_pci_set_flags(int flags) { }
57 static inline void ppc_pci_add_flags(int flags) { }
58 static inline int ppc_pci_has_flag(int flag)
66 * Structure of a PCI controller (host bridge)
68 struct pci_controller {
74 struct device_node *dn;
75 struct list_head list_node;
76 struct device *parent;
82 void __iomem *io_base_virt;
86 resource_size_t io_base_phys;
87 resource_size_t pci_io_size;
89 /* Some machines (PReP) have a non 1:1 mapping of
90 * the PCI memory space in the CPU bus space
92 resource_size_t pci_mem_offset;
94 /* Some machines have a special region to forward the ISA
95 * "memory" cycles such as VGA memory regions. Left to 0
98 resource_size_t isa_mem_phys;
99 resource_size_t isa_mem_size;
102 unsigned int __iomem *cfg_addr;
103 void __iomem *cfg_data;
106 * Used for variants of PCI indirect handling and possible quirks:
107 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
108 * EXT_REG - provides access to PCI-e extended registers
109 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
110 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
111 * to determine which bus number to match on when generating type0
113 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
114 * hanging if we don't have link and try to do config cycles to
115 * anything but the PHB. Only allow talking to the PHB if this is
117 * BIG_ENDIAN - cfg_addr is a big endian register
118 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
119 * the PLB4. Effectively disable MRM commands by setting this.
121 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
122 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
123 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
124 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
125 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
126 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
128 /* Currently, we limit ourselves to 1 IO range and 3 mem
129 * ranges since the common pci_bus structure can't handle more
131 struct resource io_resource;
132 struct resource mem_resources[3];
133 int global_number; /* PCI domain number */
135 resource_size_t dma_window_base_cur;
136 resource_size_t dma_window_size;
142 #endif /* CONFIG_PPC64 */
145 /* These are used for config access before all the PCI probing
147 extern int early_read_config_byte(struct pci_controller *hose, int bus,
148 int dev_fn, int where, u8 *val);
149 extern int early_read_config_word(struct pci_controller *hose, int bus,
150 int dev_fn, int where, u16 *val);
151 extern int early_read_config_dword(struct pci_controller *hose, int bus,
152 int dev_fn, int where, u32 *val);
153 extern int early_write_config_byte(struct pci_controller *hose, int bus,
154 int dev_fn, int where, u8 val);
155 extern int early_write_config_word(struct pci_controller *hose, int bus,
156 int dev_fn, int where, u16 val);
157 extern int early_write_config_dword(struct pci_controller *hose, int bus,
158 int dev_fn, int where, u32 val);
160 extern int early_find_capability(struct pci_controller *hose, int bus,
161 int dev_fn, int cap);
163 extern void setup_indirect_pci(struct pci_controller* hose,
164 resource_size_t cfg_addr,
165 resource_size_t cfg_data, u32 flags);
167 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
174 extern int pci_device_from_OF_node(struct device_node *node,
176 extern void pci_create_OF_bus_map(void);
178 static inline int isa_vaddr_is_ioport(void __iomem *address)
180 /* No specific ISA handling on ppc32 at this stage, it
181 * all goes through PCI
186 #else /* CONFIG_PPC64 */
189 * PCI stuff, for nodes representing PCI devices, pointed to
190 * by device_node->data.
195 int busno; /* pci bus number */
196 int devfn; /* pci device and function number */
198 struct pci_controller *phb; /* for pci devices */
199 struct iommu_table *iommu_table; /* for phb's or bridges */
200 struct device_node *node; /* back-pointer to the device_node */
202 int pci_ext_config_space; /* for pci devices */
205 struct pci_dev *pcidev; /* back-pointer to the pci device */
206 int class_code; /* pci device class */
207 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
209 int eeh_pe_config_addr; /* new-style partition endpoint address */
210 int eeh_check_count; /* # times driver ignored error */
211 int eeh_freeze_count; /* # times this device froze up. */
212 int eeh_false_positives; /* # times this device reported #ff's */
213 u32 config_space[16]; /* saved PCI config space */
217 /* Get the pointer to a device_node's pci_dn */
218 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
220 extern void * update_dn_pci_info(struct device_node *dn, void *data);
222 static inline int pci_device_from_OF_node(struct device_node *np,
227 *bus = PCI_DN(np)->busno;
228 *devfn = PCI_DN(np)->devfn;
232 /** Find the bus corresponding to the indicated device node */
233 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
235 /** Remove all of the PCI devices under this bus */
236 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
238 /** Discover new pci devices under this bus, and add them */
239 extern void pcibios_add_pci_devices(struct pci_bus *bus);
242 extern void isa_bridge_find_early(struct pci_controller *hose);
244 static inline int isa_vaddr_is_ioport(void __iomem *address)
246 /* Check if address hits the reserved legacy IO range */
247 unsigned long ea = (unsigned long)address;
248 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
251 extern int pcibios_unmap_io_space(struct pci_bus *bus);
252 extern int pcibios_map_io_space(struct pci_bus *bus);
255 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
257 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
260 #endif /* CONFIG_PPC64 */
262 /* Get the PCI host controller for an OF device */
263 extern struct pci_controller *pci_find_hose_for_OF_device(
264 struct device_node* node);
266 /* Fill up host controller resources from the OF node */
267 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
268 struct device_node *dev, int primary);
270 /* Allocate & free a PCI host bridge structure */
271 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
272 extern void pcibios_free_controller(struct pci_controller *phb);
273 extern void pcibios_setup_phb_resources(struct pci_controller *hose);
276 extern int pcibios_vaddr_is_ioport(void __iomem *address);
278 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
282 #endif /* CONFIG_PCI */
284 #endif /* __KERNEL__ */
285 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */