arch/powerpc/boot/dts/p4080si.dtsi

   1 /*
   2  * P4080 Silicon Device Tree Source
   3  *
   4  * Copyright 2009-2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /dts-v1/;
  36
  37 / {
  38         compatible = "fsl,P4080";
  39         #address-cells = <2>;
  40         #size-cells = <2>;
  41         interrupt-parent = <&mpic>;
  42
  43         aliases {
  44                 ccsr = &soc;
  45
  46                 serial0 = &serial0;
  47                 serial1 = &serial1;
  48                 serial2 = &serial2;
  49                 serial3 = &serial3;
  50                 pci0 = &pci0;
  51                 pci1 = &pci1;
  52                 pci2 = &pci2;
  53                 usb0 = &usb0;
  54                 usb1 = &usb1;
  55                 dma0 = &dma0;
  56                 dma1 = &dma1;
  57                 sdhc = &sdhc;
  58                 msi0 = &msi0;
  59                 msi1 = &msi1;
  60                 msi2 = &msi2;
  61
  62                 crypto = &crypto;
  63                 sec_jr0 = &sec_jr0;
  64                 sec_jr1 = &sec_jr1;
  65                 sec_jr2 = &sec_jr2;
  66                 sec_jr3 = &sec_jr3;
  67                 rtic_a = &rtic_a;
  68                 rtic_b = &rtic_b;
  69                 rtic_c = &rtic_c;
  70                 rtic_d = &rtic_d;
  71                 sec_mon = &sec_mon;
  72
  73                 rio0 = &rapidio0;
  74         };
  75
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79
  80                 cpu0: PowerPC,4080@0 {
  81                         device_type = "cpu";
  82                         reg = <0>;
  83                         next-level-cache = <&L2_0>;
  84                         L2_0: l2-cache {
  85                                 next-level-cache = <&cpc>;
  86                         };
  87                 };
  88                 cpu1: PowerPC,4080@1 {
  89                         device_type = "cpu";
  90                         reg = <1>;
  91                         next-level-cache = <&L2_1>;
  92                         L2_1: l2-cache {
  93                                 next-level-cache = <&cpc>;
  94                         };
  95                 };
  96                 cpu2: PowerPC,4080@2 {
  97                         device_type = "cpu";
  98                         reg = <2>;
  99                         next-level-cache = <&L2_2>;
 100                         L2_2: l2-cache {
 101                                 next-level-cache = <&cpc>;
 102                         };
 103                 };
 104                 cpu3: PowerPC,4080@3 {
 105                         device_type = "cpu";
 106                         reg = <3>;
 107                         next-level-cache = <&L2_3>;
 108                         L2_3: l2-cache {
 109                                 next-level-cache = <&cpc>;
 110                         };
 111                 };
 112                 cpu4: PowerPC,4080@4 {
 113                         device_type = "cpu";
 114                         reg = <4>;
 115                         next-level-cache = <&L2_4>;
 116                         L2_4: l2-cache {
 117                                 next-level-cache = <&cpc>;
 118                         };
 119                 };
 120                 cpu5: PowerPC,4080@5 {
 121                         device_type = "cpu";
 122                         reg = <5>;
 123                         next-level-cache = <&L2_5>;
 124                         L2_5: l2-cache {
 125                                 next-level-cache = <&cpc>;
 126                         };
 127                 };
 128                 cpu6: PowerPC,4080@6 {
 129                         device_type = "cpu";
 130                         reg = <6>;
 131                         next-level-cache = <&L2_6>;
 132                         L2_6: l2-cache {
 133                                 next-level-cache = <&cpc>;
 134                         };
 135                 };
 136                 cpu7: PowerPC,4080@7 {
 137                         device_type = "cpu";
 138                         reg = <7>;
 139                         next-level-cache = <&L2_7>;
 140                         L2_7: l2-cache {
 141                                 next-level-cache = <&cpc>;
 142                         };
 143                 };
 144         };
 145
 146         soc: soc@ffe000000 {
 147                 #address-cells = <1>;
 148                 #size-cells = <1>;
 149                 device_type = "soc";
 150                 compatible = "simple-bus";
 151                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 152                 reg = <0xf 0xfe000000 0 0x00001000>;
 153
 154                 soc-sram-error {
 155                         compatible = "fsl,soc-sram-error";
 156                         interrupts = <16 2 1 29>;
 157                 };
 158
 159                 corenet-law@0 {
 160                         compatible = "fsl,corenet-law";
 161                         reg = <0x0 0x1000>;
 162                         fsl,num-laws = <32>;
 163                 };
 164
 165                 memory-controller@8000 {
 166                         compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
 167                         reg = <0x8000 0x1000>;
 168                         interrupts = <16 2 1 23>;
 169                 };
 170
 171                 memory-controller@9000 {
 172                         compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
 173                         reg = <0x9000 0x1000>;
 174                         interrupts = <16 2 1 22>;
 175                 };
 176
 177                 cpc: l3-cache-controller@10000 {
 178                         compatible = "fsl,p4080-l3-cache-controller", "cache";
 179                         reg = <0x10000 0x1000
 180                                0x11000 0x1000>;
 181                         interrupts = <16 2 1 27
 182                                       16 2 1 26>;
 183                 };
 184
 185                 corenet-cf@18000 {
 186                         compatible = "fsl,corenet-cf";
 187                         reg = <0x18000 0x1000>;
 188                         interrupts = <16 2 1 31>;
 189                         fsl,ccf-num-csdids = <32>;
 190                         fsl,ccf-num-snoopids = <32>;
 191                 };
 192
 193                 iommu@20000 {
 194                         compatible = "fsl,pamu-v1.0", "fsl,pamu";
 195                         reg = <0x20000 0x5000>;
 196                         interrupts = <
 197                                 24 2 0 0
 198                                 16 2 1 30>;
 199                 };
 200
 201                 mpic: pic@40000 {
 202                         clock-frequency = <0>;
 203                         interrupt-controller;
 204                         #address-cells = <0>;
 205                         #interrupt-cells = <4>;
 206                         reg = <0x40000 0x40000>;
 207                         compatible = "fsl,mpic", "chrp,open-pic";
 208                         device_type = "open-pic";
 209                 };
 210
 211                 msi0: msi@41600 {
 212                         compatible = "fsl,mpic-msi";
 213                         reg = <0x41600 0x200>;
 214                         msi-available-ranges = <0 0x100>;
 215                         interrupts = <
 216                                 0xe0 0 0 0
 217                                 0xe1 0 0 0
 218                                 0xe2 0 0 0
 219                                 0xe3 0 0 0
 220                                 0xe4 0 0 0
 221                                 0xe5 0 0 0
 222                                 0xe6 0 0 0
 223                                 0xe7 0 0 0>;
 224                 };
 225
 226                 msi1: msi@41800 {
 227                         compatible = "fsl,mpic-msi";
 228                         reg = <0x41800 0x200>;
 229                         msi-available-ranges = <0 0x100>;
 230                         interrupts = <
 231                                 0xe8 0 0 0
 232                                 0xe9 0 0 0
 233                                 0xea 0 0 0
 234                                 0xeb 0 0 0
 235                                 0xec 0 0 0
 236                                 0xed 0 0 0
 237                                 0xee 0 0 0
 238                                 0xef 0 0 0>;
 239                 };
 240
 241                 msi2: msi@41a00 {
 242                         compatible = "fsl,mpic-msi";
 243                         reg = <0x41a00 0x200>;
 244                         msi-available-ranges = <0 0x100>;
 245                         interrupts = <
 246                                 0xf0 0 0 0
 247                                 0xf1 0 0 0
 248                                 0xf2 0 0 0
 249                                 0xf3 0 0 0
 250                                 0xf4 0 0 0
 251                                 0xf5 0 0 0
 252                                 0xf6 0 0 0
 253                                 0xf7 0 0 0>;
 254                 };
 255
 256                 guts: global-utilities@e0000 {
 257                         compatible = "fsl,qoriq-device-config-1.0";
 258                         reg = <0xe0000 0xe00>;
 259                         fsl,has-rstcr;
 260                         #sleep-cells = <1>;
 261                         fsl,liodn-bits = <12>;
 262                 };
 263
 264                 pins: global-utilities@e0e00 {
 265                         compatible = "fsl,qoriq-pin-control-1.0";
 266                         reg = <0xe0e00 0x200>;
 267                         #sleep-cells = <2>;
 268                 };
 269
 270                 clockgen: global-utilities@e1000 {
 271                         compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
 272                         reg = <0xe1000 0x1000>;
 273                         clock-frequency = <0>;
 274                 };
 275
 276                 rcpm: global-utilities@e2000 {
 277                         compatible = "fsl,qoriq-rcpm-1.0";
 278                         reg = <0xe2000 0x1000>;
 279                         #sleep-cells = <1>;
 280                 };
 281
 282                 sfp: sfp@e8000 {
 283                         compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
 284                         reg        = <0xe8000 0x1000>;
 285                 };
 286
 287                 serdes: serdes@ea000 {
 288                         compatible = "fsl,p4080-serdes";
 289                         reg        = <0xea000 0x1000>;
 290                 };
 291
 292                 dma0: dma@100300 {
 293                         #address-cells = <1>;
 294                         #size-cells = <1>;
 295                         compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
 296                         reg = <0x100300 0x4>;
 297                         ranges = <0x0 0x100100 0x200>;
 298                         cell-index = <0>;
 299                         dma-channel@0 {
 300                                 compatible = "fsl,p4080-dma-channel",
 301                                                 "fsl,eloplus-dma-channel";
 302                                 reg = <0x0 0x80>;
 303                                 cell-index = <0>;
 304                                 interrupts = <28 2 0 0>;
 305                         };
 306                         dma-channel@80 {
 307                                 compatible = "fsl,p4080-dma-channel",
 308                                                 "fsl,eloplus-dma-channel";
 309                                 reg = <0x80 0x80>;
 310                                 cell-index = <1>;
 311                                 interrupts = <29 2 0 0>;
 312                         };
 313                         dma-channel@100 {
 314                                 compatible = "fsl,p4080-dma-channel",
 315                                                 "fsl,eloplus-dma-channel";
 316                                 reg = <0x100 0x80>;
 317                                 cell-index = <2>;
 318                                 interrupts = <30 2 0 0>;
 319                         };
 320                         dma-channel@180 {
 321                                 compatible = "fsl,p4080-dma-channel",
 322                                                 "fsl,eloplus-dma-channel";
 323                                 reg = <0x180 0x80>;
 324                                 cell-index = <3>;
 325                                 interrupts = <31 2 0 0>;
 326                         };
 327                 };
 328
 329                 dma1: dma@101300 {
 330                         #address-cells = <1>;
 331                         #size-cells = <1>;
 332                         compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
 333                         reg = <0x101300 0x4>;
 334                         ranges = <0x0 0x101100 0x200>;
 335                         cell-index = <1>;
 336                         dma-channel@0 {
 337                                 compatible = "fsl,p4080-dma-channel",
 338                                                 "fsl,eloplus-dma-channel";
 339                                 reg = <0x0 0x80>;
 340                                 cell-index = <0>;
 341                                 interrupts = <32 2 0 0>;
 342                         };
 343                         dma-channel@80 {
 344                                 compatible = "fsl,p4080-dma-channel",
 345                                                 "fsl,eloplus-dma-channel";
 346                                 reg = <0x80 0x80>;
 347                                 cell-index = <1>;
 348                                 interrupts = <33 2 0 0>;
 349                         };
 350                         dma-channel@100 {
 351                                 compatible = "fsl,p4080-dma-channel",
 352                                                 "fsl,eloplus-dma-channel";
 353                                 reg = <0x100 0x80>;
 354                                 cell-index = <2>;
 355                                 interrupts = <34 2 0 0>;
 356                         };
 357                         dma-channel@180 {
 358                                 compatible = "fsl,p4080-dma-channel",
 359                                                 "fsl,eloplus-dma-channel";
 360                                 reg = <0x180 0x80>;
 361                                 cell-index = <3>;
 362                                 interrupts = <35 2 0 0>;
 363                         };
 364                 };
 365
 366                 spi@110000 {
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
 370                         reg = <0x110000 0x1000>;
 371                         interrupts = <53 0x2 0 0>;
 372                         fsl,espi-num-chipselects = <4>;
 373                 };
 374
 375                 sdhc: sdhc@114000 {
 376                         compatible = "fsl,p4080-esdhc", "fsl,esdhc";
 377                         reg = <0x114000 0x1000>;
 378                         interrupts = <48 2 0 0>;
 379                         voltage-ranges = <3300 3300>;
 380                         sdhci,auto-cmd12;
 381                         clock-frequency = <0>;
 382                 };
 383
 384                 i2c@118000 {
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         cell-index = <0>;
 388                         compatible = "fsl-i2c";
 389                         reg = <0x118000 0x100>;
 390                         interrupts = <38 2 0 0>;
 391                         dfsrr;
 392                 };
 393
 394                 i2c@118100 {
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         cell-index = <1>;
 398                         compatible = "fsl-i2c";
 399                         reg = <0x118100 0x100>;
 400                         interrupts = <38 2 0 0>;
 401                         dfsrr;
 402                 };
 403
 404                 i2c@119000 {
 405                         #address-cells = <1>;
 406                         #size-cells = <0>;
 407                         cell-index = <2>;
 408                         compatible = "fsl-i2c";
 409                         reg = <0x119000 0x100>;
 410                         interrupts = <39 2 0 0>;
 411                         dfsrr;
 412                 };
 413
 414                 i2c@119100 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         cell-index = <3>;
 418                         compatible = "fsl-i2c";
 419                         reg = <0x119100 0x100>;
 420                         interrupts = <39 2 0 0>;
 421                         dfsrr;
 422                 };
 423
 424                 serial0: serial@11c500 {
 425                         cell-index = <0>;
 426                         device_type = "serial";
 427                         compatible = "ns16550";
 428                         reg = <0x11c500 0x100>;
 429                         clock-frequency = <0>;
 430                         interrupts = <36 2 0 0>;
 431                 };
 432
 433                 serial1: serial@11c600 {
 434                         cell-index = <1>;
 435                         device_type = "serial";
 436                         compatible = "ns16550";
 437                         reg = <0x11c600 0x100>;
 438                         clock-frequency = <0>;
 439                         interrupts = <36 2 0 0>;
 440                 };
 441
 442                 serial2: serial@11d500 {
 443                         cell-index = <2>;
 444                         device_type = "serial";
 445                         compatible = "ns16550";
 446                         reg = <0x11d500 0x100>;
 447                         clock-frequency = <0>;
 448                         interrupts = <37 2 0 0>;
 449                 };
 450
 451                 serial3: serial@11d600 {
 452                         cell-index = <3>;
 453                         device_type = "serial";
 454                         compatible = "ns16550";
 455                         reg = <0x11d600 0x100>;
 456                         clock-frequency = <0>;
 457                         interrupts = <37 2 0 0>;
 458                 };
 459
 460                 gpio0: gpio@130000 {
 461                         compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
 462                         reg = <0x130000 0x1000>;
 463                         interrupts = <55 2 0 0>;
 464                         #gpio-cells = <2>;
 465                         gpio-controller;
 466                 };
 467
 468                 usb0: usb@210000 {
 469                         compatible = "fsl,p4080-usb2-mph",
 470                                         "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 471                         reg = <0x210000 0x1000>;
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                         interrupts = <44 0x2 0 0>;
 475                 };
 476
 477                 usb1: usb@211000 {
 478                         compatible = "fsl,p4080-usb2-dr",
 479                                         "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 480                         reg = <0x211000 0x1000>;
 481                         #address-cells = <1>;
 482                         #size-cells = <0>;
 483                         interrupts = <45 0x2 0 0>;
 484                 };
 485
 486                 crypto: crypto@300000 {
 487                         compatible = "fsl,sec-v4.0";
 488                         #address-cells = <1>;
 489                         #size-cells = <1>;
 490                         reg = <0x300000 0x10000>;
 491                         ranges = <0 0x300000 0x10000>;
 492                         interrupt-parent = <&mpic>;
 493                         interrupts = <92 2 0 0>;
 494
 495                         sec_jr0: jr@1000 {
 496                                 compatible = "fsl,sec-v4.0-job-ring";
 497                                 reg = <0x1000 0x1000>;
 498                                 interrupt-parent = <&mpic>;
 499                                 interrupts = <88 2 0 0>;
 500                         };
 501
 502                         sec_jr1: jr@2000 {
 503                                 compatible = "fsl,sec-v4.0-job-ring";
 504                                 reg = <0x2000 0x1000>;
 505                                 interrupt-parent = <&mpic>;
 506                                 interrupts = <89 2 0 0>;
 507                         };
 508
 509                         sec_jr2: jr@3000 {
 510                                 compatible = "fsl,sec-v4.0-job-ring";
 511                                 reg = <0x3000 0x1000>;
 512                                 interrupt-parent = <&mpic>;
 513                                 interrupts = <90 2 0 0>;
 514                         };
 515
 516                         sec_jr3: jr@4000 {
 517                                 compatible = "fsl,sec-v4.0-job-ring";
 518                                 reg = <0x4000 0x1000>;
 519                                 interrupt-parent = <&mpic>;
 520                                 interrupts = <91 2 0 0>;
 521                         };
 522
 523                         rtic@6000 {
 524                                 compatible = "fsl,sec-v4.0-rtic";
 525                                 #address-cells = <1>;
 526                                 #size-cells = <1>;
 527                                 reg = <0x6000 0x100>;
 528                                 ranges = <0x0 0x6100 0xe00>;
 529
 530                                 rtic_a: rtic-a@0 {
 531                                         compatible = "fsl,sec-v4.0-rtic-memory";
 532                                         reg = <0x00 0x20 0x100 0x80>;
 533                                 };
 534
 535                                 rtic_b: rtic-b@20 {
 536                                         compatible = "fsl,sec-v4.0-rtic-memory";
 537                                         reg = <0x20 0x20 0x200 0x80>;
 538                                 };
 539
 540                                 rtic_c: rtic-c@40 {
 541                                         compatible = "fsl,sec-v4.0-rtic-memory";
 542                                         reg = <0x40 0x20 0x300 0x80>;
 543                                 };
 544
 545                                 rtic_d: rtic-d@60 {
 546                                         compatible = "fsl,sec-v4.0-rtic-memory";
 547                                         reg = <0x60 0x20 0x500 0x80>;
 548                                 };
 549                         };
 550                 };
 551
 552                 sec_mon: sec_mon@314000 {
 553                         compatible = "fsl,sec-v4.0-mon";
 554                         reg = <0x314000 0x1000>;
 555                         interrupt-parent = <&mpic>;
 556                         interrupts = <93 2 0 0>;
 557                 };
 558         };
 559
 560         rapidio0: rapidio@ffe0c0000 {
 561                 #address-cells = <2>;
 562                 #size-cells = <2>;
 563                 compatible = "fsl,rapidio-delta";
 564                 interrupts = <
 565                         16 2 1 11 /* err_irq */
 566                         56 2 0 0  /* bell_outb_irq */
 567                         57 2 0 0  /* bell_inb_irq */
 568                         60 2 0 0  /* msg1_tx_irq */
 569                         61 2 0 0  /* msg1_rx_irq */
 570                         62 2 0 0  /* msg2_tx_irq */
 571                         63 2 0 0>; /* msg2_rx_irq */
 572         };
 573
 574         localbus@ffe124000 {
 575                 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
 576                 interrupts = <25 2 0 0>;
 577                 #address-cells = <2>;
 578                 #size-cells = <1>;
 579         };
 580
 581         pci0: pcie@ffe200000 {
 582                 compatible = "fsl,p4080-pcie";
 583                 device_type = "pci";
 584                 #size-cells = <2>;
 585                 #address-cells = <3>;
 586                 bus-range = <0x0 0xff>;
 587                 clock-frequency = <0x1fca055>;
 588                 fsl,msi = <&msi0>;
 589                 interrupts = <16 2 1 15>;
 590                 pcie@0 {
 591                         reg = <0 0 0 0 0>;
 592                         #interrupt-cells = <1>;
 593                         #size-cells = <2>;
 594                         #address-cells = <3>;
 595                         device_type = "pci";
 596                         interrupts = <16 2 1 15>;
 597                         interrupt-map-mask = <0xf800 0 0 7>;
 598                         interrupt-map = <
 599                                 /* IDSEL 0x0 */
 600                                 0000 0 0 1 &mpic 40 1 0 0
 601                                 0000 0 0 2 &mpic 1 1 0 0
 602                                 0000 0 0 3 &mpic 2 1 0 0
 603                                 0000 0 0 4 &mpic 3 1 0 0
 604                                 >;
 605                 };
 606         };
 607
 608         pci1: pcie@ffe201000 {
 609                 compatible = "fsl,p4080-pcie";
 610                 device_type = "pci";
 611                 #size-cells = <2>;
 612                 #address-cells = <3>;
 613                 bus-range = <0 0xff>;
 614                 clock-frequency = <0x1fca055>;
 615                 fsl,msi = <&msi1>;
 616                 interrupts = <16 2 1 14>;
 617                 pcie@0 {
 618                         reg = <0 0 0 0 0>;
 619                         #interrupt-cells = <1>;
 620                         #size-cells = <2>;
 621                         #address-cells = <3>;
 622                         device_type = "pci";
 623                         interrupts = <16 2 1 14>;
 624                         interrupt-map-mask = <0xf800 0 0 7>;
 625                         interrupt-map = <
 626                                 /* IDSEL 0x0 */
 627                                 0000 0 0 1 &mpic 41 1 0 0
 628                                 0000 0 0 2 &mpic 5 1 0 0
 629                                 0000 0 0 3 &mpic 6 1 0 0
 630                                 0000 0 0 4 &mpic 7 1 0 0
 631                                 >;
 632                 };
 633         };
 634
 635         pci2: pcie@ffe202000 {
 636                 compatible = "fsl,p4080-pcie";
 637                 device_type = "pci";
 638                 #size-cells = <2>;
 639                 #address-cells = <3>;
 640                 bus-range = <0x0 0xff>;
 641                 clock-frequency = <0x1fca055>;
 642                 fsl,msi = <&msi2>;
 643                 interrupts = <16 2 1 13>;
 644                 pcie@0 {
 645                         reg = <0 0 0 0 0>;
 646                         #interrupt-cells = <1>;
 647                         #size-cells = <2>;
 648                         #address-cells = <3>;
 649                         device_type = "pci";
 650                         interrupts = <16 2 1 13>;
 651                         interrupt-map-mask = <0xf800 0 0 7>;
 652                         interrupt-map = <
 653                                 /* IDSEL 0x0 */
 654                                 0000 0 0 1 &mpic 42 1 0 0
 655                                 0000 0 0 2 &mpic 9 1 0 0
 656                                 0000 0 0 3 &mpic 10 1 0 0
 657                                 0000 0 0 4 &mpic 11 1 0 0
 658                                 >;
 659                 };
 660         };
 661 };