arch/powerpc/boot/dts/p4080ds.dts

   1 /*
   2  * P4080DS Device Tree Source
   3  *
   4  * Copyright 2009 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "fsl,P4080DS";
  16         compatible = "fsl,P4080DS";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 ccsr = &soc;
  22
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 serial2 = &serial2;
  26                 serial3 = &serial3;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29                 pci2 = &pci2;
  30                 usb0 = &usb0;
  31                 usb1 = &usb1;
  32                 dma0 = &dma0;
  33                 dma1 = &dma1;
  34                 sdhc = &sdhc;
  35
  36                 rio0 = &rapidio0;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu0: PowerPC,4080@0 {
  44                         device_type = "cpu";
  45                         reg = <0>;
  46                         next-level-cache = <&L2_0>;
  47                         L2_0: l2-cache {
  48                         };
  49                 };
  50                 cpu1: PowerPC,4080@1 {
  51                         device_type = "cpu";
  52                         reg = <1>;
  53                         next-level-cache = <&L2_1>;
  54                         L2_1: l2-cache {
  55                         };
  56                 };
  57                 cpu2: PowerPC,4080@2 {
  58                         device_type = "cpu";
  59                         reg = <2>;
  60                         next-level-cache = <&L2_2>;
  61                         L2_2: l2-cache {
  62                         };
  63                 };
  64                 cpu3: PowerPC,4080@3 {
  65                         device_type = "cpu";
  66                         reg = <3>;
  67                         next-level-cache = <&L2_3>;
  68                         L2_3: l2-cache {
  69                         };
  70                 };
  71                 cpu4: PowerPC,4080@4 {
  72                         device_type = "cpu";
  73                         reg = <4>;
  74                         next-level-cache = <&L2_4>;
  75                         L2_4: l2-cache {
  76                         };
  77                 };
  78                 cpu5: PowerPC,4080@5 {
  79                         device_type = "cpu";
  80                         reg = <5>;
  81                         next-level-cache = <&L2_5>;
  82                         L2_5: l2-cache {
  83                         };
  84                 };
  85                 cpu6: PowerPC,4080@6 {
  86                         device_type = "cpu";
  87                         reg = <6>;
  88                         next-level-cache = <&L2_6>;
  89                         L2_6: l2-cache {
  90                         };
  91                 };
  92                 cpu7: PowerPC,4080@7 {
  93                         device_type = "cpu";
  94                         reg = <7>;
  95                         next-level-cache = <&L2_7>;
  96                         L2_7: l2-cache {
  97                         };
  98                 };
  99         };
 100
 101         memory {
 102                 device_type = "memory";
 103         };
 104
 105         soc: soc@ffe000000 {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 device_type = "soc";
 109                 compatible = "simple-bus";
 110                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 111                 reg = <0xf 0xfe000000 0 0x00001000>;
 112
 113                 corenet-law@0 {
 114                         compatible = "fsl,corenet-law";
 115                         reg = <0x0 0x1000>;
 116                         fsl,num-laws = <32>;
 117                 };
 118
 119                 memory-controller@8000 {
 120                         compatible = "fsl,p4080-memory-controller";
 121                         reg = <0x8000 0x1000>;
 122                         interrupt-parent = <&mpic>;
 123                         interrupts = <0x12 2>;
 124                 };
 125
 126                 memory-controller@9000 {
 127                         compatible = "fsl,p4080-memory-controller";
 128                         reg = <0x9000 0x1000>;
 129                         interrupt-parent = <&mpic>;
 130                         interrupts = <0x12 2>;
 131                 };
 132
 133                 corenet-cf@18000 {
 134                         compatible = "fsl,corenet-cf";
 135                         reg = <0x18000 0x1000>;
 136                         fsl,ccf-num-csdids = <32>;
 137                         fsl,ccf-num-snoopids = <32>;
 138                 };
 139
 140                 iommu@20000 {
 141                         compatible = "fsl,p4080-pamu";
 142                         reg = <0x20000 0x10000>;
 143                         interrupts = <24 2>;
 144                         interrupt-parent = <&mpic>;
 145                 };
 146
 147                 mpic: pic@40000 {
 148                         interrupt-controller;
 149                         #address-cells = <0>;
 150                         #interrupt-cells = <2>;
 151                         reg = <0x40000 0x40000>;
 152                         compatible = "chrp,open-pic";
 153                         device_type = "open-pic";
 154                 };
 155
 156                 dma0: dma@100300 {
 157                         #address-cells = <1>;
 158                         #size-cells = <1>;
 159                         compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
 160                         reg = <0x100300 0x4>;
 161                         ranges = <0x0 0x100100 0x200>;
 162                         cell-index = <0>;
 163                         dma-channel@0 {
 164                                 compatible = "fsl,p4080-dma-channel",
 165                                                 "fsl,eloplus-dma-channel";
 166                                 reg = <0x0 0x80>;
 167                                 cell-index = <0>;
 168                                 interrupt-parent = <&mpic>;
 169                                 interrupts = <28 2>;
 170                         };
 171                         dma-channel@80 {
 172                                 compatible = "fsl,p4080-dma-channel",
 173                                                 "fsl,eloplus-dma-channel";
 174                                 reg = <0x80 0x80>;
 175                                 cell-index = <1>;
 176                                 interrupt-parent = <&mpic>;
 177                                 interrupts = <29 2>;
 178                         };
 179                         dma-channel@100 {
 180                                 compatible = "fsl,p4080-dma-channel",
 181                                                 "fsl,eloplus-dma-channel";
 182                                 reg = <0x100 0x80>;
 183                                 cell-index = <2>;
 184                                 interrupt-parent = <&mpic>;
 185                                 interrupts = <30 2>;
 186                         };
 187                         dma-channel@180 {
 188                                 compatible = "fsl,p4080-dma-channel",
 189                                                 "fsl,eloplus-dma-channel";
 190                                 reg = <0x180 0x80>;
 191                                 cell-index = <3>;
 192                                 interrupt-parent = <&mpic>;
 193                                 interrupts = <31 2>;
 194                         };
 195                 };
 196
 197                 dma1: dma@101300 {
 198                         #address-cells = <1>;
 199                         #size-cells = <1>;
 200                         compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
 201                         reg = <0x101300 0x4>;
 202                         ranges = <0x0 0x101100 0x200>;
 203                         cell-index = <1>;
 204                         dma-channel@0 {
 205                                 compatible = "fsl,p4080-dma-channel",
 206                                                 "fsl,eloplus-dma-channel";
 207                                 reg = <0x0 0x80>;
 208                                 cell-index = <0>;
 209                                 interrupt-parent = <&mpic>;
 210                                 interrupts = <32 2>;
 211                         };
 212                         dma-channel@80 {
 213                                 compatible = "fsl,p4080-dma-channel",
 214                                                 "fsl,eloplus-dma-channel";
 215                                 reg = <0x80 0x80>;
 216                                 cell-index = <1>;
 217                                 interrupt-parent = <&mpic>;
 218                                 interrupts = <33 2>;
 219                         };
 220                         dma-channel@100 {
 221                                 compatible = "fsl,p4080-dma-channel",
 222                                                 "fsl,eloplus-dma-channel";
 223                                 reg = <0x100 0x80>;
 224                                 cell-index = <2>;
 225                                 interrupt-parent = <&mpic>;
 226                                 interrupts = <34 2>;
 227                         };
 228                         dma-channel@180 {
 229                                 compatible = "fsl,p4080-dma-channel",
 230                                                 "fsl,eloplus-dma-channel";
 231                                 reg = <0x180 0x80>;
 232                                 cell-index = <3>;
 233                                 interrupt-parent = <&mpic>;
 234                                 interrupts = <35 2>;
 235                         };
 236                 };
 237
 238                 spi@110000 {
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
 242                         reg = <0x110000 0x1000>;
 243                         interrupts = <53 0x2>;
 244                         interrupt-parent = <&mpic>;
 245                         fsl,espi-num-chipselects = <4>;
 246
 247                         flash@0 {
 248                                 #address-cells = <1>;
 249                                 #size-cells = <1>;
 250                                 compatible = "spansion,s25sl12801";
 251                                 reg = <0>;
 252                                 spi-max-frequency = <40000000>; /* input clock */
 253                                 partition@u-boot {
 254                                         label = "u-boot";
 255                                         reg = <0x00000000 0x00100000>;
 256                                         read-only;
 257                                 };
 258                                 partition@kernel {
 259                                         label = "kernel";
 260                                         reg = <0x00100000 0x00500000>;
 261                                         read-only;
 262                                 };
 263                                 partition@dtb {
 264                                         label = "dtb";
 265                                         reg = <0x00600000 0x00100000>;
 266                                         read-only;
 267                                 };
 268                                 partition@fs {
 269                                         label = "file system";
 270                                         reg = <0x00700000 0x00900000>;
 271                                 };
 272                         };
 273                 };
 274
 275                 sdhc: sdhc@114000 {
 276                         compatible = "fsl,p4080-esdhc", "fsl,esdhc";
 277                         reg = <0x114000 0x1000>;
 278                         interrupts = <48 2>;
 279                         interrupt-parent = <&mpic>;
 280                         voltage-ranges = <3300 3300>;
 281                         sdhci,auto-cmd12;
 282                 };
 283
 284                 i2c@118000 {
 285                         #address-cells = <1>;
 286                         #size-cells = <0>;
 287                         cell-index = <0>;
 288                         compatible = "fsl-i2c";
 289                         reg = <0x118000 0x100>;
 290                         interrupts = <38 2>;
 291                         interrupt-parent = <&mpic>;
 292                         dfsrr;
 293                 };
 294
 295                 i2c@118100 {
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         cell-index = <1>;
 299                         compatible = "fsl-i2c";
 300                         reg = <0x118100 0x100>;
 301                         interrupts = <38 2>;
 302                         interrupt-parent = <&mpic>;
 303                         dfsrr;
 304                         eeprom@51 {
 305                                 compatible = "at24,24c256";
 306                                 reg = <0x51>;
 307                         };
 308                         eeprom@52 {
 309                                 compatible = "at24,24c256";
 310                                 reg = <0x52>;
 311                         };
 312                         rtc@68 {
 313                                 compatible = "dallas,ds3232";
 314                                 reg = <0x68>;
 315                                 interrupts = <0 0x1>;
 316                                 interrupt-parent = <&mpic>;
 317                         };
 318                 };
 319
 320                 i2c@119000 {
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         cell-index = <2>;
 324                         compatible = "fsl-i2c";
 325                         reg = <0x119000 0x100>;
 326                         interrupts = <39 2>;
 327                         interrupt-parent = <&mpic>;
 328                         dfsrr;
 329                 };
 330
 331                 i2c@119100 {
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         cell-index = <3>;
 335                         compatible = "fsl-i2c";
 336                         reg = <0x119100 0x100>;
 337                         interrupts = <39 2>;
 338                         interrupt-parent = <&mpic>;
 339                         dfsrr;
 340                 };
 341
 342                 serial0: serial@11c500 {
 343                         cell-index = <0>;
 344                         device_type = "serial";
 345                         compatible = "ns16550";
 346                         reg = <0x11c500 0x100>;
 347                         clock-frequency = <0>;
 348                         interrupts = <36 2>;
 349                         interrupt-parent = <&mpic>;
 350                 };
 351
 352                 serial1: serial@11c600 {
 353                         cell-index = <1>;
 354                         device_type = "serial";
 355                         compatible = "ns16550";
 356                         reg = <0x11c600 0x100>;
 357                         clock-frequency = <0>;
 358                         interrupts = <36 2>;
 359                         interrupt-parent = <&mpic>;
 360                 };
 361
 362                 serial2: serial@11d500 {
 363                         cell-index = <2>;
 364                         device_type = "serial";
 365                         compatible = "ns16550";
 366                         reg = <0x11d500 0x100>;
 367                         clock-frequency = <0>;
 368                         interrupts = <37 2>;
 369                         interrupt-parent = <&mpic>;
 370                 };
 371
 372                 serial3: serial@11d600 {
 373                         cell-index = <3>;
 374                         device_type = "serial";
 375                         compatible = "ns16550";
 376                         reg = <0x11d600 0x100>;
 377                         clock-frequency = <0>;
 378                         interrupts = <37 2>;
 379                         interrupt-parent = <&mpic>;
 380                 };
 381
 382                 gpio0: gpio@130000 {
 383                         compatible = "fsl,p4080-gpio";
 384                         reg = <0x130000 0x1000>;
 385                         interrupts = <55 2>;
 386                         interrupt-parent = <&mpic>;
 387                         #gpio-cells = <2>;
 388                         gpio-controller;
 389                 };
 390
 391                 usb0: usb@210000 {
 392                         compatible = "fsl,p4080-usb2-mph",
 393                                         "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 394                         reg = <0x210000 0x1000>;
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         interrupt-parent = <&mpic>;
 398                         interrupts = <44 0x2>;
 399                         phy_type = "ulpi";
 400                 };
 401
 402                 usb1: usb@211000 {
 403                         compatible = "fsl,p4080-usb2-dr",
 404                                         "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 405                         reg = <0x211000 0x1000>;
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         interrupt-parent = <&mpic>;
 409                         interrupts = <45 0x2>;
 410                         dr_mode = "host";
 411                         phy_type = "ulpi";
 412                 };
 413         };
 414
 415         rapidio0: rapidio@ffe0c0000 {
 416                 #address-cells = <2>;
 417                 #size-cells = <2>;
 418                 compatible = "fsl,rapidio-delta";
 419                 reg = <0xf 0xfe0c0000 0 0x20000>;
 420                 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
 421                 interrupt-parent = <&mpic>;
 422                 /* err_irq bell_outb_irq bell_inb_irq
 423                         msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
 424                 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
 425         };
 426
 427         localbus@ffe124000 {
 428                 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
 429                 reg = <0xf 0xfe124000 0 0x1000>;
 430                 interrupts = <25 2>;
 431                 #address-cells = <2>;
 432                 #size-cells = <1>;
 433
 434                 ranges = <0 0 0xf 0xe8000000 0x08000000>;
 435
 436                 flash@0,0 {
 437                         compatible = "cfi-flash";
 438                         reg = <0 0 0x08000000>;
 439                         bank-width = <2>;
 440                         device-width = <2>;
 441                 };
 442         };
 443
 444         pci0: pcie@ffe200000 {
 445                 compatible = "fsl,p4080-pcie";
 446                 device_type = "pci";
 447                 #interrupt-cells = <1>;
 448                 #size-cells = <2>;
 449                 #address-cells = <3>;
 450                 reg = <0xf 0xfe200000 0 0x1000>;
 451                 bus-range = <0x0 0xff>;
 452                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 453                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 454                 clock-frequency = <0x1fca055>;
 455                 interrupt-parent = <&mpic>;
 456                 interrupts = <16 2>;
 457
 458                 interrupt-map-mask = <0xf800 0 0 7>;
 459                 interrupt-map = <
 460                         /* IDSEL 0x0 */
 461                         0000 0 0 1 &mpic 40 1
 462                         0000 0 0 2 &mpic 1 1
 463                         0000 0 0 3 &mpic 2 1
 464                         0000 0 0 4 &mpic 3 1
 465                         >;
 466                 pcie@0 {
 467                         reg = <0 0 0 0 0>;
 468                         #size-cells = <2>;
 469                         #address-cells = <3>;
 470                         device_type = "pci";
 471                         ranges = <0x02000000 0 0xe0000000
 472                                   0x02000000 0 0xe0000000
 473                                   0 0x20000000
 474
 475                                   0x01000000 0 0x00000000
 476                                   0x01000000 0 0x00000000
 477                                   0 0x00010000>;
 478                 };
 479         };
 480
 481         pci1: pcie@ffe201000 {
 482                 compatible = "fsl,p4080-pcie";
 483                 device_type = "pci";
 484                 #interrupt-cells = <1>;
 485                 #size-cells = <2>;
 486                 #address-cells = <3>;
 487                 reg = <0xf 0xfe201000 0 0x1000>;
 488                 bus-range = <0 0xff>;
 489                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 490                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 491                 clock-frequency = <0x1fca055>;
 492                 interrupt-parent = <&mpic>;
 493                 interrupts = <16 2>;
 494                 interrupt-map-mask = <0xf800 0 0 7>;
 495                 interrupt-map = <
 496                         /* IDSEL 0x0 */
 497                         0000 0 0 1 &mpic 41 1
 498                         0000 0 0 2 &mpic 5 1
 499                         0000 0 0 3 &mpic 6 1
 500                         0000 0 0 4 &mpic 7 1
 501                         >;
 502                 pcie@0 {
 503                         reg = <0 0 0 0 0>;
 504                         #size-cells = <2>;
 505                         #address-cells = <3>;
 506                         device_type = "pci";
 507                         ranges = <0x02000000 0 0xe0000000
 508                                   0x02000000 0 0xe0000000
 509                                   0 0x20000000
 510
 511                                   0x01000000 0 0x00000000
 512                                   0x01000000 0 0x00000000
 513                                   0 0x00010000>;
 514                 };
 515         };
 516
 517         pci2: pcie@ffe202000 {
 518                 compatible = "fsl,p4080-pcie";
 519                 device_type = "pci";
 520                 #interrupt-cells = <1>;
 521                 #size-cells = <2>;
 522                 #address-cells = <3>;
 523                 reg = <0xf 0xfe202000 0 0x1000>;
 524                 bus-range = <0x0 0xff>;
 525                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 526                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 527                 clock-frequency = <0x1fca055>;
 528                 interrupt-parent = <&mpic>;
 529                 interrupts = <16 2>;
 530                 interrupt-map-mask = <0xf800 0 0 7>;
 531                 interrupt-map = <
 532                         /* IDSEL 0x0 */
 533                         0000 0 0 1 &mpic 42 1
 534                         0000 0 0 2 &mpic 9 1
 535                         0000 0 0 3 &mpic 10 1
 536                         0000 0 0 4 &mpic 11 1
 537                         >;
 538                 pcie@0 {
 539                         reg = <0 0 0 0 0>;
 540                         #size-cells = <2>;
 541                         #address-cells = <3>;
 542                         device_type = "pci";
 543                         ranges = <0x02000000 0 0xe0000000
 544                                   0x02000000 0 0xe0000000
 545                                   0 0x20000000
 546
 547                                   0x01000000 0 0x00000000
 548                                   0x01000000 0 0x00000000
 549                                   0 0x00010000>;
 550                 };
 551         };
 552
 553 };