2 * P4080DS Device Tree Source
4 * Copyright 2009 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS";
43 cpu0: PowerPC,4080@0 {
46 next-level-cache = <&L2_0>;
50 cpu1: PowerPC,4080@1 {
53 next-level-cache = <&L2_1>;
57 cpu2: PowerPC,4080@2 {
60 next-level-cache = <&L2_2>;
64 cpu3: PowerPC,4080@3 {
67 next-level-cache = <&L2_3>;
71 cpu4: PowerPC,4080@4 {
74 next-level-cache = <&L2_4>;
78 cpu5: PowerPC,4080@5 {
81 next-level-cache = <&L2_5>;
85 cpu6: PowerPC,4080@6 {
88 next-level-cache = <&L2_6>;
92 cpu7: PowerPC,4080@7 {
95 next-level-cache = <&L2_7>;
102 device_type = "memory";
106 #address-cells = <1>;
109 compatible = "simple-bus";
110 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
111 reg = <0xf 0xfe000000 0 0x00001000>;
114 compatible = "fsl,corenet-law";
119 memory-controller@8000 {
120 compatible = "fsl,p4080-memory-controller";
121 reg = <0x8000 0x1000>;
122 interrupt-parent = <&mpic>;
123 interrupts = <0x12 2>;
126 memory-controller@9000 {
127 compatible = "fsl,p4080-memory-controller";
128 reg = <0x9000 0x1000>;
129 interrupt-parent = <&mpic>;
130 interrupts = <0x12 2>;
134 compatible = "fsl,corenet-cf";
135 reg = <0x18000 0x1000>;
136 fsl,ccf-num-csdids = <32>;
137 fsl,ccf-num-snoopids = <32>;
141 compatible = "fsl,p4080-pamu";
142 reg = <0x20000 0x10000>;
144 interrupt-parent = <&mpic>;
148 interrupt-controller;
149 #address-cells = <0>;
150 #interrupt-cells = <2>;
151 reg = <0x40000 0x40000>;
152 compatible = "chrp,open-pic";
153 device_type = "open-pic";
157 #address-cells = <1>;
159 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
160 reg = <0x100300 0x4>;
161 ranges = <0x0 0x100100 0x200>;
164 compatible = "fsl,p4080-dma-channel",
165 "fsl,eloplus-dma-channel";
168 interrupt-parent = <&mpic>;
172 compatible = "fsl,p4080-dma-channel",
173 "fsl,eloplus-dma-channel";
176 interrupt-parent = <&mpic>;
180 compatible = "fsl,p4080-dma-channel",
181 "fsl,eloplus-dma-channel";
184 interrupt-parent = <&mpic>;
188 compatible = "fsl,p4080-dma-channel",
189 "fsl,eloplus-dma-channel";
192 interrupt-parent = <&mpic>;
198 #address-cells = <1>;
200 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
201 reg = <0x101300 0x4>;
202 ranges = <0x0 0x101100 0x200>;
205 compatible = "fsl,p4080-dma-channel",
206 "fsl,eloplus-dma-channel";
209 interrupt-parent = <&mpic>;
213 compatible = "fsl,p4080-dma-channel",
214 "fsl,eloplus-dma-channel";
217 interrupt-parent = <&mpic>;
221 compatible = "fsl,p4080-dma-channel",
222 "fsl,eloplus-dma-channel";
225 interrupt-parent = <&mpic>;
229 compatible = "fsl,p4080-dma-channel",
230 "fsl,eloplus-dma-channel";
233 interrupt-parent = <&mpic>;
239 #address-cells = <1>;
241 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
242 reg = <0x110000 0x1000>;
243 interrupts = <53 0x2>;
244 interrupt-parent = <&mpic>;
245 fsl,espi-num-chipselects = <4>;
248 #address-cells = <1>;
250 compatible = "spansion,s25sl12801";
252 spi-max-frequency = <40000000>; /* input clock */
255 reg = <0x00000000 0x00100000>;
260 reg = <0x00100000 0x00500000>;
265 reg = <0x00600000 0x00100000>;
269 label = "file system";
270 reg = <0x00700000 0x00900000>;
276 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
277 reg = <0x114000 0x1000>;
279 interrupt-parent = <&mpic>;
280 voltage-ranges = <3300 3300>;
285 #address-cells = <1>;
288 compatible = "fsl-i2c";
289 reg = <0x118000 0x100>;
291 interrupt-parent = <&mpic>;
296 #address-cells = <1>;
299 compatible = "fsl-i2c";
300 reg = <0x118100 0x100>;
302 interrupt-parent = <&mpic>;
305 compatible = "at24,24c256";
309 compatible = "at24,24c256";
313 compatible = "dallas,ds3232";
315 interrupts = <0 0x1>;
316 interrupt-parent = <&mpic>;
321 #address-cells = <1>;
324 compatible = "fsl-i2c";
325 reg = <0x119000 0x100>;
327 interrupt-parent = <&mpic>;
332 #address-cells = <1>;
335 compatible = "fsl-i2c";
336 reg = <0x119100 0x100>;
338 interrupt-parent = <&mpic>;
342 serial0: serial@11c500 {
344 device_type = "serial";
345 compatible = "ns16550";
346 reg = <0x11c500 0x100>;
347 clock-frequency = <0>;
349 interrupt-parent = <&mpic>;
352 serial1: serial@11c600 {
354 device_type = "serial";
355 compatible = "ns16550";
356 reg = <0x11c600 0x100>;
357 clock-frequency = <0>;
359 interrupt-parent = <&mpic>;
362 serial2: serial@11d500 {
364 device_type = "serial";
365 compatible = "ns16550";
366 reg = <0x11d500 0x100>;
367 clock-frequency = <0>;
369 interrupt-parent = <&mpic>;
372 serial3: serial@11d600 {
374 device_type = "serial";
375 compatible = "ns16550";
376 reg = <0x11d600 0x100>;
377 clock-frequency = <0>;
379 interrupt-parent = <&mpic>;
383 compatible = "fsl,p4080-gpio";
384 reg = <0x130000 0x1000>;
386 interrupt-parent = <&mpic>;
392 compatible = "fsl,p4080-usb2-mph",
393 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
394 reg = <0x210000 0x1000>;
395 #address-cells = <1>;
397 interrupt-parent = <&mpic>;
398 interrupts = <44 0x2>;
403 compatible = "fsl,p4080-usb2-dr",
404 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
405 reg = <0x211000 0x1000>;
406 #address-cells = <1>;
408 interrupt-parent = <&mpic>;
409 interrupts = <45 0x2>;
415 rapidio0: rapidio@ffe0c0000 {
416 #address-cells = <2>;
418 compatible = "fsl,rapidio-delta";
419 reg = <0xf 0xfe0c0000 0 0x20000>;
420 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
421 interrupt-parent = <&mpic>;
422 /* err_irq bell_outb_irq bell_inb_irq
423 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
424 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
428 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
429 reg = <0xf 0xfe124000 0 0x1000>;
431 #address-cells = <2>;
434 ranges = <0 0 0xf 0xe8000000 0x08000000>;
437 compatible = "cfi-flash";
438 reg = <0 0 0x08000000>;
444 pci0: pcie@ffe200000 {
445 compatible = "fsl,p4080-pcie";
447 #interrupt-cells = <1>;
449 #address-cells = <3>;
450 reg = <0xf 0xfe200000 0 0x1000>;
451 bus-range = <0x0 0xff>;
452 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
453 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
454 clock-frequency = <0x1fca055>;
455 interrupt-parent = <&mpic>;
458 interrupt-map-mask = <0xf800 0 0 7>;
461 0000 0 0 1 &mpic 40 1
469 #address-cells = <3>;
471 ranges = <0x02000000 0 0xe0000000
472 0x02000000 0 0xe0000000
475 0x01000000 0 0x00000000
476 0x01000000 0 0x00000000
481 pci1: pcie@ffe201000 {
482 compatible = "fsl,p4080-pcie";
484 #interrupt-cells = <1>;
486 #address-cells = <3>;
487 reg = <0xf 0xfe201000 0 0x1000>;
488 bus-range = <0 0xff>;
489 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
490 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
491 clock-frequency = <0x1fca055>;
492 interrupt-parent = <&mpic>;
494 interrupt-map-mask = <0xf800 0 0 7>;
497 0000 0 0 1 &mpic 41 1
505 #address-cells = <3>;
507 ranges = <0x02000000 0 0xe0000000
508 0x02000000 0 0xe0000000
511 0x01000000 0 0x00000000
512 0x01000000 0 0x00000000
517 pci2: pcie@ffe202000 {
518 compatible = "fsl,p4080-pcie";
520 #interrupt-cells = <1>;
522 #address-cells = <3>;
523 reg = <0xf 0xfe202000 0 0x1000>;
524 bus-range = <0x0 0xff>;
525 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
526 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
527 clock-frequency = <0x1fca055>;
528 interrupt-parent = <&mpic>;
530 interrupt-map-mask = <0xf800 0 0 7>;
533 0000 0 0 1 &mpic 42 1
535 0000 0 0 3 &mpic 10 1
536 0000 0 0 4 &mpic 11 1
541 #address-cells = <3>;
543 ranges = <0x02000000 0 0xe0000000
544 0x02000000 0 0xe0000000
547 0x01000000 0 0x00000000
548 0x01000000 0 0x00000000