arch/powerpc/boot/dts/p2020rdb_camp_core1.dts

   1 /*
   2  * P2020 RDB Core1 Device Tree Source in CAMP mode.
   3  *
   4  * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
   5  * can be shared, all the other devices must be assigned to one core only.
   6  * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
   7  *
   8  * Please note to add "-b 1" for core1's dts compiling.
   9  *
  10  * Copyright 2009-2011 Freescale Semiconductor Inc.
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 /dts-v1/;
  19 / {
  20         model = "fsl,P2020";
  21         compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         aliases {
  26                 ethernet0 = &enet0;
  27                 serial0 = &serial0;
  28                 pci1 = &pci1;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,P2020@1 {
  36                         device_type = "cpu";
  37                         reg = <0x1>;
  38                         next-level-cache = <&L2>;
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44         };
  45
  46         soc@ffe00000 {
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 device_type = "soc";
  50                 compatible = "fsl,p2020-immr", "simple-bus";
  51                 ranges = <0x0  0x0 0xffe00000 0x100000>;
  52                 bus-frequency = <0>;            // Filled out by uboot.
  53
  54                 serial0: serial@4600 {
  55                         cell-index = <1>;
  56                         device_type = "serial";
  57                         compatible = "ns16550";
  58                         reg = <0x4600 0x100>;
  59                         clock-frequency = <0>;
  60                 };
  61
  62                 dma@c300 {
  63                         #address-cells = <1>;
  64                         #size-cells = <1>;
  65                         compatible = "fsl,eloplus-dma";
  66                         reg = <0xc300 0x4>;
  67                         ranges = <0x0 0xc100 0x200>;
  68                         cell-index = <1>;
  69                         dma-channel@0 {
  70                                 compatible = "fsl,eloplus-dma-channel";
  71                                 reg = <0x0 0x80>;
  72                                 cell-index = <0>;
  73                                 interrupt-parent = <&mpic>;
  74                                 interrupts = <76 2>;
  75                         };
  76                         dma-channel@80 {
  77                                 compatible = "fsl,eloplus-dma-channel";
  78                                 reg = <0x80 0x80>;
  79                                 cell-index = <1>;
  80                                 interrupt-parent = <&mpic>;
  81                                 interrupts = <77 2>;
  82                         };
  83                         dma-channel@100 {
  84                                 compatible = "fsl,eloplus-dma-channel";
  85                                 reg = <0x100 0x80>;
  86                                 cell-index = <2>;
  87                                 interrupt-parent = <&mpic>;
  88                                 interrupts = <78 2>;
  89                         };
  90                         dma-channel@180 {
  91                                 compatible = "fsl,eloplus-dma-channel";
  92                                 reg = <0x180 0x80>;
  93                                 cell-index = <3>;
  94                                 interrupt-parent = <&mpic>;
  95                                 interrupts = <79 2>;
  96                         };
  97                 };
  98
  99                 L2: l2-cache-controller@20000 {
 100                         compatible = "fsl,p2020-l2-cache-controller";
 101                         reg = <0x20000 0x1000>;
 102                         cache-line-size = <32>; // 32 bytes
 103                         cache-size = <0x80000>; // L2,512K
 104                         interrupt-parent = <&mpic>;
 105                 };
 106
 107
 108                 enet0: ethernet@24000 {
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111                         cell-index = <0>;
 112                         device_type = "network";
 113                         model = "eTSEC";
 114                         compatible = "gianfar";
 115                         reg = <0x24000 0x1000>;
 116                         ranges = <0x0 0x24000 0x1000>;
 117                         local-mac-address = [ 00 00 00 00 00 00 ];
 118                         interrupts = <29 2 30 2 34 2>;
 119                         interrupt-parent = <&mpic>;
 120                         fixed-link = <1 1 1000 0 0>;
 121                         phy-connection-type = "rgmii-id";
 122
 123                 };
 124
 125                 mpic: pic@40000 {
 126                         interrupt-controller;
 127                         #address-cells = <0>;
 128                         #interrupt-cells = <2>;
 129                         reg = <0x40000 0x40000>;
 130                         compatible = "chrp,open-pic";
 131                         device_type = "open-pic";
 132                         protected-sources = <
 133                         17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
 134                         16 20 21 22 23 28       /* L2, dma1, USB */
 135                         03 35 36 40 31 32 33    /* mdio, enet1, enet2 */
 136                         72 45 58 25             /* sdhci, crypto , pci */
 137                         >;
 138                 };
 139
 140                 msi@41600 {
 141                         compatible = "fsl,p2020-msi", "fsl,mpic-msi";
 142                         reg = <0x41600 0x80>;
 143                         msi-available-ranges = <0 0x100>;
 144                         interrupts = <
 145                                 0xe0 0
 146                                 0xe1 0
 147                                 0xe2 0
 148                                 0xe3 0
 149                                 0xe4 0
 150                                 0xe5 0
 151                                 0xe6 0
 152                                 0xe7 0>;
 153                         interrupt-parent = <&mpic>;
 154                 };
 155         };
 156
 157         pci1: pcie@ffe0a000 {
 158                 compatible = "fsl,mpc8548-pcie";
 159                 device_type = "pci";
 160                 #interrupt-cells = <1>;
 161                 #size-cells = <2>;
 162                 #address-cells = <3>;
 163                 reg = <0 0xffe0a000 0 0x1000>;
 164                 bus-range = <0 255>;
 165                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 166                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
 167                 clock-frequency = <33333333>;
 168                 interrupt-parent = <&mpic>;
 169                 interrupts = <26 2>;
 170                 pcie@0 {
 171                         reg = <0x0 0x0 0x0 0x0 0x0>;
 172                         #size-cells = <2>;
 173                         #address-cells = <3>;
 174                         device_type = "pci";
 175                         ranges = <0x2000000 0x0 0x80000000
 176                                   0x2000000 0x0 0x80000000
 177                                   0x0 0x20000000
 178
 179                                   0x1000000 0x0 0x0
 180                                   0x1000000 0x0 0x0
 181                                   0x0 0x100000>;
 182                 };
 183         };
 184 };