arch/powerpc/boot/dts/p2020rdb_camp_core0.dts

   1 /*
   2  * P2020 RDB  Core0 Device Tree Source in CAMP mode.
   3  *
   4  * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
   5  * can be shared, all the other devices must be assigned to one core only.
   6  * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
   7  * eth1, eth2, sdhc, crypto, global-util, pci0.
   8  *
   9  * Copyright 2009-2011 Freescale Semiconductor Inc.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 /dts-v1/;
  18 / {
  19         model = "fsl,P2020";
  20         compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 ethernet1 = &enet1;
  26                 ethernet2 = &enet2;
  27                 serial0 = &serial0;
  28                 pci0 = &pci0;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,P2020@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         next-level-cache = <&L2>;
  39                 };
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44         };
  45
  46         soc@ffe00000 {
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 device_type = "soc";
  50                 compatible = "fsl,p2020-immr", "simple-bus";
  51                 ranges = <0x0  0x0 0xffe00000 0x100000>;
  52                 bus-frequency = <0>;            // Filled out by uboot.
  53
  54                 ecm-law@0 {
  55                         compatible = "fsl,ecm-law";
  56                         reg = <0x0 0x1000>;
  57                         fsl,num-laws = <12>;
  58                 };
  59
  60                 ecm@1000 {
  61                         compatible = "fsl,p2020-ecm", "fsl,ecm";
  62                         reg = <0x1000 0x1000>;
  63                         interrupts = <17 2>;
  64                         interrupt-parent = <&mpic>;
  65                 };
  66
  67                 memory-controller@2000 {
  68                         compatible = "fsl,p2020-memory-controller";
  69                         reg = <0x2000 0x1000>;
  70                         interrupt-parent = <&mpic>;
  71                         interrupts = <18 2>;
  72                 };
  73
  74                 i2c@3000 {
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                         cell-index = <0>;
  78                         compatible = "fsl-i2c";
  79                         reg = <0x3000 0x100>;
  80                         interrupts = <43 2>;
  81                         interrupt-parent = <&mpic>;
  82                         dfsrr;
  83                         rtc@68 {
  84                                 compatible = "dallas,ds1339";
  85                                 reg = <0x68>;
  86                         };
  87                 };
  88
  89                 i2c@3100 {
  90                         #address-cells = <1>;
  91                         #size-cells = <0>;
  92                         cell-index = <1>;
  93                         compatible = "fsl-i2c";
  94                         reg = <0x3100 0x100>;
  95                         interrupts = <43 2>;
  96                         interrupt-parent = <&mpic>;
  97                         dfsrr;
  98                 };
  99
 100                 serial0: serial@4500 {
 101                         cell-index = <0>;
 102                         device_type = "serial";
 103                         compatible = "ns16550";
 104                         reg = <0x4500 0x100>;
 105                         clock-frequency = <0>;
 106                 };
 107
 108                 spi@7000 {
 109                         cell-index = <0>;
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         compatible = "fsl,espi";
 113                         reg = <0x7000 0x1000>;
 114                         interrupts = <59 0x2>;
 115                         interrupt-parent = <&mpic>;
 116                         mode = "cpu";
 117
 118                         fsl_m25p80@0 {
 119                                 #address-cells = <1>;
 120                                 #size-cells = <1>;
 121                                 compatible = "fsl,espi-flash";
 122                                 reg = <0>;
 123                                 linux,modalias = "fsl_m25p80";
 124                                 modal = "s25sl128b";
 125                                 spi-max-frequency = <50000000>;
 126                                 mode = <0>;
 127
 128                                 partition@0 {
 129                                         /* 512KB for u-boot Bootloader Image */
 130                                         reg = <0x0 0x00080000>;
 131                                         label = "SPI (RO) U-Boot Image";
 132                                         read-only;
 133                                 };
 134
 135                                 partition@80000 {
 136                                         /* 512KB for DTB Image */
 137                                         reg = <0x00080000 0x00080000>;
 138                                         label = "SPI (RO) DTB Image";
 139                                         read-only;
 140                                 };
 141
 142                                 partition@100000 {
 143                                         /* 4MB for Linux Kernel Image */
 144                                         reg = <0x00100000 0x00400000>;
 145                                         label = "SPI (RO) Linux Kernel Image";
 146                                         read-only;
 147                                 };
 148
 149                                 partition@500000 {
 150                                         /* 4MB for Compressed RFS Image */
 151                                         reg = <0x00500000 0x00400000>;
 152                                         label = "SPI (RO) Compressed RFS Image";
 153                                         read-only;
 154                                 };
 155
 156                                 partition@900000 {
 157                                         /* 7MB for JFFS2 based RFS */
 158                                         reg = <0x00900000 0x00700000>;
 159                                         label = "SPI (RW) JFFS2 RFS";
 160                                 };
 161                         };
 162                 };
 163
 164                 gpio: gpio-controller@f000 {
 165                         #gpio-cells = <2>;
 166                         compatible = "fsl,mpc8572-gpio";
 167                         reg = <0xf000 0x100>;
 168                         interrupts = <47 0x2>;
 169                         interrupt-parent = <&mpic>;
 170                         gpio-controller;
 171                 };
 172
 173                 L2: l2-cache-controller@20000 {
 174                         compatible = "fsl,p2020-l2-cache-controller";
 175                         reg = <0x20000 0x1000>;
 176                         cache-line-size = <32>; // 32 bytes
 177                         cache-size = <0x80000>; // L2,512K
 178                         interrupt-parent = <&mpic>;
 179                         interrupts = <16 2>;
 180                 };
 181
 182                 dma@21300 {
 183                         #address-cells = <1>;
 184                         #size-cells = <1>;
 185                         compatible = "fsl,eloplus-dma";
 186                         reg = <0x21300 0x4>;
 187                         ranges = <0x0 0x21100 0x200>;
 188                         cell-index = <0>;
 189                         dma-channel@0 {
 190                                 compatible = "fsl,eloplus-dma-channel";
 191                                 reg = <0x0 0x80>;
 192                                 cell-index = <0>;
 193                                 interrupt-parent = <&mpic>;
 194                                 interrupts = <20 2>;
 195                         };
 196                         dma-channel@80 {
 197                                 compatible = "fsl,eloplus-dma-channel";
 198                                 reg = <0x80 0x80>;
 199                                 cell-index = <1>;
 200                                 interrupt-parent = <&mpic>;
 201                                 interrupts = <21 2>;
 202                         };
 203                         dma-channel@100 {
 204                                 compatible = "fsl,eloplus-dma-channel";
 205                                 reg = <0x100 0x80>;
 206                                 cell-index = <2>;
 207                                 interrupt-parent = <&mpic>;
 208                                 interrupts = <22 2>;
 209                         };
 210                         dma-channel@180 {
 211                                 compatible = "fsl,eloplus-dma-channel";
 212                                 reg = <0x180 0x80>;
 213                                 cell-index = <3>;
 214                                 interrupt-parent = <&mpic>;
 215                                 interrupts = <23 2>;
 216                         };
 217                 };
 218
 219                 usb@22000 {
 220                         #address-cells = <1>;
 221                         #size-cells = <0>;
 222                         compatible = "fsl-usb2-dr";
 223                         reg = <0x22000 0x1000>;
 224                         interrupt-parent = <&mpic>;
 225                         interrupts = <28 0x2>;
 226                         phy_type = "ulpi";
 227                 };
 228
 229                 mdio@24520 {
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         compatible = "fsl,gianfar-mdio";
 233                         reg = <0x24520 0x20>;
 234
 235                         phy0: ethernet-phy@0 {
 236                                 interrupt-parent = <&mpic>;
 237                                 interrupts = <3 1>;
 238                                 reg = <0x0>;
 239                         };
 240                         phy1: ethernet-phy@1 {
 241                                 interrupt-parent = <&mpic>;
 242                                 interrupts = <3 1>;
 243                                 reg = <0x1>;
 244                         };
 245                 };
 246
 247                 mdio@25520 {
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         compatible = "fsl,gianfar-tbi";
 251                         reg = <0x26520 0x20>;
 252
 253                         tbi0: tbi-phy@11 {
 254                                 reg = <0x11>;
 255                                 device_type = "tbi-phy";
 256                         };
 257                 };
 258
 259                 enet1: ethernet@25000 {
 260                         #address-cells = <1>;
 261                         #size-cells = <1>;
 262                         cell-index = <1>;
 263                         device_type = "network";
 264                         model = "eTSEC";
 265                         compatible = "gianfar";
 266                         reg = <0x25000 0x1000>;
 267                         ranges = <0x0 0x25000 0x1000>;
 268                         local-mac-address = [ 00 00 00 00 00 00 ];
 269                         interrupts = <35 2 36 2 40 2>;
 270                         interrupt-parent = <&mpic>;
 271                         tbi-handle = <&tbi0>;
 272                         phy-handle = <&phy0>;
 273                         phy-connection-type = "sgmii";
 274
 275                 };
 276
 277                 enet2: ethernet@26000 {
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280                         cell-index = <2>;
 281                         device_type = "network";
 282                         model = "eTSEC";
 283                         compatible = "gianfar";
 284                         reg = <0x26000 0x1000>;
 285                         ranges = <0x0 0x26000 0x1000>;
 286                         local-mac-address = [ 00 00 00 00 00 00 ];
 287                         interrupts = <31 2 32 2 33 2>;
 288                         interrupt-parent = <&mpic>;
 289                         phy-handle = <&phy1>;
 290                         phy-connection-type = "rgmii-id";
 291                 };
 292
 293                 sdhci@2e000 {
 294                         compatible = "fsl,p2020-esdhc", "fsl,esdhc";
 295                         reg = <0x2e000 0x1000>;
 296                         interrupts = <72 0x2>;
 297                         interrupt-parent = <&mpic>;
 298                         /* Filled in by U-Boot */
 299                         clock-frequency = <0>;
 300                 };
 301
 302                 crypto@30000 {
 303                         compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
 304                                      "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 305                         reg = <0x30000 0x10000>;
 306                         interrupts = <45 2 58 2>;
 307                         interrupt-parent = <&mpic>;
 308                         fsl,num-channels = <4>;
 309                         fsl,channel-fifo-len = <24>;
 310                         fsl,exec-units-mask = <0xbfe>;
 311                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 312                 };
 313
 314                 mpic: pic@40000 {
 315                         interrupt-controller;
 316                         #address-cells = <0>;
 317                         #interrupt-cells = <2>;
 318                         reg = <0x40000 0x40000>;
 319                         compatible = "chrp,open-pic";
 320                         device_type = "open-pic";
 321                         protected-sources = <
 322                         42 76 77 78 79 /* serial1 , dma2 */
 323                         29 30 34 26 /* enet0, pci1 */
 324                         0xe0 0xe1 0xe2 0xe3 /* msi */
 325                         0xe4 0xe5 0xe6 0xe7
 326                         >;
 327                 };
 328
 329                 global-utilities@e0000 {
 330                         compatible = "fsl,p2020-guts";
 331                         reg = <0xe0000 0x1000>;
 332                         fsl,has-rstcr;
 333                 };
 334         };
 335
 336         pci0: pcie@ffe09000 {
 337                 compatible = "fsl,mpc8548-pcie";
 338                 device_type = "pci";
 339                 #interrupt-cells = <1>;
 340                 #size-cells = <2>;
 341                 #address-cells = <3>;
 342                 reg = <0 0xffe09000 0 0x1000>;
 343                 bus-range = <0 255>;
 344                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 345                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
 346                 clock-frequency = <33333333>;
 347                 interrupt-parent = <&mpic>;
 348                 interrupts = <25 2>;
 349                 pcie@0 {
 350                         reg = <0x0 0x0 0x0 0x0 0x0>;
 351                         #size-cells = <2>;
 352                         #address-cells = <3>;
 353                         device_type = "pci";
 354                         ranges = <0x2000000 0x0 0xa0000000
 355                                   0x2000000 0x0 0xa0000000
 356                                   0x0 0x20000000
 357
 358                                   0x1000000 0x0 0x0
 359                                   0x1000000 0x0 0x0
 360                                   0x0 0x100000>;
 361                 };
 362         };
 363 };