2 * P1022 DS 36Bit Physical Address Map Device Tree Source
4 * Copyright 2010 Freescale Semiconductor, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
14 compatible = "fsl,P1022DS";
17 interrupt-parent = <&mpic>;
36 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
47 device_type = "memory";
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2 0 0>;
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000
59 0x2 0x0 0x0 0xffa00000 0x00040000
60 0x3 0x0 0xf 0xffdf0000 0x00008000>;
65 compatible = "cfi-flash";
66 reg = <0x0 0x0 0x8000000>;
71 reg = <0x0 0x03000000>;
72 label = "ramdisk-nor";
77 reg = <0x03000000 0x00e00000>;
78 label = "diagnostic-nor";
83 reg = <0x03e00000 0x00200000>;
89 reg = <0x04000000 0x00400000>;
95 reg = <0x04400000 0x03b00000>;
100 reg = <0x07f00000 0x00080000>;
106 reg = <0x07f80000 0x00080000>;
107 label = "u-boot-nor";
113 #address-cells = <1>;
115 compatible = "fsl,elbc-fcm-nand";
116 reg = <0x2 0x0 0x40000>;
119 reg = <0x0 0x02000000>;
120 label = "u-boot-nand";
125 reg = <0x02000000 0x10000000>;
126 label = "jffs2-nand";
130 reg = <0x12000000 0x10000000>;
131 label = "ramdisk-nand";
136 reg = <0x22000000 0x04000000>;
137 label = "kernel-nand";
141 reg = <0x26000000 0x01000000>;
147 reg = <0x27000000 0x19000000>;
148 label = "reserved-nand";
153 compatible = "fsl,p1022ds-pixis";
155 interrupt-parent = <&mpic>;
157 * IRQ8 is generated if the "EVENT" switch is pressed
158 * and PX_CTL[EVESEL] is set to 00.
160 interrupts = <8 8 0 0>;
165 #address-cells = <1>;
168 compatible = "fsl,p1022-immr", "simple-bus";
169 ranges = <0x0 0xf 0xffe00000 0x100000>;
170 bus-frequency = <0>; // Filled out by uboot.
173 compatible = "fsl,ecm-law";
179 compatible = "fsl,p1022-ecm", "fsl,ecm";
180 reg = <0x1000 0x1000>;
181 interrupts = <16 2 0 0>;
184 memory-controller@2000 {
185 compatible = "fsl,p1022-memory-controller";
186 reg = <0x2000 0x1000>;
187 interrupts = <16 2 0 0>;
191 #address-cells = <1>;
194 compatible = "fsl-i2c";
195 reg = <0x3000 0x100>;
196 interrupts = <43 2 0 0>;
201 #address-cells = <1>;
204 compatible = "fsl-i2c";
205 reg = <0x3100 0x100>;
206 interrupts = <43 2 0 0>;
210 compatible = "wlf,wm8776";
213 * clock-frequency will be set by U-Boot if
214 * the clock is enabled.
219 serial0: serial@4500 {
221 device_type = "serial";
222 compatible = "ns16550";
223 reg = <0x4500 0x100>;
224 clock-frequency = <0>;
225 interrupts = <42 2 0 0>;
228 serial1: serial@4600 {
230 device_type = "serial";
231 compatible = "ns16550";
232 reg = <0x4600 0x100>;
233 clock-frequency = <0>;
234 interrupts = <42 2 0 0>;
239 #address-cells = <1>;
241 compatible = "fsl,espi";
242 reg = <0x7000 0x1000>;
243 interrupts = <59 0x2 0 0>;
244 espi,num-ss-bits = <4>;
248 #address-cells = <1>;
250 compatible = "fsl,espi-flash";
252 linux,modalias = "fsl_m25p80";
253 spi-max-frequency = <40000000>; /* input clock */
255 label = "u-boot-spi";
256 reg = <0x00000000 0x00100000>;
260 label = "kernel-spi";
261 reg = <0x00100000 0x00500000>;
266 reg = <0x00600000 0x00100000>;
270 label = "file system-spi";
271 reg = <0x00700000 0x00900000>;
277 compatible = "fsl,mpc8610-ssi";
279 reg = <0x15000 0x100>;
280 interrupts = <75 2 0 0>;
281 fsl,mode = "i2s-slave";
282 codec-handle = <&wm8776>;
283 fsl,playback-dma = <&dma00>;
284 fsl,capture-dma = <&dma01>;
285 fsl,fifo-depth = <15>;
286 fsl,ssi-asynchronous;
290 #address-cells = <1>;
292 compatible = "fsl,eloplus-dma";
294 ranges = <0x0 0xc100 0x200>;
296 dma00: dma-channel@0 {
297 compatible = "fsl,ssi-dma-channel";
300 interrupts = <76 2 0 0>;
302 dma01: dma-channel@80 {
303 compatible = "fsl,ssi-dma-channel";
306 interrupts = <77 2 0 0>;
309 compatible = "fsl,eloplus-dma-channel";
312 interrupts = <78 2 0 0>;
315 compatible = "fsl,eloplus-dma-channel";
318 interrupts = <79 2 0 0>;
322 gpio: gpio-controller@f000 {
324 compatible = "fsl,mpc8572-gpio";
325 reg = <0xf000 0x100>;
326 interrupts = <47 0x2 0 0>;
330 L2: l2-cache-controller@20000 {
331 compatible = "fsl,p1022-l2-cache-controller";
332 reg = <0x20000 0x1000>;
333 cache-line-size = <32>; // 32 bytes
334 cache-size = <0x40000>; // L2, 256K
335 interrupts = <16 2 0 0>;
339 #address-cells = <1>;
341 compatible = "fsl,eloplus-dma";
343 ranges = <0x0 0x21100 0x200>;
346 compatible = "fsl,eloplus-dma-channel";
349 interrupts = <20 2 0 0>;
352 compatible = "fsl,eloplus-dma-channel";
355 interrupts = <21 2 0 0>;
358 compatible = "fsl,eloplus-dma-channel";
361 interrupts = <22 2 0 0>;
364 compatible = "fsl,eloplus-dma-channel";
367 interrupts = <23 2 0 0>;
372 #address-cells = <1>;
374 compatible = "fsl-usb2-dr";
375 reg = <0x22000 0x1000>;
376 interrupts = <28 0x2 0 0>;
381 #address-cells = <1>;
383 compatible = "fsl,etsec2-mdio";
384 reg = <0x24000 0x1000 0xb0030 0x4>;
386 phy0: ethernet-phy@0 {
387 interrupts = <3 1 0 0>;
390 phy1: ethernet-phy@1 {
391 interrupts = <9 1 0 0>;
397 #address-cells = <1>;
399 compatible = "fsl,etsec2-mdio";
400 reg = <0x25000 0x1000 0xb1030 0x4>;
403 enet0: ethernet@B0000 {
404 #address-cells = <1>;
407 device_type = "network";
409 compatible = "fsl,etsec2";
410 fsl,num_rx_queues = <0x8>;
411 fsl,num_tx_queues = <0x8>;
414 local-mac-address = [ 00 00 00 00 00 00 ];
415 fixed-link = <1 1 1000 0 0>;
416 phy-handle = <&phy0>;
417 phy-connection-type = "rgmii-id";
419 #address-cells = <1>;
421 reg = <0xB0000 0x1000>;
422 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
425 #address-cells = <1>;
427 reg = <0xB4000 0x1000>;
428 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
432 enet1: ethernet@B1000 {
433 #address-cells = <1>;
436 device_type = "network";
438 compatible = "fsl,etsec2";
439 fsl,num_rx_queues = <0x8>;
440 fsl,num_tx_queues = <0x8>;
441 local-mac-address = [ 00 00 00 00 00 00 ];
442 fixed-link = <1 1 1000 0 0>;
443 phy-handle = <&phy1>;
444 phy-connection-type = "rgmii-id";
446 #address-cells = <1>;
448 reg = <0xB1000 0x1000>;
449 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
452 #address-cells = <1>;
454 reg = <0xB5000 0x1000>;
455 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
460 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
461 reg = <0x2e000 0x1000>;
462 interrupts = <72 0x2 0 0>;
463 fsl,sdhci-auto-cmd12;
464 /* Filled in by U-Boot */
465 clock-frequency = <0>;
469 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
470 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
472 reg = <0x30000 0x10000>;
473 interrupts = <45 2 0 0 58 2 0 0>;
474 fsl,num-channels = <4>;
475 fsl,channel-fifo-len = <24>;
476 fsl,exec-units-mask = <0x97c>;
477 fsl,descriptor-types-mask = <0x3a30abf>;
481 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
482 reg = <0x18000 0x1000>;
484 interrupts = <74 0x2 0 0>;
488 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
489 reg = <0x19000 0x1000>;
491 interrupts = <41 0x2 0 0>;
495 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
496 reg = <0xe0070 0x20>;
500 compatible = "fsl,diu", "fsl,p1022-diu";
501 reg = <0x10000 1000>;
502 interrupts = <64 2 0 0>;
506 compatible = "fsl,mpic-global-timer";
507 reg = <0x41100 0x100 0x41300 4>;
508 interrupts = <0 0 3 0
515 compatible = "fsl,mpic-global-timer";
516 reg = <0x42100 0x100 0x42300 4>;
517 interrupts = <4 0 3 0
524 interrupt-controller;
525 #address-cells = <0>;
526 #interrupt-cells = <4>;
527 reg = <0x40000 0x40000>;
528 compatible = "fsl,mpic";
529 device_type = "open-pic";
533 compatible = "fsl,p1022-msi", "fsl,mpic-msi";
534 reg = <0x41600 0x80>;
535 msi-available-ranges = <0 0x100>;
547 global-utilities@e0000 { //global utilities block
548 compatible = "fsl,p1022-guts";
549 reg = <0xe0000 0x1000>;
554 pci0: pcie@fffe09000 {
555 compatible = "fsl,p1022-pcie";
557 #interrupt-cells = <1>;
559 #address-cells = <3>;
560 reg = <0xf 0xffe09000 0 0x1000>;
562 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
563 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
564 clock-frequency = <33333333>;
565 interrupts = <16 2 0 0>;
566 interrupt-map-mask = <0xf800 0 0 7>;
575 reg = <0x0 0x0 0x0 0x0 0x0>;
577 #address-cells = <3>;
579 ranges = <0x2000000 0x0 0xe0000000
580 0x2000000 0x0 0xe0000000
589 pci1: pcie@fffe0a000 {
590 compatible = "fsl,p1022-pcie";
592 #interrupt-cells = <1>;
594 #address-cells = <3>;
595 reg = <0xf 0xffe0a000 0 0x1000>;
597 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
598 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
599 clock-frequency = <33333333>;
600 interrupts = <16 2 0 0>;
601 interrupt-map-mask = <0xf800 0 0 7>;
610 reg = <0x0 0x0 0x0 0x0 0x0>;
612 #address-cells = <3>;
614 ranges = <0x2000000 0x0 0xe0000000
615 0x2000000 0x0 0xe0000000
625 pci2: pcie@fffe0b000 {
626 compatible = "fsl,p1022-pcie";
628 #interrupt-cells = <1>;
630 #address-cells = <3>;
631 reg = <0xf 0xffe0b000 0 0x1000>;
633 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
634 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
635 clock-frequency = <33333333>;
636 interrupts = <16 2 0 0>;
637 interrupt-map-mask = <0xf800 0 0 7>;
642 0000 0 0 3 &mpic 10 1
643 0000 0 0 4 &mpic 11 1
646 reg = <0x0 0x0 0x0 0x0 0x0>;
648 #address-cells = <3>;
650 ranges = <0x2000000 0x0 0xe0000000
651 0x2000000 0x0 0xe0000000