2 * P1022 DS 36Bit Physical Address Map Device Tree Source
4 * Copyright 2010 Freescale Semiconductor, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
14 compatible = "fsl,P1022DS";
17 interrupt-parent = <&mpic>;
36 next-level-cache = <&L2>;
42 next-level-cache = <&L2>;
47 device_type = "memory";
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2 0 0>;
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000
59 0x2 0x0 0x0 0xffa00000 0x00040000
60 0x3 0x0 0xf 0xffdf0000 0x00008000>;
65 compatible = "cfi-flash";
66 reg = <0x0 0x0 0x8000000>;
71 reg = <0x0 0x03000000>;
72 label = "ramdisk-nor";
77 reg = <0x03000000 0x00e00000>;
78 label = "diagnostic-nor";
83 reg = <0x03e00000 0x00200000>;
89 reg = <0x04000000 0x00400000>;
95 reg = <0x04400000 0x03b00000>;
100 reg = <0x07f00000 0x00080000>;
106 reg = <0x07f80000 0x00080000>;
107 label = "u-boot-nor";
113 #address-cells = <1>;
115 compatible = "fsl,elbc-fcm-nand";
116 reg = <0x2 0x0 0x40000>;
119 reg = <0x0 0x02000000>;
120 label = "u-boot-nand";
125 reg = <0x02000000 0x10000000>;
126 label = "jffs2-nand";
130 reg = <0x12000000 0x10000000>;
131 label = "ramdisk-nand";
136 reg = <0x22000000 0x04000000>;
137 label = "kernel-nand";
141 reg = <0x26000000 0x01000000>;
147 reg = <0x27000000 0x19000000>;
148 label = "reserved-nand";
153 compatible = "fsl,p1022ds-pixis";
155 interrupt-parent = <&mpic>;
157 * IRQ8 is generated if the "EVENT" switch is pressed
158 * and PX_CTL[EVESEL] is set to 00.
160 interrupts = <8 8 0 0>;
165 #address-cells = <1>;
168 compatible = "fsl,p1022-immr", "simple-bus";
169 ranges = <0x0 0xf 0xffe00000 0x100000>;
170 bus-frequency = <0>; // Filled out by uboot.
173 compatible = "fsl,ecm-law";
179 compatible = "fsl,p1022-ecm", "fsl,ecm";
180 reg = <0x1000 0x1000>;
181 interrupts = <16 2 0 0>;
184 memory-controller@2000 {
185 compatible = "fsl,p1022-memory-controller";
186 reg = <0x2000 0x1000>;
187 interrupts = <16 2 0 0>;
191 #address-cells = <1>;
194 compatible = "fsl-i2c";
195 reg = <0x3000 0x100>;
196 interrupts = <43 2 0 0>;
201 #address-cells = <1>;
204 compatible = "fsl-i2c";
205 reg = <0x3100 0x100>;
206 interrupts = <43 2 0 0>;
210 compatible = "wlf,wm8776";
212 /* MCLK source is a stand-alone oscillator */
213 clock-frequency = <12288000>;
217 serial0: serial@4500 {
219 device_type = "serial";
220 compatible = "ns16550";
221 reg = <0x4500 0x100>;
222 clock-frequency = <0>;
223 interrupts = <42 2 0 0>;
226 serial1: serial@4600 {
228 device_type = "serial";
229 compatible = "ns16550";
230 reg = <0x4600 0x100>;
231 clock-frequency = <0>;
232 interrupts = <42 2 0 0>;
237 #address-cells = <1>;
239 compatible = "fsl,espi";
240 reg = <0x7000 0x1000>;
241 interrupts = <59 0x2 0 0>;
242 espi,num-ss-bits = <4>;
246 #address-cells = <1>;
248 compatible = "fsl,espi-flash";
250 linux,modalias = "fsl_m25p80";
251 spi-max-frequency = <40000000>; /* input clock */
253 label = "u-boot-spi";
254 reg = <0x00000000 0x00100000>;
258 label = "kernel-spi";
259 reg = <0x00100000 0x00500000>;
264 reg = <0x00600000 0x00100000>;
268 label = "file system-spi";
269 reg = <0x00700000 0x00900000>;
275 compatible = "fsl,mpc8610-ssi";
277 reg = <0x15000 0x100>;
278 interrupts = <75 2 0 0>;
279 fsl,mode = "i2s-slave";
280 codec-handle = <&wm8776>;
281 fsl,playback-dma = <&dma00>;
282 fsl,capture-dma = <&dma01>;
283 fsl,fifo-depth = <16>;
287 #address-cells = <1>;
289 compatible = "fsl,eloplus-dma";
291 ranges = <0x0 0xc100 0x200>;
293 dma00: dma-channel@0 {
294 compatible = "fsl,ssi-dma-channel";
297 interrupts = <76 2 0 0>;
299 dma01: dma-channel@80 {
300 compatible = "fsl,ssi-dma-channel";
303 interrupts = <77 2 0 0>;
306 compatible = "fsl,eloplus-dma-channel";
309 interrupts = <78 2 0 0>;
312 compatible = "fsl,eloplus-dma-channel";
315 interrupts = <79 2 0 0>;
319 gpio: gpio-controller@f000 {
321 compatible = "fsl,mpc8572-gpio";
322 reg = <0xf000 0x100>;
323 interrupts = <47 0x2 0 0>;
327 L2: l2-cache-controller@20000 {
328 compatible = "fsl,p1022-l2-cache-controller";
329 reg = <0x20000 0x1000>;
330 cache-line-size = <32>; // 32 bytes
331 cache-size = <0x40000>; // L2, 256K
332 interrupts = <16 2 0 0>;
336 #address-cells = <1>;
338 compatible = "fsl,eloplus-dma";
340 ranges = <0x0 0x21100 0x200>;
343 compatible = "fsl,eloplus-dma-channel";
346 interrupts = <20 2 0 0>;
349 compatible = "fsl,eloplus-dma-channel";
352 interrupts = <21 2 0 0>;
355 compatible = "fsl,eloplus-dma-channel";
358 interrupts = <22 2 0 0>;
361 compatible = "fsl,eloplus-dma-channel";
364 interrupts = <23 2 0 0>;
369 #address-cells = <1>;
371 compatible = "fsl-usb2-dr";
372 reg = <0x22000 0x1000>;
373 interrupts = <28 0x2 0 0>;
378 #address-cells = <1>;
380 compatible = "fsl,etsec2-mdio";
381 reg = <0x24000 0x1000 0xb0030 0x4>;
383 phy0: ethernet-phy@0 {
384 interrupts = <3 1 0 0>;
387 phy1: ethernet-phy@1 {
388 interrupts = <9 1 0 0>;
394 #address-cells = <1>;
396 compatible = "fsl,etsec2-mdio";
397 reg = <0x25000 0x1000 0xb1030 0x4>;
400 enet0: ethernet@B0000 {
401 #address-cells = <1>;
404 device_type = "network";
406 compatible = "fsl,etsec2";
407 fsl,num_rx_queues = <0x8>;
408 fsl,num_tx_queues = <0x8>;
411 local-mac-address = [ 00 00 00 00 00 00 ];
412 fixed-link = <1 1 1000 0 0>;
413 phy-handle = <&phy0>;
414 phy-connection-type = "rgmii-id";
416 #address-cells = <1>;
418 reg = <0xB0000 0x1000>;
419 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
422 #address-cells = <1>;
424 reg = <0xB4000 0x1000>;
425 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
429 enet1: ethernet@B1000 {
430 #address-cells = <1>;
433 device_type = "network";
435 compatible = "fsl,etsec2";
436 fsl,num_rx_queues = <0x8>;
437 fsl,num_tx_queues = <0x8>;
438 local-mac-address = [ 00 00 00 00 00 00 ];
439 fixed-link = <1 1 1000 0 0>;
440 phy-handle = <&phy1>;
441 phy-connection-type = "rgmii-id";
443 #address-cells = <1>;
445 reg = <0xB1000 0x1000>;
446 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
449 #address-cells = <1>;
451 reg = <0xB5000 0x1000>;
452 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
457 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
458 reg = <0x2e000 0x1000>;
459 interrupts = <72 0x2 0 0>;
460 fsl,sdhci-auto-cmd12;
461 /* Filled in by U-Boot */
462 clock-frequency = <0>;
466 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
467 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
469 reg = <0x30000 0x10000>;
470 interrupts = <45 2 0 0 58 2 0 0>;
471 fsl,num-channels = <4>;
472 fsl,channel-fifo-len = <24>;
473 fsl,exec-units-mask = <0x97c>;
474 fsl,descriptor-types-mask = <0x3a30abf>;
478 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
479 reg = <0x18000 0x1000>;
481 interrupts = <74 0x2 0 0>;
485 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
486 reg = <0x19000 0x1000>;
488 interrupts = <41 0x2 0 0>;
492 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
493 reg = <0xe0070 0x20>;
497 compatible = "fsl,diu", "fsl,p1022-diu";
498 reg = <0x10000 1000>;
499 interrupts = <64 2 0 0>;
503 compatible = "fsl,mpic-global-timer";
504 reg = <0x41100 0x100 0x41300 4>;
505 interrupts = <0 0 3 0
512 compatible = "fsl,mpic-global-timer";
513 reg = <0x42100 0x100 0x42300 4>;
514 interrupts = <4 0 3 0
521 interrupt-controller;
522 #address-cells = <0>;
523 #interrupt-cells = <4>;
524 reg = <0x40000 0x40000>;
525 compatible = "fsl,mpic";
526 device_type = "open-pic";
530 compatible = "fsl,p1022-msi", "fsl,mpic-msi";
531 reg = <0x41600 0x80>;
532 msi-available-ranges = <0 0x100>;
544 global-utilities@e0000 { //global utilities block
545 compatible = "fsl,p1022-guts";
546 reg = <0xe0000 0x1000>;
551 pci0: pcie@fffe09000 {
552 compatible = "fsl,p1022-pcie";
554 #interrupt-cells = <1>;
556 #address-cells = <3>;
557 reg = <0xf 0xffe09000 0 0x1000>;
559 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
560 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
561 clock-frequency = <33333333>;
562 interrupts = <16 2 0 0>;
563 interrupt-map-mask = <0xf800 0 0 7>;
572 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #address-cells = <3>;
576 ranges = <0x2000000 0x0 0xe0000000
577 0x2000000 0x0 0xe0000000
586 pci1: pcie@fffe0a000 {
587 compatible = "fsl,p1022-pcie";
589 #interrupt-cells = <1>;
591 #address-cells = <3>;
592 reg = <0xf 0xffe0a000 0 0x1000>;
594 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
595 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
596 clock-frequency = <33333333>;
597 interrupts = <16 2 0 0>;
598 interrupt-map-mask = <0xf800 0 0 7>;
607 reg = <0x0 0x0 0x0 0x0 0x0>;
609 #address-cells = <3>;
611 ranges = <0x2000000 0x0 0xe0000000
612 0x2000000 0x0 0xe0000000
622 pci2: pcie@fffe0b000 {
623 compatible = "fsl,p1022-pcie";
625 #interrupt-cells = <1>;
627 #address-cells = <3>;
628 reg = <0xf 0xffe0b000 0 0x1000>;
630 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
631 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
632 clock-frequency = <33333333>;
633 interrupts = <16 2 0 0>;
634 interrupt-map-mask = <0xf800 0 0 7>;
639 0000 0 0 3 &mpic 10 1
640 0000 0 0 4 &mpic 11 1
643 reg = <0x0 0x0 0x0 0x0 0x0>;
645 #address-cells = <3>;
647 ranges = <0x2000000 0x0 0xe0000000
648 0x2000000 0x0 0xe0000000