arch/powerpc/boot/dts/p1022ds.dts

   1 /*
   2  * P1022 DS 36Bit Physical Address Map Device Tree Source
   3  *
   4  * Copyright 2010 Freescale Semiconductor, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /dts-v1/;
  12 / {
  13         model = "fsl,P1022";
  14         compatible = "fsl,P1022DS";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&mpic>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,P1022@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         next-level-cache = <&L2>;
  37                 };
  38
  39                 PowerPC,P1022@1 {
  40                         device_type = "cpu";
  41                         reg = <0x1>;
  42                         next-level-cache = <&L2>;
  43                 };
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48         };
  49
  50         localbus@fffe05000 {
  51                 #address-cells = <2>;
  52                 #size-cells = <1>;
  53                 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
  54                 reg = <0 0xffe05000 0 0x1000>;
  55                 interrupts = <19 2>;
  56
  57                 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
  58                           0x1 0x0 0xf 0xe0000000 0x08000000
  59                           0x2 0x0 0x0 0xffa00000 0x00040000
  60                           0x3 0x0 0xf 0xffdf0000 0x00008000>;
  61
  62                 nor@0,0 {
  63                         #address-cells = <1>;
  64                         #size-cells = <1>;
  65                         compatible = "cfi-flash";
  66                         reg = <0x0 0x0 0x8000000>;
  67                         bank-width = <2>;
  68                         device-width = <1>;
  69
  70                         partition@0 {
  71                                 reg = <0x0 0x03000000>;
  72                                 label = "ramdisk-nor";
  73                                 read-only;
  74                         };
  75
  76                         partition@3000000 {
  77                                 reg = <0x03000000 0x00e00000>;
  78                                 label = "diagnostic-nor";
  79                                 read-only;
  80                         };
  81
  82                         partition@3e00000 {
  83                                 reg = <0x03e00000 0x00200000>;
  84                                 label = "dink-nor";
  85                                 read-only;
  86                         };
  87
  88                         partition@4000000 {
  89                                 reg = <0x04000000 0x00400000>;
  90                                 label = "kernel-nor";
  91                                 read-only;
  92                         };
  93
  94                         partition@4400000 {
  95                                 reg = <0x04400000 0x03b00000>;
  96                                 label = "jffs2-nor";
  97                         };
  98
  99                         partition@7f00000 {
 100                                 reg = <0x07f00000 0x00080000>;
 101                                 label = "dtb-nor";
 102                                 read-only;
 103                         };
 104
 105                         partition@7f80000 {
 106                                 reg = <0x07f80000 0x00080000>;
 107                                 label = "u-boot-nor";
 108                                 read-only;
 109                         };
 110                 };
 111
 112                 nand@2,0 {
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115                         compatible = "fsl,elbc-fcm-nand";
 116                         reg = <0x2 0x0 0x40000>;
 117
 118                         partition@0 {
 119                                 reg = <0x0 0x02000000>;
 120                                 label = "u-boot-nand";
 121                                 read-only;
 122                         };
 123
 124                         partition@2000000 {
 125                                 reg = <0x02000000 0x10000000>;
 126                                 label = "jffs2-nand";
 127                         };
 128
 129                         partition@12000000 {
 130                                 reg = <0x12000000 0x10000000>;
 131                                 label = "ramdisk-nand";
 132                                 read-only;
 133                         };
 134
 135                         partition@22000000 {
 136                                 reg = <0x22000000 0x04000000>;
 137                                 label = "kernel-nand";
 138                         };
 139
 140                         partition@26000000 {
 141                                 reg = <0x26000000 0x01000000>;
 142                                 label = "dtb-nand";
 143                                 read-only;
 144                         };
 145
 146                         partition@27000000 {
 147                                 reg = <0x27000000 0x19000000>;
 148                                 label = "reserved-nand";
 149                         };
 150                 };
 151
 152                 board-control@3,0 {
 153                         compatible = "fsl,p1022ds-pixis";
 154                         reg = <3 0 0x30>;
 155                         interrupt-parent = <&mpic>;
 156                         /*
 157                          * IRQ8 is generated if the "EVENT" switch is pressed
 158                          * and PX_CTL[EVESEL] is set to 00.
 159                          */
 160                         interrupts = <8 8>;
 161                 };
 162         };
 163
 164         soc@fffe00000 {
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 device_type = "soc";
 168                 compatible = "fsl,p1022-immr", "simple-bus";
 169                 ranges = <0x0 0xf 0xffe00000 0x100000>;
 170                 bus-frequency = <0>;            // Filled out by uboot.
 171
 172                 ecm-law@0 {
 173                         compatible = "fsl,ecm-law";
 174                         reg = <0x0 0x1000>;
 175                         fsl,num-laws = <12>;
 176                 };
 177
 178                 ecm@1000 {
 179                         compatible = "fsl,p1022-ecm", "fsl,ecm";
 180                         reg = <0x1000 0x1000>;
 181                         interrupts = <16 2>;
 182                 };
 183
 184                 memory-controller@2000 {
 185                         compatible = "fsl,p1022-memory-controller";
 186                         reg = <0x2000 0x1000>;
 187                         interrupts = <16 2>;
 188                 };
 189
 190                 i2c@3000 {
 191                         #address-cells = <1>;
 192                         #size-cells = <0>;
 193                         cell-index = <0>;
 194                         compatible = "fsl-i2c";
 195                         reg = <0x3000 0x100>;
 196                         interrupts = <43 2>;
 197                         dfsrr;
 198                 };
 199
 200                 i2c@3100 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         cell-index = <1>;
 204                         compatible = "fsl-i2c";
 205                         reg = <0x3100 0x100>;
 206                         interrupts = <43 2>;
 207                         dfsrr;
 208
 209                         wm8776:codec@1a {
 210                                 compatible = "wlf,wm8776";
 211                                 reg = <0x1a>;
 212                                 /* MCLK source is a stand-alone oscillator */
 213                                 clock-frequency = <12288000>;
 214                         };
 215                 };
 216
 217                 serial0: serial@4500 {
 218                         cell-index = <0>;
 219                         device_type = "serial";
 220                         compatible = "ns16550";
 221                         reg = <0x4500 0x100>;
 222                         clock-frequency = <0>;
 223                         interrupts = <42 2>;
 224                 };
 225
 226                 serial1: serial@4600 {
 227                         cell-index = <1>;
 228                         device_type = "serial";
 229                         compatible = "ns16550";
 230                         reg = <0x4600 0x100>;
 231                         clock-frequency = <0>;
 232                         interrupts = <42 2>;
 233                 };
 234
 235                 spi@7000 {
 236                         cell-index = <0>;
 237                         #address-cells = <1>;
 238                         #size-cells = <0>;
 239                         compatible = "fsl,espi";
 240                         reg = <0x7000 0x1000>;
 241                         interrupts = <59 0x2>;
 242                         espi,num-ss-bits = <4>;
 243                         mode = "cpu";
 244
 245                         fsl_m25p80@0 {
 246                                 #address-cells = <1>;
 247                                 #size-cells = <1>;
 248                                 compatible = "fsl,espi-flash";
 249                                 reg = <0>;
 250                                 linux,modalias = "fsl_m25p80";
 251                                 spi-max-frequency = <40000000>; /* input clock */
 252                                 partition@0 {
 253                                         label = "u-boot-spi";
 254                                         reg = <0x00000000 0x00100000>;
 255                                         read-only;
 256                                 };
 257                                 partition@100000 {
 258                                         label = "kernel-spi";
 259                                         reg = <0x00100000 0x00500000>;
 260                                         read-only;
 261                                 };
 262                                 partition@600000 {
 263                                         label = "dtb-spi";
 264                                         reg = <0x00600000 0x00100000>;
 265                                         read-only;
 266                                 };
 267                                 partition@700000 {
 268                                         label = "file system-spi";
 269                                         reg = <0x00700000 0x00900000>;
 270                                 };
 271                         };
 272                 };
 273
 274                 ssi@15000 {
 275                         compatible = "fsl,mpc8610-ssi";
 276                         cell-index = <0>;
 277                         reg = <0x15000 0x100>;
 278                         interrupts = <75 2>;
 279                         fsl,mode = "i2s-slave";
 280                         codec-handle = <&wm8776>;
 281                         fsl,playback-dma = <&dma00>;
 282                         fsl,capture-dma = <&dma01>;
 283                         fsl,fifo-depth = <16>;
 284                 };
 285
 286                 dma@c300 {
 287                         #address-cells = <1>;
 288                         #size-cells = <1>;
 289                         compatible = "fsl,eloplus-dma";
 290                         reg = <0xc300 0x4>;
 291                         ranges = <0x0 0xc100 0x200>;
 292                         cell-index = <1>;
 293                         dma00: dma-channel@0 {
 294                                 compatible = "fsl,eloplus-dma-channel";
 295                                 reg = <0x0 0x80>;
 296                                 cell-index = <0>;
 297                                 interrupts = <76 2>;
 298                         };
 299                         dma01: dma-channel@80 {
 300                                 compatible = "fsl,eloplus-dma-channel";
 301                                 reg = <0x80 0x80>;
 302                                 cell-index = <1>;
 303                                 interrupts = <77 2>;
 304                         };
 305                         dma-channel@100 {
 306                                 compatible = "fsl,eloplus-dma-channel";
 307                                 reg = <0x100 0x80>;
 308                                 cell-index = <2>;
 309                                 interrupts = <78 2>;
 310                         };
 311                         dma-channel@180 {
 312                                 compatible = "fsl,eloplus-dma-channel";
 313                                 reg = <0x180 0x80>;
 314                                 cell-index = <3>;
 315                                 interrupts = <79 2>;
 316                         };
 317                 };
 318
 319                 gpio: gpio-controller@f000 {
 320                         #gpio-cells = <2>;
 321                         compatible = "fsl,mpc8572-gpio";
 322                         reg = <0xf000 0x100>;
 323                         interrupts = <47 0x2>;
 324                         gpio-controller;
 325                 };
 326
 327                 L2: l2-cache-controller@20000 {
 328                         compatible = "fsl,p1022-l2-cache-controller";
 329                         reg = <0x20000 0x1000>;
 330                         cache-line-size = <32>; // 32 bytes
 331                         cache-size = <0x40000>; // L2, 256K
 332                         interrupts = <16 2>;
 333                 };
 334
 335                 dma@21300 {
 336                         #address-cells = <1>;
 337                         #size-cells = <1>;
 338                         compatible = "fsl,eloplus-dma";
 339                         reg = <0x21300 0x4>;
 340                         ranges = <0x0 0x21100 0x200>;
 341                         cell-index = <0>;
 342                         dma-channel@0 {
 343                                 compatible = "fsl,eloplus-dma-channel";
 344                                 reg = <0x0 0x80>;
 345                                 cell-index = <0>;
 346                                 interrupts = <20 2>;
 347                         };
 348                         dma-channel@80 {
 349                                 compatible = "fsl,eloplus-dma-channel";
 350                                 reg = <0x80 0x80>;
 351                                 cell-index = <1>;
 352                                 interrupts = <21 2>;
 353                         };
 354                         dma-channel@100 {
 355                                 compatible = "fsl,eloplus-dma-channel";
 356                                 reg = <0x100 0x80>;
 357                                 cell-index = <2>;
 358                                 interrupts = <22 2>;
 359                         };
 360                         dma-channel@180 {
 361                                 compatible = "fsl,eloplus-dma-channel";
 362                                 reg = <0x180 0x80>;
 363                                 cell-index = <3>;
 364                                 interrupts = <23 2>;
 365                         };
 366                 };
 367
 368                 usb@22000 {
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         compatible = "fsl-usb2-dr";
 372                         reg = <0x22000 0x1000>;
 373                         interrupts = <28 0x2>;
 374                         phy_type = "ulpi";
 375                 };
 376
 377                 mdio@24000 {
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         compatible = "fsl,etsec2-mdio";
 381                         reg = <0x24000 0x1000 0xb0030 0x4>;
 382
 383                         phy0: ethernet-phy@0 {
 384                                 interrupts = <3 1>;
 385                                 reg = <0x1>;
 386                         };
 387                         phy1: ethernet-phy@1 {
 388                                 interrupts = <9 1>;
 389                                 reg = <0x2>;
 390                         };
 391                 };
 392
 393                 mdio@25000 {
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         compatible = "fsl,etsec2-mdio";
 397                         reg = <0x25000 0x1000 0xb1030 0x4>;
 398                 };
 399
 400                 enet0: ethernet@B0000 {
 401                         #address-cells = <1>;
 402                         #size-cells = <1>;
 403                         cell-index = <0>;
 404                         device_type = "network";
 405                         model = "eTSEC";
 406                         compatible = "fsl,etsec2";
 407                         fsl,num_rx_queues = <0x8>;
 408                         fsl,num_tx_queues = <0x8>;
 409                         fsl,magic-packet;
 410                         fsl,wake-on-filer;
 411                         local-mac-address = [ 00 00 00 00 00 00 ];
 412                         fixed-link = <1 1 1000 0 0>;
 413                         phy-handle = <&phy0>;
 414                         phy-connection-type = "rgmii-id";
 415                         queue-group@0{
 416                                 #address-cells = <1>;
 417                                 #size-cells = <1>;
 418                                 reg = <0xB0000 0x1000>;
 419                                 interrupts = <29 2 30 2 34 2>;
 420                         };
 421                         queue-group@1{
 422                                 #address-cells = <1>;
 423                                 #size-cells = <1>;
 424                                 reg = <0xB4000 0x1000>;
 425                                 interrupts = <17 2 18 2 24 2>;
 426                         };
 427                 };
 428
 429                 enet1: ethernet@B1000 {
 430                         #address-cells = <1>;
 431                         #size-cells = <1>;
 432                         cell-index = <0>;
 433                         device_type = "network";
 434                         model = "eTSEC";
 435                         compatible = "fsl,etsec2";
 436                         fsl,num_rx_queues = <0x8>;
 437                         fsl,num_tx_queues = <0x8>;
 438                         local-mac-address = [ 00 00 00 00 00 00 ];
 439                         fixed-link = <1 1 1000 0 0>;
 440                         phy-handle = <&phy1>;
 441                         phy-connection-type = "rgmii-id";
 442                         queue-group@0{
 443                                 #address-cells = <1>;
 444                                 #size-cells = <1>;
 445                                 reg = <0xB1000 0x1000>;
 446                                 interrupts = <35 2 36 2 40 2>;
 447                         };
 448                         queue-group@1{
 449                                 #address-cells = <1>;
 450                                 #size-cells = <1>;
 451                                 reg = <0xB5000 0x1000>;
 452                                 interrupts = <51 2 52 2 67 2>;
 453                         };
 454                 };
 455
 456                 sdhci@2e000 {
 457                         compatible = "fsl,p1022-esdhc", "fsl,esdhc";
 458                         reg = <0x2e000 0x1000>;
 459                         interrupts = <72 0x2>;
 460                         fsl,sdhci-auto-cmd12;
 461                         /* Filled in by U-Boot */
 462                         clock-frequency = <0>;
 463                 };
 464
 465                 crypto@30000 {
 466                         compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
 467                                      "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
 468                                      "fsl,sec2.0";
 469                         reg = <0x30000 0x10000>;
 470                         interrupts = <45 2 58 2>;
 471                         fsl,num-channels = <4>;
 472                         fsl,channel-fifo-len = <24>;
 473                         fsl,exec-units-mask = <0x97c>;
 474                         fsl,descriptor-types-mask = <0x3a30abf>;
 475                 };
 476
 477                 sata@18000 {
 478                         compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
 479                         reg = <0x18000 0x1000>;
 480                         cell-index = <1>;
 481                         interrupts = <74 0x2>;
 482                 };
 483
 484                 sata@19000 {
 485                         compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
 486                         reg = <0x19000 0x1000>;
 487                         cell-index = <2>;
 488                         interrupts = <41 0x2>;
 489                 };
 490
 491                 power@e0070{
 492                         compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
 493                         reg = <0xe0070 0x20>;
 494                 };
 495
 496                 display@10000 {
 497                         compatible = "fsl,diu", "fsl,p1022-diu";
 498                         reg = <0x10000 1000>;
 499                         interrupts = <64 2>;
 500                 };
 501
 502                 timer@41100 {
 503                         compatible = "fsl,mpic-global-timer";
 504                         reg = <0x41100 0x204>;
 505                         interrupts = <0xf7 0x2>;
 506                 };
 507
 508                 mpic: pic@40000 {
 509                         interrupt-controller;
 510                         #address-cells = <0>;
 511                         #interrupt-cells = <2>;
 512                         reg = <0x40000 0x40000>;
 513                         compatible = "chrp,open-pic";
 514                         device_type = "open-pic";
 515                 };
 516
 517                 msi@41600 {
 518                         compatible = "fsl,p1022-msi", "fsl,mpic-msi";
 519                         reg = <0x41600 0x80>;
 520                         msi-available-ranges = <0 0x100>;
 521                         interrupts = <
 522                                 0xe0 0
 523                                 0xe1 0
 524                                 0xe2 0
 525                                 0xe3 0
 526                                 0xe4 0
 527                                 0xe5 0
 528                                 0xe6 0
 529                                 0xe7 0>;
 530                 };
 531
 532                 global-utilities@e0000 {        //global utilities block
 533                         compatible = "fsl,p1022-guts";
 534                         reg = <0xe0000 0x1000>;
 535                         fsl,has-rstcr;
 536                 };
 537         };
 538
 539         pci0: pcie@fffe09000 {
 540                 compatible = "fsl,p1022-pcie";
 541                 device_type = "pci";
 542                 #interrupt-cells = <1>;
 543                 #size-cells = <2>;
 544                 #address-cells = <3>;
 545                 reg = <0xf 0xffe09000 0 0x1000>;
 546                 bus-range = <0 255>;
 547                 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
 548                           0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
 549                 clock-frequency = <33333333>;
 550                 interrupts = <16 2>;
 551                 interrupt-map-mask = <0xf800 0 0 7>;
 552                 interrupt-map = <
 553                         /* IDSEL 0x0 */
 554                         0000 0 0 1 &mpic 4 1
 555                         0000 0 0 2 &mpic 5 1
 556                         0000 0 0 3 &mpic 6 1
 557                         0000 0 0 4 &mpic 7 1
 558                         >;
 559                 pcie@0 {
 560                         reg = <0x0 0x0 0x0 0x0 0x0>;
 561                         #size-cells = <2>;
 562                         #address-cells = <3>;
 563                         device_type = "pci";
 564                         ranges = <0x2000000 0x0 0xe0000000
 565                                   0x2000000 0x0 0xe0000000
 566                                   0x0 0x20000000
 567
 568                                   0x1000000 0x0 0x0
 569                                   0x1000000 0x0 0x0
 570                                   0x0 0x100000>;
 571                 };
 572         };
 573
 574         pci1: pcie@fffe0a000 {
 575                 compatible = "fsl,p1022-pcie";
 576                 device_type = "pci";
 577                 #interrupt-cells = <1>;
 578                 #size-cells = <2>;
 579                 #address-cells = <3>;
 580                 reg = <0xf 0xffe0a000 0 0x1000>;
 581                 bus-range = <0 255>;
 582                 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
 583                           0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
 584                 clock-frequency = <33333333>;
 585                 interrupts = <16 2>;
 586                 interrupt-map-mask = <0xf800 0 0 7>;
 587                 interrupt-map = <
 588                         /* IDSEL 0x0 */
 589                         0000 0 0 1 &mpic 0 1
 590                         0000 0 0 2 &mpic 1 1
 591                         0000 0 0 3 &mpic 2 1
 592                         0000 0 0 4 &mpic 3 1
 593                         >;
 594                 pcie@0 {
 595                         reg = <0x0 0x0 0x0 0x0 0x0>;
 596                         #size-cells = <2>;
 597                         #address-cells = <3>;
 598                         device_type = "pci";
 599                         ranges = <0x2000000 0x0 0xe0000000
 600                                   0x2000000 0x0 0xe0000000
 601                                   0x0 0x20000000
 602
 603                                   0x1000000 0x0 0x0
 604                                   0x1000000 0x0 0x0
 605                                   0x0 0x100000>;
 606                 };
 607         };
 608
 609
 610         pci2: pcie@fffe0b000 {
 611                 compatible = "fsl,p1022-pcie";
 612                 device_type = "pci";
 613                 #interrupt-cells = <1>;
 614                 #size-cells = <2>;
 615                 #address-cells = <3>;
 616                 reg = <0xf 0xffe0b000 0 0x1000>;
 617                 bus-range = <0 255>;
 618                 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
 619                           0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
 620                 clock-frequency = <33333333>;
 621                 interrupts = <16 2>;
 622                 interrupt-map-mask = <0xf800 0 0 7>;
 623                 interrupt-map = <
 624                         /* IDSEL 0x0 */
 625                         0000 0 0 1 &mpic 8 1
 626                         0000 0 0 2 &mpic 9 1
 627                         0000 0 0 3 &mpic 10 1
 628                         0000 0 0 4 &mpic 11 1
 629                         >;
 630                 pcie@0 {
 631                         reg = <0x0 0x0 0x0 0x0 0x0>;
 632                         #size-cells = <2>;
 633                         #address-cells = <3>;
 634                         device_type = "pci";
 635                         ranges = <0x2000000 0x0 0xe0000000
 636                                   0x2000000 0x0 0xe0000000
 637                                   0x0 0x20000000
 638
 639                                   0x1000000 0x0 0x0
 640                                   0x1000000 0x0 0x0
 641                                   0x0 0x100000>;
 642                 };
 643         };
 644 };