arch/powerpc/boot/dts/p1022ds.dts

   1 /*
   2  * P1022 DS 36Bit Physical Address Map Device Tree Source
   3  *
   4  * Copyright 2010 Freescale Semiconductor, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /dts-v1/;
  12 / {
  13         model = "fsl,P1022";
  14         compatible = "fsl,P1022DS";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&mpic>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,P1022@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         next-level-cache = <&L2>;
  37                 };
  38
  39                 PowerPC,P1022@1 {
  40                         device_type = "cpu";
  41                         reg = <0x1>;
  42                         next-level-cache = <&L2>;
  43                 };
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48         };
  49
  50         localbus@fffe05000 {
  51                 #address-cells = <2>;
  52                 #size-cells = <1>;
  53                 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
  54                 reg = <0 0xffe05000 0 0x1000>;
  55                 interrupts = <19 2 0 0>;
  56
  57                 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
  58                           0x1 0x0 0xf 0xe0000000 0x08000000
  59                           0x2 0x0 0x0 0xffa00000 0x00040000
  60                           0x3 0x0 0xf 0xffdf0000 0x00008000>;
  61
  62                 nor@0,0 {
  63                         #address-cells = <1>;
  64                         #size-cells = <1>;
  65                         compatible = "cfi-flash";
  66                         reg = <0x0 0x0 0x8000000>;
  67                         bank-width = <2>;
  68                         device-width = <1>;
  69
  70                         partition@0 {
  71                                 reg = <0x0 0x03000000>;
  72                                 label = "ramdisk-nor";
  73                                 read-only;
  74                         };
  75
  76                         partition@3000000 {
  77                                 reg = <0x03000000 0x00e00000>;
  78                                 label = "diagnostic-nor";
  79                                 read-only;
  80                         };
  81
  82                         partition@3e00000 {
  83                                 reg = <0x03e00000 0x00200000>;
  84                                 label = "dink-nor";
  85                                 read-only;
  86                         };
  87
  88                         partition@4000000 {
  89                                 reg = <0x04000000 0x00400000>;
  90                                 label = "kernel-nor";
  91                                 read-only;
  92                         };
  93
  94                         partition@4400000 {
  95                                 reg = <0x04400000 0x03b00000>;
  96                                 label = "jffs2-nor";
  97                         };
  98
  99                         partition@7f00000 {
 100                                 reg = <0x07f00000 0x00080000>;
 101                                 label = "dtb-nor";
 102                                 read-only;
 103                         };
 104
 105                         partition@7f80000 {
 106                                 reg = <0x07f80000 0x00080000>;
 107                                 label = "u-boot-nor";
 108                                 read-only;
 109                         };
 110                 };
 111
 112                 nand@2,0 {
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115                         compatible = "fsl,elbc-fcm-nand";
 116                         reg = <0x2 0x0 0x40000>;
 117
 118                         partition@0 {
 119                                 reg = <0x0 0x02000000>;
 120                                 label = "u-boot-nand";
 121                                 read-only;
 122                         };
 123
 124                         partition@2000000 {
 125                                 reg = <0x02000000 0x10000000>;
 126                                 label = "jffs2-nand";
 127                         };
 128
 129                         partition@12000000 {
 130                                 reg = <0x12000000 0x10000000>;
 131                                 label = "ramdisk-nand";
 132                                 read-only;
 133                         };
 134
 135                         partition@22000000 {
 136                                 reg = <0x22000000 0x04000000>;
 137                                 label = "kernel-nand";
 138                         };
 139
 140                         partition@26000000 {
 141                                 reg = <0x26000000 0x01000000>;
 142                                 label = "dtb-nand";
 143                                 read-only;
 144                         };
 145
 146                         partition@27000000 {
 147                                 reg = <0x27000000 0x19000000>;
 148                                 label = "reserved-nand";
 149                         };
 150                 };
 151
 152                 board-control@3,0 {
 153                         compatible = "fsl,p1022ds-pixis";
 154                         reg = <3 0 0x30>;
 155                         interrupt-parent = <&mpic>;
 156                         /*
 157                          * IRQ8 is generated if the "EVENT" switch is pressed
 158                          * and PX_CTL[EVESEL] is set to 00.
 159                          */
 160                         interrupts = <8 8 0 0>;
 161                 };
 162         };
 163
 164         soc@fffe00000 {
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 device_type = "soc";
 168                 compatible = "fsl,p1022-immr", "simple-bus";
 169                 ranges = <0x0 0xf 0xffe00000 0x100000>;
 170                 bus-frequency = <0>;            // Filled out by uboot.
 171
 172                 ecm-law@0 {
 173                         compatible = "fsl,ecm-law";
 174                         reg = <0x0 0x1000>;
 175                         fsl,num-laws = <12>;
 176                 };
 177
 178                 ecm@1000 {
 179                         compatible = "fsl,p1022-ecm", "fsl,ecm";
 180                         reg = <0x1000 0x1000>;
 181                         interrupts = <16 2 0 0>;
 182                 };
 183
 184                 memory-controller@2000 {
 185                         compatible = "fsl,p1022-memory-controller";
 186                         reg = <0x2000 0x1000>;
 187                         interrupts = <16 2 0 0>;
 188                 };
 189
 190                 i2c@3000 {
 191                         #address-cells = <1>;
 192                         #size-cells = <0>;
 193                         cell-index = <0>;
 194                         compatible = "fsl-i2c";
 195                         reg = <0x3000 0x100>;
 196                         interrupts = <43 2 0 0>;
 197                         dfsrr;
 198                 };
 199
 200                 i2c@3100 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         cell-index = <1>;
 204                         compatible = "fsl-i2c";
 205                         reg = <0x3100 0x100>;
 206                         interrupts = <43 2 0 0>;
 207                         dfsrr;
 208
 209                         wm8776:codec@1a {
 210                                 compatible = "wlf,wm8776";
 211                                 reg = <0x1a>;
 212                                 /*
 213                                  * clock-frequency will be set by U-Boot if
 214                                  * the clock is enabled.
 215                                  */
 216                         };
 217                 };
 218
 219                 serial0: serial@4500 {
 220                         cell-index = <0>;
 221                         device_type = "serial";
 222                         compatible = "ns16550";
 223                         reg = <0x4500 0x100>;
 224                         clock-frequency = <0>;
 225                         interrupts = <42 2 0 0>;
 226                 };
 227
 228                 serial1: serial@4600 {
 229                         cell-index = <1>;
 230                         device_type = "serial";
 231                         compatible = "ns16550";
 232                         reg = <0x4600 0x100>;
 233                         clock-frequency = <0>;
 234                         interrupts = <42 2 0 0>;
 235                 };
 236
 237                 spi@7000 {
 238                         cell-index = <0>;
 239                         #address-cells = <1>;
 240                         #size-cells = <0>;
 241                         compatible = "fsl,espi";
 242                         reg = <0x7000 0x1000>;
 243                         interrupts = <59 0x2 0 0>;
 244                         espi,num-ss-bits = <4>;
 245                         mode = "cpu";
 246
 247                         fsl_m25p80@0 {
 248                                 #address-cells = <1>;
 249                                 #size-cells = <1>;
 250                                 compatible = "fsl,espi-flash";
 251                                 reg = <0>;
 252                                 linux,modalias = "fsl_m25p80";
 253                                 spi-max-frequency = <40000000>; /* input clock */
 254                                 partition@0 {
 255                                         label = "u-boot-spi";
 256                                         reg = <0x00000000 0x00100000>;
 257                                         read-only;
 258                                 };
 259                                 partition@100000 {
 260                                         label = "kernel-spi";
 261                                         reg = <0x00100000 0x00500000>;
 262                                         read-only;
 263                                 };
 264                                 partition@600000 {
 265                                         label = "dtb-spi";
 266                                         reg = <0x00600000 0x00100000>;
 267                                         read-only;
 268                                 };
 269                                 partition@700000 {
 270                                         label = "file system-spi";
 271                                         reg = <0x00700000 0x00900000>;
 272                                 };
 273                         };
 274                 };
 275
 276                 ssi@15000 {
 277                         compatible = "fsl,mpc8610-ssi";
 278                         cell-index = <0>;
 279                         reg = <0x15000 0x100>;
 280                         interrupts = <75 2 0 0>;
 281                         fsl,mode = "i2s-slave";
 282                         codec-handle = <&wm8776>;
 283                         fsl,playback-dma = <&dma00>;
 284                         fsl,capture-dma = <&dma01>;
 285                         fsl,fifo-depth = <15>;
 286                         fsl,ssi-asynchronous;
 287                 };
 288
 289                 dma@c300 {
 290                         #address-cells = <1>;
 291                         #size-cells = <1>;
 292                         compatible = "fsl,eloplus-dma";
 293                         reg = <0xc300 0x4>;
 294                         ranges = <0x0 0xc100 0x200>;
 295                         cell-index = <1>;
 296                         dma00: dma-channel@0 {
 297                                 compatible = "fsl,ssi-dma-channel";
 298                                 reg = <0x0 0x80>;
 299                                 cell-index = <0>;
 300                                 interrupts = <76 2 0 0>;
 301                         };
 302                         dma01: dma-channel@80 {
 303                                 compatible = "fsl,ssi-dma-channel";
 304                                 reg = <0x80 0x80>;
 305                                 cell-index = <1>;
 306                                 interrupts = <77 2 0 0>;
 307                         };
 308                         dma-channel@100 {
 309                                 compatible = "fsl,eloplus-dma-channel";
 310                                 reg = <0x100 0x80>;
 311                                 cell-index = <2>;
 312                                 interrupts = <78 2 0 0>;
 313                         };
 314                         dma-channel@180 {
 315                                 compatible = "fsl,eloplus-dma-channel";
 316                                 reg = <0x180 0x80>;
 317                                 cell-index = <3>;
 318                                 interrupts = <79 2 0 0>;
 319                         };
 320                 };
 321
 322                 gpio: gpio-controller@f000 {
 323                         #gpio-cells = <2>;
 324                         compatible = "fsl,mpc8572-gpio";
 325                         reg = <0xf000 0x100>;
 326                         interrupts = <47 0x2 0 0>;
 327                         gpio-controller;
 328                 };
 329
 330                 L2: l2-cache-controller@20000 {
 331                         compatible = "fsl,p1022-l2-cache-controller";
 332                         reg = <0x20000 0x1000>;
 333                         cache-line-size = <32>; // 32 bytes
 334                         cache-size = <0x40000>; // L2, 256K
 335                         interrupts = <16 2 0 0>;
 336                 };
 337
 338                 dma@21300 {
 339                         #address-cells = <1>;
 340                         #size-cells = <1>;
 341                         compatible = "fsl,eloplus-dma";
 342                         reg = <0x21300 0x4>;
 343                         ranges = <0x0 0x21100 0x200>;
 344                         cell-index = <0>;
 345                         dma-channel@0 {
 346                                 compatible = "fsl,eloplus-dma-channel";
 347                                 reg = <0x0 0x80>;
 348                                 cell-index = <0>;
 349                                 interrupts = <20 2 0 0>;
 350                         };
 351                         dma-channel@80 {
 352                                 compatible = "fsl,eloplus-dma-channel";
 353                                 reg = <0x80 0x80>;
 354                                 cell-index = <1>;
 355                                 interrupts = <21 2 0 0>;
 356                         };
 357                         dma-channel@100 {
 358                                 compatible = "fsl,eloplus-dma-channel";
 359                                 reg = <0x100 0x80>;
 360                                 cell-index = <2>;
 361                                 interrupts = <22 2 0 0>;
 362                         };
 363                         dma-channel@180 {
 364                                 compatible = "fsl,eloplus-dma-channel";
 365                                 reg = <0x180 0x80>;
 366                                 cell-index = <3>;
 367                                 interrupts = <23 2 0 0>;
 368                         };
 369                 };
 370
 371                 usb@22000 {
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         compatible = "fsl-usb2-dr";
 375                         reg = <0x22000 0x1000>;
 376                         interrupts = <28 0x2 0 0>;
 377                         phy_type = "ulpi";
 378                 };
 379
 380                 mdio@24000 {
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         compatible = "fsl,etsec2-mdio";
 384                         reg = <0x24000 0x1000 0xb0030 0x4>;
 385
 386                         phy0: ethernet-phy@0 {
 387                                 interrupts = <3 1 0 0>;
 388                                 reg = <0x1>;
 389                         };
 390                         phy1: ethernet-phy@1 {
 391                                 interrupts = <9 1 0 0>;
 392                                 reg = <0x2>;
 393                         };
 394                 };
 395
 396                 mdio@25000 {
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         compatible = "fsl,etsec2-mdio";
 400                         reg = <0x25000 0x1000 0xb1030 0x4>;
 401                 };
 402
 403                 enet0: ethernet@B0000 {
 404                         #address-cells = <1>;
 405                         #size-cells = <1>;
 406                         cell-index = <0>;
 407                         device_type = "network";
 408                         model = "eTSEC";
 409                         compatible = "fsl,etsec2";
 410                         fsl,num_rx_queues = <0x8>;
 411                         fsl,num_tx_queues = <0x8>;
 412                         fsl,magic-packet;
 413                         fsl,wake-on-filer;
 414                         local-mac-address = [ 00 00 00 00 00 00 ];
 415                         phy-handle = <&phy0>;
 416                         phy-connection-type = "rgmii-id";
 417                         queue-group@0{
 418                                 #address-cells = <1>;
 419                                 #size-cells = <1>;
 420                                 reg = <0xB0000 0x1000>;
 421                                 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
 422                         };
 423                         queue-group@1{
 424                                 #address-cells = <1>;
 425                                 #size-cells = <1>;
 426                                 reg = <0xB4000 0x1000>;
 427                                 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
 428                         };
 429                 };
 430
 431                 enet1: ethernet@B1000 {
 432                         #address-cells = <1>;
 433                         #size-cells = <1>;
 434                         cell-index = <0>;
 435                         device_type = "network";
 436                         model = "eTSEC";
 437                         compatible = "fsl,etsec2";
 438                         fsl,num_rx_queues = <0x8>;
 439                         fsl,num_tx_queues = <0x8>;
 440                         local-mac-address = [ 00 00 00 00 00 00 ];
 441                         phy-handle = <&phy1>;
 442                         phy-connection-type = "rgmii-id";
 443                         queue-group@0{
 444                                 #address-cells = <1>;
 445                                 #size-cells = <1>;
 446                                 reg = <0xB1000 0x1000>;
 447                                 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
 448                         };
 449                         queue-group@1{
 450                                 #address-cells = <1>;
 451                                 #size-cells = <1>;
 452                                 reg = <0xB5000 0x1000>;
 453                                 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
 454                         };
 455                 };
 456
 457                 sdhci@2e000 {
 458                         compatible = "fsl,p1022-esdhc", "fsl,esdhc";
 459                         reg = <0x2e000 0x1000>;
 460                         interrupts = <72 0x2 0 0>;
 461                         fsl,sdhci-auto-cmd12;
 462                         /* Filled in by U-Boot */
 463                         clock-frequency = <0>;
 464                 };
 465
 466                 crypto@30000 {
 467                         compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
 468                                      "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
 469                                      "fsl,sec2.0";
 470                         reg = <0x30000 0x10000>;
 471                         interrupts = <45 2 0 0 58 2 0 0>;
 472                         fsl,num-channels = <4>;
 473                         fsl,channel-fifo-len = <24>;
 474                         fsl,exec-units-mask = <0x97c>;
 475                         fsl,descriptor-types-mask = <0x3a30abf>;
 476                 };
 477
 478                 sata@18000 {
 479                         compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
 480                         reg = <0x18000 0x1000>;
 481                         cell-index = <1>;
 482                         interrupts = <74 0x2 0 0>;
 483                 };
 484
 485                 sata@19000 {
 486                         compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
 487                         reg = <0x19000 0x1000>;
 488                         cell-index = <2>;
 489                         interrupts = <41 0x2 0 0>;
 490                 };
 491
 492                 power@e0070{
 493                         compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
 494                         reg = <0xe0070 0x20>;
 495                 };
 496
 497                 display@10000 {
 498                         compatible = "fsl,diu", "fsl,p1022-diu";
 499                         reg = <0x10000 1000>;
 500                         interrupts = <64 2 0 0>;
 501                 };
 502
 503                 timer@41100 {
 504                         compatible = "fsl,mpic-global-timer";
 505                         reg = <0x41100 0x100 0x41300 4>;
 506                         interrupts = <0 0 3 0
 507                                       1 0 3 0
 508                                       2 0 3 0
 509                                       3 0 3 0>;
 510                 };
 511
 512                 timer@42100 {
 513                         compatible = "fsl,mpic-global-timer";
 514                         reg = <0x42100 0x100 0x42300 4>;
 515                         interrupts = <4 0 3 0
 516                                       5 0 3 0
 517                                       6 0 3 0
 518                                       7 0 3 0>;
 519                 };
 520
 521                 mpic: pic@40000 {
 522                         interrupt-controller;
 523                         #address-cells = <0>;
 524                         #interrupt-cells = <4>;
 525                         reg = <0x40000 0x40000>;
 526                         compatible = "fsl,mpic";
 527                         device_type = "open-pic";
 528                 };
 529
 530                 msi@41600 {
 531                         compatible = "fsl,p1022-msi", "fsl,mpic-msi";
 532                         reg = <0x41600 0x80>;
 533                         msi-available-ranges = <0 0x100>;
 534                         interrupts = <
 535                                 0xe0 0 0 0
 536                                 0xe1 0 0 0
 537                                 0xe2 0 0 0
 538                                 0xe3 0 0 0
 539                                 0xe4 0 0 0
 540                                 0xe5 0 0 0
 541                                 0xe6 0 0 0
 542                                 0xe7 0 0 0>;
 543                 };
 544
 545                 global-utilities@e0000 {        //global utilities block
 546                         compatible = "fsl,p1022-guts";
 547                         reg = <0xe0000 0x1000>;
 548                         fsl,has-rstcr;
 549                 };
 550         };
 551
 552         pci0: pcie@fffe09000 {
 553                 compatible = "fsl,p1022-pcie";
 554                 device_type = "pci";
 555                 #interrupt-cells = <1>;
 556                 #size-cells = <2>;
 557                 #address-cells = <3>;
 558                 reg = <0xf 0xffe09000 0 0x1000>;
 559                 bus-range = <0 255>;
 560                 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
 561                           0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
 562                 clock-frequency = <33333333>;
 563                 interrupts = <16 2 0 0>;
 564                 interrupt-map-mask = <0xf800 0 0 7>;
 565                 interrupt-map = <
 566                         /* IDSEL 0x0 */
 567                         0000 0 0 1 &mpic 4 1
 568                         0000 0 0 2 &mpic 5 1
 569                         0000 0 0 3 &mpic 6 1
 570                         0000 0 0 4 &mpic 7 1
 571                         >;
 572                 pcie@0 {
 573                         reg = <0x0 0x0 0x0 0x0 0x0>;
 574                         #size-cells = <2>;
 575                         #address-cells = <3>;
 576                         device_type = "pci";
 577                         ranges = <0x2000000 0x0 0xe0000000
 578                                   0x2000000 0x0 0xe0000000
 579                                   0x0 0x20000000
 580
 581                                   0x1000000 0x0 0x0
 582                                   0x1000000 0x0 0x0
 583                                   0x0 0x100000>;
 584                 };
 585         };
 586
 587         pci1: pcie@fffe0a000 {
 588                 compatible = "fsl,p1022-pcie";
 589                 device_type = "pci";
 590                 #interrupt-cells = <1>;
 591                 #size-cells = <2>;
 592                 #address-cells = <3>;
 593                 reg = <0xf 0xffe0a000 0 0x1000>;
 594                 bus-range = <0 255>;
 595                 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
 596                           0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
 597                 clock-frequency = <33333333>;
 598                 interrupts = <16 2 0 0>;
 599                 interrupt-map-mask = <0xf800 0 0 7>;
 600                 interrupt-map = <
 601                         /* IDSEL 0x0 */
 602                         0000 0 0 1 &mpic 0 1
 603                         0000 0 0 2 &mpic 1 1
 604                         0000 0 0 3 &mpic 2 1
 605                         0000 0 0 4 &mpic 3 1
 606                         >;
 607                 pcie@0 {
 608                         reg = <0x0 0x0 0x0 0x0 0x0>;
 609                         #size-cells = <2>;
 610                         #address-cells = <3>;
 611                         device_type = "pci";
 612                         ranges = <0x2000000 0x0 0xe0000000
 613                                   0x2000000 0x0 0xe0000000
 614                                   0x0 0x20000000
 615
 616                                   0x1000000 0x0 0x0
 617                                   0x1000000 0x0 0x0
 618                                   0x0 0x100000>;
 619                 };
 620         };
 621
 622
 623         pci2: pcie@fffe0b000 {
 624                 compatible = "fsl,p1022-pcie";
 625                 device_type = "pci";
 626                 #interrupt-cells = <1>;
 627                 #size-cells = <2>;
 628                 #address-cells = <3>;
 629                 reg = <0xf 0xffe0b000 0 0x1000>;
 630                 bus-range = <0 255>;
 631                 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
 632                           0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
 633                 clock-frequency = <33333333>;
 634                 interrupts = <16 2 0 0>;
 635                 interrupt-map-mask = <0xf800 0 0 7>;
 636                 interrupt-map = <
 637                         /* IDSEL 0x0 */
 638                         0000 0 0 1 &mpic 8 1
 639                         0000 0 0 2 &mpic 9 1
 640                         0000 0 0 3 &mpic 10 1
 641                         0000 0 0 4 &mpic 11 1
 642                         >;
 643                 pcie@0 {
 644                         reg = <0x0 0x0 0x0 0x0 0x0>;
 645                         #size-cells = <2>;
 646                         #address-cells = <3>;
 647                         device_type = "pci";
 648                         ranges = <0x2000000 0x0 0xe0000000
 649                                   0x2000000 0x0 0xe0000000
 650                                   0x0 0x20000000
 651
 652                                   0x1000000 0x0 0x0
 653                                   0x1000000 0x0 0x0
 654                                   0x0 0x100000>;
 655                 };
 656         };
 657 };