arch/powerpc/boot/dts/p1020si.dtsi

   1 /*
   2  * P1020si Device Tree Source
   3  *
   4  * Copyright 2011 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         compatible = "fsl,P1020";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 PowerPC,P1020@0 {
  23                         device_type = "cpu";
  24                         reg = <0x0>;
  25                         next-level-cache = <&L2>;
  26                 };
  27
  28                 PowerPC,P1020@1 {
  29                         device_type = "cpu";
  30                         reg = <0x1>;
  31                         next-level-cache = <&L2>;
  32                 };
  33         };
  34
  35         localbus@ffe05000 {
  36                 #address-cells = <2>;
  37                 #size-cells = <1>;
  38                 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
  39                 reg = <0 0xffe05000 0 0x1000>;
  40                 interrupts = <19 2>;
  41                 interrupt-parent = <&mpic>;
  42         };
  43
  44         soc@ffe00000 {
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 device_type = "soc";
  48                 compatible = "fsl,p1020-immr", "simple-bus";
  49                 ranges = <0x0  0x0 0xffe00000 0x100000>;
  50                 bus-frequency = <0>;            // Filled out by uboot.
  51
  52                 ecm-law@0 {
  53                         compatible = "fsl,ecm-law";
  54                         reg = <0x0 0x1000>;
  55                         fsl,num-laws = <12>;
  56                 };
  57
  58                 ecm@1000 {
  59                         compatible = "fsl,p1020-ecm", "fsl,ecm";
  60                         reg = <0x1000 0x1000>;
  61                         interrupts = <16 2>;
  62                         interrupt-parent = <&mpic>;
  63                 };
  64
  65                 memory-controller@2000 {
  66                         compatible = "fsl,p1020-memory-controller";
  67                         reg = <0x2000 0x1000>;
  68                         interrupt-parent = <&mpic>;
  69                         interrupts = <16 2>;
  70                 };
  71
  72                 i2c@3000 {
  73                         #address-cells = <1>;
  74                         #size-cells = <0>;
  75                         cell-index = <0>;
  76                         compatible = "fsl-i2c";
  77                         reg = <0x3000 0x100>;
  78                         interrupts = <43 2>;
  79                         interrupt-parent = <&mpic>;
  80                         dfsrr;
  81                 };
  82
  83                 i2c@3100 {
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                         cell-index = <1>;
  87                         compatible = "fsl-i2c";
  88                         reg = <0x3100 0x100>;
  89                         interrupts = <43 2>;
  90                         interrupt-parent = <&mpic>;
  91                         dfsrr;
  92                 };
  93
  94                 serial0: serial@4500 {
  95                         cell-index = <0>;
  96                         device_type = "serial";
  97                         compatible = "ns16550";
  98                         reg = <0x4500 0x100>;
  99                         clock-frequency = <0>;
 100                         interrupts = <42 2>;
 101                         interrupt-parent = <&mpic>;
 102                 };
 103
 104                 serial1: serial@4600 {
 105                         cell-index = <1>;
 106                         device_type = "serial";
 107                         compatible = "ns16550";
 108                         reg = <0x4600 0x100>;
 109                         clock-frequency = <0>;
 110                         interrupts = <42 2>;
 111                         interrupt-parent = <&mpic>;
 112                 };
 113
 114                 spi@7000 {
 115                         cell-index = <0>;
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118                         compatible = "fsl,espi";
 119                         reg = <0x7000 0x1000>;
 120                         interrupts = <59 0x2>;
 121                         interrupt-parent = <&mpic>;
 122                         mode = "cpu";
 123                 };
 124
 125                 gpio: gpio-controller@f000 {
 126                         #gpio-cells = <2>;
 127                         compatible = "fsl,mpc8572-gpio";
 128                         reg = <0xf000 0x100>;
 129                         interrupts = <47 0x2>;
 130                         interrupt-parent = <&mpic>;
 131                         gpio-controller;
 132                 };
 133
 134                 L2: l2-cache-controller@20000 {
 135                         compatible = "fsl,p1020-l2-cache-controller";
 136                         reg = <0x20000 0x1000>;
 137                         cache-line-size = <32>; // 32 bytes
 138                         cache-size = <0x40000>; // L2,256K
 139                         interrupt-parent = <&mpic>;
 140                         interrupts = <16 2>;
 141                 };
 142
 143                 dma@21300 {
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146                         compatible = "fsl,eloplus-dma";
 147                         reg = <0x21300 0x4>;
 148                         ranges = <0x0 0x21100 0x200>;
 149                         cell-index = <0>;
 150                         dma-channel@0 {
 151                                 compatible = "fsl,eloplus-dma-channel";
 152                                 reg = <0x0 0x80>;
 153                                 cell-index = <0>;
 154                                 interrupt-parent = <&mpic>;
 155                                 interrupts = <20 2>;
 156                         };
 157                         dma-channel@80 {
 158                                 compatible = "fsl,eloplus-dma-channel";
 159                                 reg = <0x80 0x80>;
 160                                 cell-index = <1>;
 161                                 interrupt-parent = <&mpic>;
 162                                 interrupts = <21 2>;
 163                         };
 164                         dma-channel@100 {
 165                                 compatible = "fsl,eloplus-dma-channel";
 166                                 reg = <0x100 0x80>;
 167                                 cell-index = <2>;
 168                                 interrupt-parent = <&mpic>;
 169                                 interrupts = <22 2>;
 170                         };
 171                         dma-channel@180 {
 172                                 compatible = "fsl,eloplus-dma-channel";
 173                                 reg = <0x180 0x80>;
 174                                 cell-index = <3>;
 175                                 interrupt-parent = <&mpic>;
 176                                 interrupts = <23 2>;
 177                         };
 178                 };
 179
 180                 mdio@24000 {
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         compatible = "fsl,etsec2-mdio";
 184                         reg = <0x24000 0x1000 0xb0030 0x4>;
 185
 186                 };
 187
 188                 mdio@25000 {
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         compatible = "fsl,etsec2-tbi";
 192                         reg = <0x25000 0x1000 0xb1030 0x4>;
 193
 194                 };
 195
 196                 enet0: ethernet@b0000 {
 197                         #address-cells = <1>;
 198                         #size-cells = <1>;
 199                         device_type = "network";
 200                         model = "eTSEC";
 201                         compatible = "fsl,etsec2";
 202                         fsl,num_rx_queues = <0x8>;
 203                         fsl,num_tx_queues = <0x8>;
 204                         local-mac-address = [ 00 00 00 00 00 00 ];
 205                         interrupt-parent = <&mpic>;
 206
 207                         queue-group@0 {
 208                                 #address-cells = <1>;
 209                                 #size-cells = <1>;
 210                                 reg = <0xb0000 0x1000>;
 211                                 interrupts = <29 2 30 2 34 2>;
 212                         };
 213
 214                         queue-group@1 {
 215                                 #address-cells = <1>;
 216                                 #size-cells = <1>;
 217                                 reg = <0xb4000 0x1000>;
 218                                 interrupts = <17 2 18 2 24 2>;
 219                         };
 220                 };
 221
 222                 enet1: ethernet@b1000 {
 223                         #address-cells = <1>;
 224                         #size-cells = <1>;
 225                         device_type = "network";
 226                         model = "eTSEC";
 227                         compatible = "fsl,etsec2";
 228                         fsl,num_rx_queues = <0x8>;
 229                         fsl,num_tx_queues = <0x8>;
 230                         local-mac-address = [ 00 00 00 00 00 00 ];
 231                         interrupt-parent = <&mpic>;
 232
 233                         queue-group@0 {
 234                                 #address-cells = <1>;
 235                                 #size-cells = <1>;
 236                                 reg = <0xb1000 0x1000>;
 237                                 interrupts = <35 2 36 2 40 2>;
 238                         };
 239
 240                         queue-group@1 {
 241                                 #address-cells = <1>;
 242                                 #size-cells = <1>;
 243                                 reg = <0xb5000 0x1000>;
 244                                 interrupts = <51 2 52 2 67 2>;
 245                         };
 246                 };
 247
 248                 enet2: ethernet@b2000 {
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251                         device_type = "network";
 252                         model = "eTSEC";
 253                         compatible = "fsl,etsec2";
 254                         fsl,num_rx_queues = <0x8>;
 255                         fsl,num_tx_queues = <0x8>;
 256                         local-mac-address = [ 00 00 00 00 00 00 ];
 257                         interrupt-parent = <&mpic>;
 258
 259                         queue-group@0 {
 260                                 #address-cells = <1>;
 261                                 #size-cells = <1>;
 262                                 reg = <0xb2000 0x1000>;
 263                                 interrupts = <31 2 32 2 33 2>;
 264                         };
 265
 266                         queue-group@1 {
 267                                 #address-cells = <1>;
 268                                 #size-cells = <1>;
 269                                 reg = <0xb6000 0x1000>;
 270                                 interrupts = <25 2 26 2 27 2>;
 271                         };
 272                 };
 273
 274                 usb@22000 {
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                         compatible = "fsl-usb2-dr";
 278                         reg = <0x22000 0x1000>;
 279                         interrupt-parent = <&mpic>;
 280                         interrupts = <28 0x2>;
 281                 };
 282
 283                 /* USB2 is shared with localbus, so it must be disabled
 284                    by default. We can't put 'status = "disabled";' here
 285                    since U-Boot doesn't clear the status property when
 286                    it enables USB2. OTOH, U-Boot does create a new node
 287                    when there isn't any. So, just comment it out.
 288                 usb@23000 {
 289                         #address-cells = <1>;
 290                         #size-cells = <0>;
 291                         compatible = "fsl-usb2-dr";
 292                         reg = <0x23000 0x1000>;
 293                         interrupt-parent = <&mpic>;
 294                         interrupts = <46 0x2>;
 295                         phy_type = "ulpi";
 296                 };
 297                 */
 298
 299                 sdhci@2e000 {
 300                         compatible = "fsl,p1020-esdhc", "fsl,esdhc";
 301                         reg = <0x2e000 0x1000>;
 302                         interrupts = <72 0x2>;
 303                         interrupt-parent = <&mpic>;
 304                         /* Filled in by U-Boot */
 305                         clock-frequency = <0>;
 306                 };
 307
 308                 crypto@30000 {
 309                         compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
 310                                      "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 311                         reg = <0x30000 0x10000>;
 312                         interrupts = <45 2 58 2>;
 313                         interrupt-parent = <&mpic>;
 314                         fsl,num-channels = <4>;
 315                         fsl,channel-fifo-len = <24>;
 316                         fsl,exec-units-mask = <0xbfe>;
 317                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 318                 };
 319
 320                 mpic: pic@40000 {
 321                         interrupt-controller;
 322                         #address-cells = <0>;
 323                         #interrupt-cells = <2>;
 324                         reg = <0x40000 0x40000>;
 325                         compatible = "chrp,open-pic";
 326                         device_type = "open-pic";
 327                 };
 328
 329                 msi@41600 {
 330                         compatible = "fsl,p1020-msi", "fsl,mpic-msi";
 331                         reg = <0x41600 0x80>;
 332                         msi-available-ranges = <0 0x100>;
 333                         interrupts = <
 334                                 0xe0 0
 335                                 0xe1 0
 336                                 0xe2 0
 337                                 0xe3 0
 338                                 0xe4 0
 339                                 0xe5 0
 340                                 0xe6 0
 341                                 0xe7 0>;
 342                         interrupt-parent = <&mpic>;
 343                 };
 344
 345                 global-utilities@e0000 {        //global utilities block
 346                         compatible = "fsl,p1020-guts","fsl,p2020-guts";
 347                         reg = <0xe0000 0x1000>;
 348                         fsl,has-rstcr;
 349                 };
 350         };
 351
 352         pci0: pcie@ffe09000 {
 353                 compatible = "fsl,mpc8548-pcie";
 354                 device_type = "pci";
 355                 #interrupt-cells = <1>;
 356                 #size-cells = <2>;
 357                 #address-cells = <3>;
 358                 reg = <0 0xffe09000 0 0x1000>;
 359                 bus-range = <0 255>;
 360                 clock-frequency = <33333333>;
 361                 interrupt-parent = <&mpic>;
 362                 interrupts = <16 2>;
 363         };
 364
 365         pci1: pcie@ffe0a000 {
 366                 compatible = "fsl,mpc8548-pcie";
 367                 device_type = "pci";
 368                 #interrupt-cells = <1>;
 369                 #size-cells = <2>;
 370                 #address-cells = <3>;
 371                 reg = <0 0xffe0a000 0 0x1000>;
 372                 bus-range = <0 255>;
 373                 clock-frequency = <33333333>;
 374                 interrupt-parent = <&mpic>;
 375                 interrupts = <16 2>;
 376         };
 377 };