arch/powerpc/boot/dts/p1010si.dtsi

   1 /*
   2  * P1010si Device Tree Source
   3  *
   4  * Copyright 2011 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         compatible = "fsl,P1010";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 PowerPC,P1010@0 {
  23                         device_type = "cpu";
  24                         reg = <0x0>;
  25                         next-level-cache = <&L2>;
  26                 };
  27         };
  28
  29         ifc@ffe1e000 {
  30                 #address-cells = <2>;
  31                 #size-cells = <1>;
  32                 compatible = "fsl,ifc", "simple-bus";
  33                 reg = <0x0 0xffe1e000 0 0x2000>;
  34                 interrupts = <16 2 19 2>;
  35                 interrupt-parent = <&mpic>;
  36         };
  37
  38         soc@ffe00000 {
  39                 #address-cells = <1>;
  40                 #size-cells = <1>;
  41                 device_type = "soc";
  42                 compatible = "fsl,p1010-immr", "simple-bus";
  43                 ranges = <0x0  0x0 0xffe00000 0x100000>;
  44                 bus-frequency = <0>;            // Filled out by uboot.
  45
  46                 ecm-law@0 {
  47                         compatible = "fsl,ecm-law";
  48                         reg = <0x0 0x1000>;
  49                         fsl,num-laws = <12>;
  50                 };
  51
  52                 ecm@1000 {
  53                         compatible = "fsl,p1010-ecm", "fsl,ecm";
  54                         reg = <0x1000 0x1000>;
  55                         interrupts = <16 2>;
  56                         interrupt-parent = <&mpic>;
  57                 };
  58
  59                 memory-controller@2000 {
  60                         compatible = "fsl,p1010-memory-controller";
  61                         reg = <0x2000 0x1000>;
  62                         interrupt-parent = <&mpic>;
  63                         interrupts = <16 2>;
  64                 };
  65
  66                 i2c@3000 {
  67                         #address-cells = <1>;
  68                         #size-cells = <0>;
  69                         cell-index = <0>;
  70                         compatible = "fsl-i2c";
  71                         reg = <0x3000 0x100>;
  72                         interrupts = <43 2>;
  73                         interrupt-parent = <&mpic>;
  74                         dfsrr;
  75                 };
  76
  77                 i2c@3100 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         cell-index = <1>;
  81                         compatible = "fsl-i2c";
  82                         reg = <0x3100 0x100>;
  83                         interrupts = <43 2>;
  84                         interrupt-parent = <&mpic>;
  85                         dfsrr;
  86                 };
  87
  88                 serial0: serial@4500 {
  89                         cell-index = <0>;
  90                         device_type = "serial";
  91                         compatible = "ns16550";
  92                         reg = <0x4500 0x100>;
  93                         clock-frequency = <0>;
  94                         interrupts = <42 2>;
  95                         interrupt-parent = <&mpic>;
  96                 };
  97
  98                 serial1: serial@4600 {
  99                         cell-index = <1>;
 100                         device_type = "serial";
 101                         compatible = "ns16550";
 102                         reg = <0x4600 0x100>;
 103                         clock-frequency = <0>;
 104                         interrupts = <42 2>;
 105                         interrupt-parent = <&mpic>;
 106                 };
 107
 108                 spi@7000 {
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         compatible = "fsl,mpc8536-espi";
 112                         reg = <0x7000 0x1000>;
 113                         interrupts = <59 0x2>;
 114                         interrupt-parent = <&mpic>;
 115                         fsl,espi-num-chipselects = <1>;
 116                 };
 117
 118                 gpio: gpio-controller@f000 {
 119                         #gpio-cells = <2>;
 120                         compatible = "fsl,mpc8572-gpio";
 121                         reg = <0xf000 0x100>;
 122                         interrupts = <47 0x2>;
 123                         interrupt-parent = <&mpic>;
 124                         gpio-controller;
 125                 };
 126
 127                 sata@18000 {
 128                         compatible = "fsl,pq-sata-v2";
 129                         reg = <0x18000 0x1000>;
 130                         cell-index = <1>;
 131                         interrupts = <74 0x2>;
 132                         interrupt-parent = <&mpic>;
 133                 };
 134
 135                 sata@19000 {
 136                         compatible = "fsl,pq-sata-v2";
 137                         reg = <0x19000 0x1000>;
 138                         cell-index = <2>;
 139                         interrupts = <41 0x2>;
 140                         interrupt-parent = <&mpic>;
 141                 };
 142
 143                 can0@1c000 {
 144                         compatible = "fsl,flexcan-v1.0";
 145                         reg = <0x1c000 0x1000>;
 146                         interrupts = <48 0x2>;
 147                         interrupt-parent = <&mpic>;
 148                         fsl,flexcan-clock-divider = <2>;
 149                 };
 150
 151                 can1@1d000 {
 152                         compatible = "fsl,flexcan-v1.0";
 153                         reg = <0x1d000 0x1000>;
 154                         interrupts = <61 0x2>;
 155                         interrupt-parent = <&mpic>;
 156                         fsl,flexcan-clock-divider = <2>;
 157                 };
 158
 159                 L2: l2-cache-controller@20000 {
 160                         compatible = "fsl,p1010-l2-cache-controller",
 161                                         "fsl,p1014-l2-cache-controller";
 162                         reg = <0x20000 0x1000>;
 163                         cache-line-size = <32>; // 32 bytes
 164                         cache-size = <0x40000>; // L2,256K
 165                         interrupt-parent = <&mpic>;
 166                         interrupts = <16 2>;
 167                 };
 168
 169                 dma@21300 {
 170                         #address-cells = <1>;
 171                         #size-cells = <1>;
 172                         compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
 173                         reg = <0x21300 0x4>;
 174                         ranges = <0x0 0x21100 0x200>;
 175                         cell-index = <0>;
 176                         dma-channel@0 {
 177                                 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
 178                                 reg = <0x0 0x80>;
 179                                 cell-index = <0>;
 180                                 interrupt-parent = <&mpic>;
 181                                 interrupts = <20 2>;
 182                         };
 183                         dma-channel@80 {
 184                                 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
 185                                 reg = <0x80 0x80>;
 186                                 cell-index = <1>;
 187                                 interrupt-parent = <&mpic>;
 188                                 interrupts = <21 2>;
 189                         };
 190                         dma-channel@100 {
 191                                 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
 192                                 reg = <0x100 0x80>;
 193                                 cell-index = <2>;
 194                                 interrupt-parent = <&mpic>;
 195                                 interrupts = <22 2>;
 196                         };
 197                         dma-channel@180 {
 198                                 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
 199                                 reg = <0x180 0x80>;
 200                                 cell-index = <3>;
 201                                 interrupt-parent = <&mpic>;
 202                                 interrupts = <23 2>;
 203                         };
 204                 };
 205
 206                 usb@22000 {
 207                         compatible = "fsl-usb2-dr";
 208                         reg = <0x22000 0x1000>;
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         interrupt-parent = <&mpic>;
 212                         interrupts = <28 0x2>;
 213                         dr_mode = "host";
 214                 };
 215
 216                 mdio@24000 {
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         compatible = "fsl,etsec2-mdio";
 220                         reg = <0x24000 0x1000 0xb0030 0x4>;
 221                 };
 222
 223                 mdio@25000 {
 224                         #address-cells = <1>;
 225                         #size-cells = <0>;
 226                         compatible = "fsl,etsec2-tbi";
 227                         reg = <0x25000 0x1000 0xb1030 0x4>;
 228                         tbi0: tbi-phy@11 {
 229                                 reg = <0x11>;
 230                                 device_type = "tbi-phy";
 231                         };
 232                 };
 233
 234                 mdio@26000 {
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237                         compatible = "fsl,etsec2-tbi";
 238                         reg = <0x26000 0x1000 0xb1030 0x4>;
 239                         tbi1: tbi-phy@11 {
 240                                 reg = <0x11>;
 241                                 device_type = "tbi-phy";
 242                         };
 243                 };
 244
 245                 sdhci@2e000 {
 246                         compatible = "fsl,esdhc";
 247                         reg = <0x2e000 0x1000>;
 248                         interrupts = <72 0x8>;
 249                         interrupt-parent = <&mpic>;
 250                         /* Filled in by U-Boot */
 251                         clock-frequency = <0>;
 252                         fsl,sdhci-auto-cmd12;
 253                 };
 254
 255                 enet0: ethernet@b0000 {
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258                         device_type = "network";
 259                         model = "eTSEC";
 260                         compatible = "fsl,etsec2";
 261                         fsl,num_rx_queues = <0x8>;
 262                         fsl,num_tx_queues = <0x8>;
 263                         local-mac-address = [ 00 00 00 00 00 00 ];
 264                         interrupt-parent = <&mpic>;
 265
 266                         queue-group@0 {
 267                                 #address-cells = <1>;
 268                                 #size-cells = <1>;
 269                                 reg = <0xb0000 0x1000>;
 270                                 fsl,rx-bit-map = <0xff>;
 271                                 fsl,tx-bit-map = <0xff>;
 272                                 interrupts = <29 2 30 2 34 2>;
 273                         };
 274
 275                 };
 276
 277                 enet1: ethernet@b1000 {
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280                         device_type = "network";
 281                         model = "eTSEC";
 282                         compatible = "fsl,etsec2";
 283                         fsl,num_rx_queues = <0x8>;
 284                         fsl,num_tx_queues = <0x8>;
 285                         local-mac-address = [ 00 00 00 00 00 00 ];
 286                         interrupt-parent = <&mpic>;
 287
 288                         queue-group@0 {
 289                                 #address-cells = <1>;
 290                                 #size-cells = <1>;
 291                                 reg = <0xb1000 0x1000>;
 292                                 fsl,rx-bit-map = <0xff>;
 293                                 fsl,tx-bit-map = <0xff>;
 294                                 interrupts = <35 2 36 2 40 2>;
 295                         };
 296
 297                 };
 298
 299                 enet2: ethernet@b2000 {
 300                         #address-cells = <1>;
 301                         #size-cells = <1>;
 302                         device_type = "network";
 303                         model = "eTSEC";
 304                         compatible = "fsl,etsec2";
 305                         fsl,num_rx_queues = <0x8>;
 306                         fsl,num_tx_queues = <0x8>;
 307                         local-mac-address = [ 00 00 00 00 00 00 ];
 308                         interrupt-parent = <&mpic>;
 309
 310                         queue-group@0 {
 311                                 #address-cells = <1>;
 312                                 #size-cells = <1>;
 313                                 reg = <0xb2000 0x1000>;
 314                                 fsl,rx-bit-map = <0xff>;
 315                                 fsl,tx-bit-map = <0xff>;
 316                                 interrupts = <31 2 32 2 33 2>;
 317                         };
 318
 319                 };
 320
 321                 mpic: pic@40000 {
 322                         interrupt-controller;
 323                         #address-cells = <0>;
 324                         #interrupt-cells = <2>;
 325                         reg = <0x40000 0x40000>;
 326                         compatible = "chrp,open-pic";
 327                         device_type = "open-pic";
 328                 };
 329
 330                 msi@41600 {
 331                         compatible = "fsl,p1010-msi", "fsl,mpic-msi";
 332                         reg = <0x41600 0x80>;
 333                         msi-available-ranges = <0 0x100>;
 334                         interrupts = <
 335                                 0xe0 0
 336                                 0xe1 0
 337                                 0xe2 0
 338                                 0xe3 0
 339                                 0xe4 0
 340                                 0xe5 0
 341                                 0xe6 0
 342                                 0xe7 0>;
 343                         interrupt-parent = <&mpic>;
 344                 };
 345
 346                 global-utilities@e0000 {        //global utilities block
 347                         compatible = "fsl,p1010-guts";
 348                         reg = <0xe0000 0x1000>;
 349                         fsl,has-rstcr;
 350                 };
 351         };
 352
 353         pci0: pcie@ffe09000 {
 354                 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
 355                 device_type = "pci";
 356                 #size-cells = <2>;
 357                 #address-cells = <3>;
 358                 reg = <0 0xffe09000 0 0x1000>;
 359                 bus-range = <0 255>;
 360                 clock-frequency = <33333333>;
 361                 interrupt-parent = <&mpic>;
 362                 interrupts = <16 2>;
 363         };
 364
 365         pci1: pcie@ffe0a000 {
 366                 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
 367                 device_type = "pci";
 368                 #size-cells = <2>;
 369                 #address-cells = <3>;
 370                 reg = <0 0xffe0a000 0 0x1000>;
 371                 bus-range = <0 255>;
 372                 clock-frequency = <33333333>;
 373                 interrupt-parent = <&mpic>;
 374                 interrupts = <16 2>;
 375         };
 376 };