arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8568EMDS";
  16         compatible = "MPC8568EMDS", "MPC85xxMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8568@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;
  43                         bus-frequency = <0>;
  44                         clock-frequency = <0>;
  45                         next-level-cache = <&L2>;
  46                 };
  47         };
  48
  49         memory {
  50                 device_type = "memory";
  51                 reg = <0x0 0x10000000>;
  52         };
  53
  54         bcsr@f8000000 {
  55                 device_type = "board-control";
  56                 reg = <0xf8000000 0x8000>;
  57         };
  58
  59         soc8568@e0000000 {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 device_type = "soc";
  63                 ranges = <0x0 0xe0000000 0x100000>;
  64                 reg = <0xe0000000 0x1000>;
  65                 bus-frequency = <0>;
  66
  67                 memory-controller@2000 {
  68                         compatible = "fsl,8568-memory-controller";
  69                         reg = <0x2000 0x1000>;
  70                         interrupt-parent = <&mpic>;
  71                         interrupts = <18 2>;
  72                 };
  73
  74                 L2: l2-cache-controller@20000 {
  75                         compatible = "fsl,8568-l2-cache-controller";
  76                         reg = <0x20000 0x1000>;
  77                         cache-line-size = <32>; // 32 bytes
  78                         cache-size = <0x80000>; // L2, 512K
  79                         interrupt-parent = <&mpic>;
  80                         interrupts = <16 2>;
  81                 };
  82
  83                 i2c@3000 {
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86                         cell-index = <0>;
  87                         compatible = "fsl-i2c";
  88                         reg = <0x3000 0x100>;
  89                         interrupts = <43 2>;
  90                         interrupt-parent = <&mpic>;
  91                         dfsrr;
  92
  93                         rtc@68 {
  94                                 compatible = "dallas,ds1374";
  95                                 reg = <0x68>;
  96                         };
  97                 };
  98
  99                 i2c@3100 {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         cell-index = <1>;
 103                         compatible = "fsl-i2c";
 104                         reg = <0x3100 0x100>;
 105                         interrupts = <43 2>;
 106                         interrupt-parent = <&mpic>;
 107                         dfsrr;
 108                 };
 109
 110                 dma@21300 {
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
 114                         reg = <0x21300 0x4>;
 115                         ranges = <0x0 0x21100 0x200>;
 116                         cell-index = <0>;
 117                         dma-channel@0 {
 118                                 compatible = "fsl,mpc8568-dma-channel",
 119                                                 "fsl,eloplus-dma-channel";
 120                                 reg = <0x0 0x80>;
 121                                 cell-index = <0>;
 122                                 interrupt-parent = <&mpic>;
 123                                 interrupts = <20 2>;
 124                         };
 125                         dma-channel@80 {
 126                                 compatible = "fsl,mpc8568-dma-channel",
 127                                                 "fsl,eloplus-dma-channel";
 128                                 reg = <0x80 0x80>;
 129                                 cell-index = <1>;
 130                                 interrupt-parent = <&mpic>;
 131                                 interrupts = <21 2>;
 132                         };
 133                         dma-channel@100 {
 134                                 compatible = "fsl,mpc8568-dma-channel",
 135                                                 "fsl,eloplus-dma-channel";
 136                                 reg = <0x100 0x80>;
 137                                 cell-index = <2>;
 138                                 interrupt-parent = <&mpic>;
 139                                 interrupts = <22 2>;
 140                         };
 141                         dma-channel@180 {
 142                                 compatible = "fsl,mpc8568-dma-channel",
 143                                                 "fsl,eloplus-dma-channel";
 144                                 reg = <0x180 0x80>;
 145                                 cell-index = <3>;
 146                                 interrupt-parent = <&mpic>;
 147                                 interrupts = <23 2>;
 148                         };
 149                 };
 150
 151                 mdio@24520 {
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                         compatible = "fsl,gianfar-mdio";
 155                         reg = <0x24520 0x20>;
 156
 157                         phy0: ethernet-phy@7 {
 158                                 interrupt-parent = <&mpic>;
 159                                 interrupts = <1 1>;
 160                                 reg = <0x7>;
 161                                 device_type = "ethernet-phy";
 162                         };
 163                         phy1: ethernet-phy@1 {
 164                                 interrupt-parent = <&mpic>;
 165                                 interrupts = <2 1>;
 166                                 reg = <0x1>;
 167                                 device_type = "ethernet-phy";
 168                         };
 169                         phy2: ethernet-phy@2 {
 170                                 interrupt-parent = <&mpic>;
 171                                 interrupts = <1 1>;
 172                                 reg = <0x2>;
 173                                 device_type = "ethernet-phy";
 174                         };
 175                         phy3: ethernet-phy@3 {
 176                                 interrupt-parent = <&mpic>;
 177                                 interrupts = <2 1>;
 178                                 reg = <0x3>;
 179                                 device_type = "ethernet-phy";
 180                         };
 181                 };
 182
 183                 enet0: ethernet@24000 {
 184                         cell-index = <0>;
 185                         device_type = "network";
 186                         model = "eTSEC";
 187                         compatible = "gianfar";
 188                         reg = <0x24000 0x1000>;
 189                         local-mac-address = [ 00 00 00 00 00 00 ];
 190                         interrupts = <29 2 30 2 34 2>;
 191                         interrupt-parent = <&mpic>;
 192                         phy-handle = <&phy2>;
 193                 };
 194
 195                 enet1: ethernet@25000 {
 196                         cell-index = <1>;
 197                         device_type = "network";
 198                         model = "eTSEC";
 199                         compatible = "gianfar";
 200                         reg = <0x25000 0x1000>;
 201                         local-mac-address = [ 00 00 00 00 00 00 ];
 202                         interrupts = <35 2 36 2 40 2>;
 203                         interrupt-parent = <&mpic>;
 204                         phy-handle = <&phy3>;
 205                 };
 206
 207                 serial0: serial@4500 {
 208                         cell-index = <0>;
 209                         device_type = "serial";
 210                         compatible = "ns16550";
 211                         reg = <0x4500 0x100>;
 212                         clock-frequency = <0>;
 213                         interrupts = <42 2>;
 214                         interrupt-parent = <&mpic>;
 215                 };
 216
 217                 global-utilities@e0000 {        //global utilities block
 218                         compatible = "fsl,mpc8548-guts";
 219                         reg = <0xe0000 0x1000>;
 220                         fsl,has-rstcr;
 221                 };
 222
 223                 serial1: serial@4600 {
 224                         cell-index = <1>;
 225                         device_type = "serial";
 226                         compatible = "ns16550";
 227                         reg = <0x4600 0x100>;
 228                         clock-frequency = <0>;
 229                         interrupts = <42 2>;
 230                         interrupt-parent = <&mpic>;
 231                 };
 232
 233                 crypto@30000 {
 234                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 235                         reg = <0x30000 0x10000>;
 236                         interrupts = <45 2>;
 237                         interrupt-parent = <&mpic>;
 238                         fsl,num-channels = <4>;
 239                         fsl,channel-fifo-len = <24>;
 240                         fsl,exec-units-mask = <0xfe>;
 241                         fsl,descriptor-types-mask = <0x12b0ebf>;
 242                 };
 243
 244                 mpic: pic@40000 {
 245                         interrupt-controller;
 246                         #address-cells = <0>;
 247                         #interrupt-cells = <2>;
 248                         reg = <0x40000 0x40000>;
 249                         compatible = "chrp,open-pic";
 250                         device_type = "open-pic";
 251                 };
 252
 253                 par_io@e0100 {
 254                         reg = <0xe0100 0x100>;
 255                         device_type = "par_io";
 256                         num-ports = <7>;
 257
 258                         pio1: ucc_pin@01 {
 259                                 pio-map = <
 260                         /* port  pin  dir  open_drain  assignment  has_irq */
 261                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
 262                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
 263                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
 264                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
 265                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
 266                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
 267                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
 268                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
 269                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
 270                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
 271                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
 272                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
 273                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
 274                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
 275                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
 276                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
 277                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
 278                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
 279                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
 280                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
 281                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
 282                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
 283                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
 284                         };
 285
 286                         pio2: ucc_pin@02 {
 287                                 pio-map = <
 288                         /* port  pin  dir  open_drain  assignment  has_irq */
 289                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
 290                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
 291                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
 292                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
 293                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
 294                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
 295                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
 296                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
 297                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
 298                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
 299                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
 300                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
 301                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
 302                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
 303                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
 304                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
 305                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
 306                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
 307                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
 308                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
 309                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
 310                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
 311                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
 312                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
 313                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
 314                         };
 315                 };
 316         };
 317
 318         qe@e0080000 {
 319                 #address-cells = <1>;
 320                 #size-cells = <1>;
 321                 device_type = "qe";
 322                 compatible = "fsl,qe";
 323                 ranges = <0x0 0xe0080000 0x40000>;
 324                 reg = <0xe0080000 0x480>;
 325                 brg-frequency = <0>;
 326                 bus-frequency = <396000000>;
 327
 328                 muram@10000 {
 329                         #address-cells = <1>;
 330                         #size-cells = <1>;
 331                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 332                         ranges = <0x0 0x10000 0x10000>;
 333
 334                         data-only@0 {
 335                                 compatible = "fsl,qe-muram-data",
 336                                              "fsl,cpm-muram-data";
 337                                 reg = <0x0 0x10000>;
 338                         };
 339                 };
 340
 341                 spi@4c0 {
 342                         cell-index = <0>;
 343                         compatible = "fsl,spi";
 344                         reg = <0x4c0 0x40>;
 345                         interrupts = <2>;
 346                         interrupt-parent = <&qeic>;
 347                         mode = "cpu";
 348                 };
 349
 350                 spi@500 {
 351                         cell-index = <1>;
 352                         compatible = "fsl,spi";
 353                         reg = <0x500 0x40>;
 354                         interrupts = <1>;
 355                         interrupt-parent = <&qeic>;
 356                         mode = "cpu";
 357                 };
 358
 359                 enet2: ucc@2000 {
 360                         device_type = "network";
 361                         compatible = "ucc_geth";
 362                         cell-index = <1>;
 363                         reg = <0x2000 0x200>;
 364                         interrupts = <32>;
 365                         interrupt-parent = <&qeic>;
 366                         local-mac-address = [ 00 00 00 00 00 00 ];
 367                         rx-clock-name = "none";
 368                         tx-clock-name = "clk16";
 369                         pio-handle = <&pio1>;
 370                         phy-handle = <&phy0>;
 371                         phy-connection-type = "rgmii-id";
 372                 };
 373
 374                 enet3: ucc@3000 {
 375                         device_type = "network";
 376                         compatible = "ucc_geth";
 377                         cell-index = <2>;
 378                         reg = <0x3000 0x200>;
 379                         interrupts = <33>;
 380                         interrupt-parent = <&qeic>;
 381                         local-mac-address = [ 00 00 00 00 00 00 ];
 382                         rx-clock-name = "none";
 383                         tx-clock-name = "clk16";
 384                         pio-handle = <&pio2>;
 385                         phy-handle = <&phy1>;
 386                         phy-connection-type = "rgmii-id";
 387                 };
 388
 389                 mdio@2120 {
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         reg = <0x2120 0x18>;
 393                         compatible = "fsl,ucc-mdio";
 394
 395                         /* These are the same PHYs as on
 396                          * gianfar's MDIO bus */
 397                         qe_phy0: ethernet-phy@07 {
 398                                 interrupt-parent = <&mpic>;
 399                                 interrupts = <1 1>;
 400                                 reg = <0x7>;
 401                                 device_type = "ethernet-phy";
 402                         };
 403                         qe_phy1: ethernet-phy@01 {
 404                                 interrupt-parent = <&mpic>;
 405                                 interrupts = <2 1>;
 406                                 reg = <0x1>;
 407                                 device_type = "ethernet-phy";
 408                         };
 409                         qe_phy2: ethernet-phy@02 {
 410                                 interrupt-parent = <&mpic>;
 411                                 interrupts = <1 1>;
 412                                 reg = <0x2>;
 413                                 device_type = "ethernet-phy";
 414                         };
 415                         qe_phy3: ethernet-phy@03 {
 416                                 interrupt-parent = <&mpic>;
 417                                 interrupts = <2 1>;
 418                                 reg = <0x3>;
 419                                 device_type = "ethernet-phy";
 420                         };
 421                 };
 422
 423                 qeic: interrupt-controller@80 {
 424                         interrupt-controller;
 425                         compatible = "fsl,qe-ic";
 426                         #address-cells = <0>;
 427                         #interrupt-cells = <1>;
 428                         reg = <0x80 0x80>;
 429                         big-endian;
 430                         interrupts = <46 2 46 2>; //high:30 low:30
 431                         interrupt-parent = <&mpic>;
 432                 };
 433
 434         };
 435
 436         pci0: pci@e0008000 {
 437                 cell-index = <0>;
 438                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 439                 interrupt-map = <
 440                         /* IDSEL 0x12 AD18 */
 441                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
 442                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
 443                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
 444                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 445
 446                         /* IDSEL 0x13 AD19 */
 447                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
 448                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
 449                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
 450                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 451
 452                 interrupt-parent = <&mpic>;
 453                 interrupts = <24 2>;
 454                 bus-range = <0 255>;
 455                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 456                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 457                 clock-frequency = <66666666>;
 458                 #interrupt-cells = <1>;
 459                 #size-cells = <2>;
 460                 #address-cells = <3>;
 461                 reg = <0xe0008000 0x1000>;
 462                 compatible = "fsl,mpc8540-pci";
 463                 device_type = "pci";
 464         };
 465
 466         /* PCI Express */
 467         pci1: pcie@e000a000 {
 468                 cell-index = <2>;
 469                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 470                 interrupt-map = <
 471
 472                         /* IDSEL 0x0 (PEX) */
 473                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 474                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 475                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 476                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 477
 478                 interrupt-parent = <&mpic>;
 479                 interrupts = <26 2>;
 480                 bus-range = <0 255>;
 481                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 482                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 483                 clock-frequency = <33333333>;
 484                 #interrupt-cells = <1>;
 485                 #size-cells = <2>;
 486                 #address-cells = <3>;
 487                 reg = <0xe000a000 0x1000>;
 488                 compatible = "fsl,mpc8548-pcie";
 489                 device_type = "pci";
 490                 pcie@0 {
 491                         reg = <0x0 0x0 0x0 0x0 0x0>;
 492                         #size-cells = <2>;
 493                         #address-cells = <3>;
 494                         device_type = "pci";
 495                         ranges = <0x2000000 0x0 0xa0000000
 496                                   0x2000000 0x0 0xa0000000
 497                                   0x0 0x10000000
 498
 499                                   0x1000000 0x0 0x0
 500                                   0x1000000 0x0 0x0
 501                                   0x0 0x800000>;
 502                 };
 503         };
 504 };