arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8568EMDS";
  16         compatible = "MPC8568EMDS", "MPC85xxMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 pci0 = &pci0;
  28                 pci1 = &pci1;
  29                 rapidio0 = &rio0;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 PowerPC,8568@0 {
  37                         device_type = "cpu";
  38                         reg = <0x0>;
  39                         d-cache-line-size = <32>;       // 32 bytes
  40                         i-cache-line-size = <32>;       // 32 bytes
  41                         d-cache-size = <0x8000>;                // L1, 32K
  42                         i-cache-size = <0x8000>;                // L1, 32K
  43                         sleep = <&pmc 0x00008000        // core
  44                                  &pmc 0x00004000>;      // timebase
  45                         timebase-frequency = <0>;
  46                         bus-frequency = <0>;
  47                         clock-frequency = <0>;
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         memory {
  53                 device_type = "memory";
  54                 reg = <0x0 0x10000000>;
  55         };
  56
  57         localbus@e0005000 {
  58                 #address-cells = <2>;
  59                 #size-cells = <1>;
  60                 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
  61                              "simple-bus";
  62                 reg = <0xe0005000 0x1000>;
  63
  64                 ranges = <0x0 0x0 0xfe000000 0x02000000
  65                           0x1 0x0 0xf8000000 0x00008000
  66                           0x2 0x0 0xf0000000 0x04000000
  67                           0x4 0x0 0xf8008000 0x00008000
  68                           0x5 0x0 0xf8010000 0x00008000>;
  69
  70                 nor@0,0 {
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         compatible = "cfi-flash";
  74                         reg = <0x0 0x0 0x02000000>;
  75                         bank-width = <2>;
  76                         device-width = <2>;
  77                 };
  78
  79                 bcsr@1,0 {
  80                         #address-cells = <1>;
  81                         #size-cells = <1>;
  82                         compatible = "fsl,mpc8568mds-bcsr";
  83                         reg = <1 0 0x8000>;
  84                         ranges = <0 1 0 0x8000>;
  85
  86                         bcsr5: gpio-controller@11 {
  87                                 #gpio-cells = <2>;
  88                                 compatible = "fsl,mpc8568mds-bcsr-gpio";
  89                                 reg = <0x5 0x1>;
  90                                 gpio-controller;
  91                         };
  92                 };
  93
  94                 pib@4,0 {
  95                         compatible = "fsl,mpc8568mds-pib";
  96                         reg = <4 0 0x8000>;
  97                 };
  98
  99                 pib@5,0 {
 100                         compatible = "fsl,mpc8568mds-pib";
 101                         reg = <5 0 0x8000>;
 102                 };
 103         };
 104
 105         soc8568@e0000000 {
 106                 #address-cells = <1>;
 107                 #size-cells = <1>;
 108                 device_type = "soc";
 109                 compatible = "simple-bus";
 110                 ranges = <0x0 0xe0000000 0x100000>;
 111                 bus-frequency = <0>;
 112
 113                 ecm-law@0 {
 114                         compatible = "fsl,ecm-law";
 115                         reg = <0x0 0x1000>;
 116                         fsl,num-laws = <10>;
 117                 };
 118
 119                 ecm@1000 {
 120                         compatible = "fsl,mpc8568-ecm", "fsl,ecm";
 121                         reg = <0x1000 0x1000>;
 122                         interrupts = <17 2>;
 123                         interrupt-parent = <&mpic>;
 124                 };
 125
 126                 memory-controller@2000 {
 127                         compatible = "fsl,mpc8568-memory-controller";
 128                         reg = <0x2000 0x1000>;
 129                         interrupt-parent = <&mpic>;
 130                         interrupts = <18 2>;
 131                 };
 132
 133                 L2: l2-cache-controller@20000 {
 134                         compatible = "fsl,mpc8568-l2-cache-controller";
 135                         reg = <0x20000 0x1000>;
 136                         cache-line-size = <32>; // 32 bytes
 137                         cache-size = <0x80000>; // L2, 512K
 138                         interrupt-parent = <&mpic>;
 139                         interrupts = <16 2>;
 140                 };
 141
 142                 i2c-sleep-nexus {
 143                         #address-cells = <1>;
 144                         #size-cells = <1>;
 145                         compatible = "simple-bus";
 146                         sleep = <&pmc 0x00000004>;
 147                         ranges;
 148
 149                         i2c@3000 {
 150                                 #address-cells = <1>;
 151                                 #size-cells = <0>;
 152                                 cell-index = <0>;
 153                                 compatible = "fsl-i2c";
 154                                 reg = <0x3000 0x100>;
 155                                 interrupts = <43 2>;
 156                                 interrupt-parent = <&mpic>;
 157                                 dfsrr;
 158
 159                                 rtc@68 {
 160                                         compatible = "dallas,ds1374";
 161                                         reg = <0x68>;
 162                                         interrupts = <3 1>;
 163                                         interrupt-parent = <&mpic>;
 164                                 };
 165                         };
 166
 167                         i2c@3100 {
 168                                 #address-cells = <1>;
 169                                 #size-cells = <0>;
 170                                 cell-index = <1>;
 171                                 compatible = "fsl-i2c";
 172                                 reg = <0x3100 0x100>;
 173                                 interrupts = <43 2>;
 174                                 interrupt-parent = <&mpic>;
 175                                 dfsrr;
 176                         };
 177                 };
 178
 179                 dma@21300 {
 180                         #address-cells = <1>;
 181                         #size-cells = <1>;
 182                         compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
 183                         reg = <0x21300 0x4>;
 184                         ranges = <0x0 0x21100 0x200>;
 185                         cell-index = <0>;
 186                         sleep = <&pmc 0x00000400>;
 187
 188                         dma-channel@0 {
 189                                 compatible = "fsl,mpc8568-dma-channel",
 190                                                 "fsl,eloplus-dma-channel";
 191                                 reg = <0x0 0x80>;
 192                                 cell-index = <0>;
 193                                 interrupt-parent = <&mpic>;
 194                                 interrupts = <20 2>;
 195                         };
 196                         dma-channel@80 {
 197                                 compatible = "fsl,mpc8568-dma-channel",
 198                                                 "fsl,eloplus-dma-channel";
 199                                 reg = <0x80 0x80>;
 200                                 cell-index = <1>;
 201                                 interrupt-parent = <&mpic>;
 202                                 interrupts = <21 2>;
 203                         };
 204                         dma-channel@100 {
 205                                 compatible = "fsl,mpc8568-dma-channel",
 206                                                 "fsl,eloplus-dma-channel";
 207                                 reg = <0x100 0x80>;
 208                                 cell-index = <2>;
 209                                 interrupt-parent = <&mpic>;
 210                                 interrupts = <22 2>;
 211                         };
 212                         dma-channel@180 {
 213                                 compatible = "fsl,mpc8568-dma-channel",
 214                                                 "fsl,eloplus-dma-channel";
 215                                 reg = <0x180 0x80>;
 216                                 cell-index = <3>;
 217                                 interrupt-parent = <&mpic>;
 218                                 interrupts = <23 2>;
 219                         };
 220                 };
 221
 222                 enet0: ethernet@24000 {
 223                         #address-cells = <1>;
 224                         #size-cells = <1>;
 225                         cell-index = <0>;
 226                         device_type = "network";
 227                         model = "eTSEC";
 228                         compatible = "gianfar";
 229                         reg = <0x24000 0x1000>;
 230                         ranges = <0x0 0x24000 0x1000>;
 231                         local-mac-address = [ 00 00 00 00 00 00 ];
 232                         interrupts = <29 2 30 2 34 2>;
 233                         interrupt-parent = <&mpic>;
 234                         tbi-handle = <&tbi0>;
 235                         phy-handle = <&phy2>;
 236                         sleep = <&pmc 0x00000080>;
 237
 238                         mdio@520 {
 239                                 #address-cells = <1>;
 240                                 #size-cells = <0>;
 241                                 compatible = "fsl,gianfar-mdio";
 242                                 reg = <0x520 0x20>;
 243
 244                                 phy0: ethernet-phy@7 {
 245                                         interrupt-parent = <&mpic>;
 246                                         interrupts = <1 1>;
 247                                         reg = <0x7>;
 248                                         device_type = "ethernet-phy";
 249                                 };
 250                                 phy1: ethernet-phy@1 {
 251                                         interrupt-parent = <&mpic>;
 252                                         interrupts = <2 1>;
 253                                         reg = <0x1>;
 254                                         device_type = "ethernet-phy";
 255                                 };
 256                                 phy2: ethernet-phy@2 {
 257                                         interrupt-parent = <&mpic>;
 258                                         interrupts = <1 1>;
 259                                         reg = <0x2>;
 260                                         device_type = "ethernet-phy";
 261                                 };
 262                                 phy3: ethernet-phy@3 {
 263                                         interrupt-parent = <&mpic>;
 264                                         interrupts = <2 1>;
 265                                         reg = <0x3>;
 266                                         device_type = "ethernet-phy";
 267                                 };
 268                                 tbi0: tbi-phy@11 {
 269                                         reg = <0x11>;
 270                                         device_type = "tbi-phy";
 271                                 };
 272                         };
 273                 };
 274
 275                 enet1: ethernet@25000 {
 276                         #address-cells = <1>;
 277                         #size-cells = <1>;
 278                         cell-index = <1>;
 279                         device_type = "network";
 280                         model = "eTSEC";
 281                         compatible = "gianfar";
 282                         reg = <0x25000 0x1000>;
 283                         ranges = <0x0 0x25000 0x1000>;
 284                         local-mac-address = [ 00 00 00 00 00 00 ];
 285                         interrupts = <35 2 36 2 40 2>;
 286                         interrupt-parent = <&mpic>;
 287                         tbi-handle = <&tbi1>;
 288                         phy-handle = <&phy3>;
 289                         sleep = <&pmc 0x00000040>;
 290
 291                         mdio@520 {
 292                                 #address-cells = <1>;
 293                                 #size-cells = <0>;
 294                                 compatible = "fsl,gianfar-tbi";
 295                                 reg = <0x520 0x20>;
 296
 297                                 tbi1: tbi-phy@11 {
 298                                         reg = <0x11>;
 299                                         device_type = "tbi-phy";
 300                                 };
 301                         };
 302                 };
 303
 304                 duart-sleep-nexus {
 305                         #address-cells = <1>;
 306                         #size-cells = <1>;
 307                         compatible = "simple-bus";
 308                         sleep = <&pmc 0x00000002>;
 309                         ranges;
 310
 311                         serial0: serial@4500 {
 312                                 cell-index = <0>;
 313                                 device_type = "serial";
 314                                 compatible = "ns16550";
 315                                 reg = <0x4500 0x100>;
 316                                 clock-frequency = <0>;
 317                                 interrupts = <42 2>;
 318                                 interrupt-parent = <&mpic>;
 319                         };
 320
 321                         serial1: serial@4600 {
 322                                 cell-index = <1>;
 323                                 device_type = "serial";
 324                                 compatible = "ns16550";
 325                                 reg = <0x4600 0x100>;
 326                                 clock-frequency = <0>;
 327                                 interrupts = <42 2>;
 328                                 interrupt-parent = <&mpic>;
 329                         };
 330                 };
 331
 332                 global-utilities@e0000 {
 333                         #address-cells = <1>;
 334                         #size-cells = <1>;
 335                         compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
 336                         reg = <0xe0000 0x1000>;
 337                         ranges = <0 0xe0000 0x1000>;
 338                         fsl,has-rstcr;
 339
 340                         pmc: power@70 {
 341                                 compatible = "fsl,mpc8568-pmc",
 342                                              "fsl,mpc8548-pmc";
 343                                 reg = <0x70 0x20>;
 344                         };
 345                 };
 346
 347                 crypto@30000 {
 348                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 349                         reg = <0x30000 0x10000>;
 350                         interrupts = <45 2>;
 351                         interrupt-parent = <&mpic>;
 352                         fsl,num-channels = <4>;
 353                         fsl,channel-fifo-len = <24>;
 354                         fsl,exec-units-mask = <0xfe>;
 355                         fsl,descriptor-types-mask = <0x12b0ebf>;
 356                         sleep = <&pmc 0x01000000>;
 357                 };
 358
 359                 mpic: pic@40000 {
 360                         interrupt-controller;
 361                         #address-cells = <0>;
 362                         #interrupt-cells = <2>;
 363                         reg = <0x40000 0x40000>;
 364                         compatible = "chrp,open-pic";
 365                         device_type = "open-pic";
 366                 };
 367
 368                 msi@41600 {
 369                         compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
 370                         reg = <0x41600 0x80>;
 371                         msi-available-ranges = <0 0x100>;
 372                         interrupts = <
 373                                 0xe0 0
 374                                 0xe1 0
 375                                 0xe2 0
 376                                 0xe3 0
 377                                 0xe4 0
 378                                 0xe5 0
 379                                 0xe6 0
 380                                 0xe7 0>;
 381                         interrupt-parent = <&mpic>;
 382                 };
 383
 384                 par_io@e0100 {
 385                         reg = <0xe0100 0x100>;
 386                         device_type = "par_io";
 387                         num-ports = <7>;
 388
 389                         pio1: ucc_pin@01 {
 390                                 pio-map = <
 391                         /* port  pin  dir  open_drain  assignment  has_irq */
 392                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
 393                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
 394                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
 395                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
 396                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
 397                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
 398                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
 399                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
 400                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
 401                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
 402                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
 403                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
 404                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
 405                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
 406                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
 407                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
 408                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
 409                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
 410                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
 411                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
 412                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
 413                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
 414                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
 415                         };
 416
 417                         pio2: ucc_pin@02 {
 418                                 pio-map = <
 419                         /* port  pin  dir  open_drain  assignment  has_irq */
 420                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
 421                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
 422                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
 423                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
 424                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
 425                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
 426                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
 427                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
 428                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
 429                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
 430                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
 431                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
 432                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
 433                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
 434                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
 435                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
 436                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
 437                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
 438                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
 439                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
 440                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
 441                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
 442                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
 443                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
 444                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
 445                         };
 446                 };
 447         };
 448
 449         qe@e0080000 {
 450                 #address-cells = <1>;
 451                 #size-cells = <1>;
 452                 device_type = "qe";
 453                 compatible = "fsl,qe";
 454                 ranges = <0x0 0xe0080000 0x40000>;
 455                 reg = <0xe0080000 0x480>;
 456                 sleep = <&pmc 0x00000800>;
 457                 brg-frequency = <0>;
 458                 bus-frequency = <396000000>;
 459                 fsl,qe-num-riscs = <2>;
 460                 fsl,qe-num-snums = <28>;
 461
 462                 muram@10000 {
 463                         #address-cells = <1>;
 464                         #size-cells = <1>;
 465                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 466                         ranges = <0x0 0x10000 0x10000>;
 467
 468                         data-only@0 {
 469                                 compatible = "fsl,qe-muram-data",
 470                                              "fsl,cpm-muram-data";
 471                                 reg = <0x0 0x10000>;
 472                         };
 473                 };
 474
 475                 spi@4c0 {
 476                         cell-index = <0>;
 477                         compatible = "fsl,spi";
 478                         reg = <0x4c0 0x40>;
 479                         interrupts = <2>;
 480                         interrupt-parent = <&qeic>;
 481                         mode = "cpu";
 482                 };
 483
 484                 spi@500 {
 485                         cell-index = <1>;
 486                         compatible = "fsl,spi";
 487                         reg = <0x500 0x40>;
 488                         interrupts = <1>;
 489                         interrupt-parent = <&qeic>;
 490                         mode = "cpu";
 491                 };
 492
 493                 enet2: ucc@2000 {
 494                         device_type = "network";
 495                         compatible = "ucc_geth";
 496                         cell-index = <1>;
 497                         reg = <0x2000 0x200>;
 498                         interrupts = <32>;
 499                         interrupt-parent = <&qeic>;
 500                         local-mac-address = [ 00 00 00 00 00 00 ];
 501                         rx-clock-name = "none";
 502                         tx-clock-name = "clk16";
 503                         pio-handle = <&pio1>;
 504                         phy-handle = <&phy0>;
 505                         phy-connection-type = "rgmii-id";
 506                 };
 507
 508                 enet3: ucc@3000 {
 509                         device_type = "network";
 510                         compatible = "ucc_geth";
 511                         cell-index = <2>;
 512                         reg = <0x3000 0x200>;
 513                         interrupts = <33>;
 514                         interrupt-parent = <&qeic>;
 515                         local-mac-address = [ 00 00 00 00 00 00 ];
 516                         rx-clock-name = "none";
 517                         tx-clock-name = "clk16";
 518                         pio-handle = <&pio2>;
 519                         phy-handle = <&phy1>;
 520                         phy-connection-type = "rgmii-id";
 521                 };
 522
 523                 mdio@2120 {
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         reg = <0x2120 0x18>;
 527                         compatible = "fsl,ucc-mdio";
 528
 529                         /* These are the same PHYs as on
 530                          * gianfar's MDIO bus */
 531                         qe_phy0: ethernet-phy@07 {
 532                                 interrupt-parent = <&mpic>;
 533                                 interrupts = <1 1>;
 534                                 reg = <0x7>;
 535                                 device_type = "ethernet-phy";
 536                         };
 537                         qe_phy1: ethernet-phy@01 {
 538                                 interrupt-parent = <&mpic>;
 539                                 interrupts = <2 1>;
 540                                 reg = <0x1>;
 541                                 device_type = "ethernet-phy";
 542                         };
 543                         qe_phy2: ethernet-phy@02 {
 544                                 interrupt-parent = <&mpic>;
 545                                 interrupts = <1 1>;
 546                                 reg = <0x2>;
 547                                 device_type = "ethernet-phy";
 548                         };
 549                         qe_phy3: ethernet-phy@03 {
 550                                 interrupt-parent = <&mpic>;
 551                                 interrupts = <2 1>;
 552                                 reg = <0x3>;
 553                                 device_type = "ethernet-phy";
 554                         };
 555                 };
 556
 557                 qeic: interrupt-controller@80 {
 558                         interrupt-controller;
 559                         compatible = "fsl,qe-ic";
 560                         #address-cells = <0>;
 561                         #interrupt-cells = <1>;
 562                         reg = <0x80 0x80>;
 563                         big-endian;
 564                         interrupts = <46 2 46 2>; //high:30 low:30
 565                         interrupt-parent = <&mpic>;
 566                 };
 567
 568         };
 569
 570         pci0: pci@e0008000 {
 571                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 572                 interrupt-map = <
 573                         /* IDSEL 0x12 AD18 */
 574                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
 575                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
 576                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
 577                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 578
 579                         /* IDSEL 0x13 AD19 */
 580                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
 581                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
 582                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
 583                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
 584
 585                 interrupt-parent = <&mpic>;
 586                 interrupts = <24 2>;
 587                 bus-range = <0 255>;
 588                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 589                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 590                 sleep = <&pmc 0x80000000>;
 591                 clock-frequency = <66666666>;
 592                 #interrupt-cells = <1>;
 593                 #size-cells = <2>;
 594                 #address-cells = <3>;
 595                 reg = <0xe0008000 0x1000>;
 596                 compatible = "fsl,mpc8540-pci";
 597                 device_type = "pci";
 598         };
 599
 600         /* PCI Express */
 601         pci1: pcie@e000a000 {
 602                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 603                 interrupt-map = <
 604
 605                         /* IDSEL 0x0 (PEX) */
 606                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 607                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 608                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 609                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 610
 611                 interrupt-parent = <&mpic>;
 612                 interrupts = <26 2>;
 613                 bus-range = <0 255>;
 614                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 615                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 616                 sleep = <&pmc 0x20000000>;
 617                 clock-frequency = <33333333>;
 618                 #interrupt-cells = <1>;
 619                 #size-cells = <2>;
 620                 #address-cells = <3>;
 621                 reg = <0xe000a000 0x1000>;
 622                 compatible = "fsl,mpc8548-pcie";
 623                 device_type = "pci";
 624                 pcie@0 {
 625                         reg = <0x0 0x0 0x0 0x0 0x0>;
 626                         #size-cells = <2>;
 627                         #address-cells = <3>;
 628                         device_type = "pci";
 629                         ranges = <0x2000000 0x0 0xa0000000
 630                                   0x2000000 0x0 0xa0000000
 631                                   0x0 0x10000000
 632
 633                                   0x1000000 0x0 0x0
 634                                   0x1000000 0x0 0x0
 635                                   0x0 0x800000>;
 636                 };
 637         };
 638
 639         rio0: rapidio@e00c00000 {
 640                 #address-cells = <2>;
 641                 #size-cells = <2>;
 642                 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
 643                 reg = <0xe00c0000 0x20000>;
 644                 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
 645                 interrupts = <48 2 /* error     */
 646                               49 2 /* bell_outb */
 647                               50 2 /* bell_inb  */
 648                               53 2 /* msg1_tx   */
 649                               54 2 /* msg1_rx   */
 650                               55 2 /* msg2_tx   */
 651                               56 2 /* msg2_rx   */>;
 652                 interrupt-parent = <&mpic>;
 653                 sleep = <&pmc 0x00080000   /* controller */
 654                          &pmc 0x00040000>; /* message unit */
 655         };
 656
 657         leds {
 658                 compatible = "gpio-leds";
 659
 660                 green {
 661                         gpios = <&bcsr5 1 0>;
 662                 };
 663
 664                 amber {
 665                         gpios = <&bcsr5 2 0>;
 666                 };
 667
 668                 red {
 669                         gpios = <&bcsr5 3 0>;
 670                 };
 671         };
 672 };