arch/powerpc/boot/dts/mpc8560ads.dts

   1 /*
   2  * MPC8560 ADS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8560ADS";
  15         compatible = "MPC8560ADS", "MPC85xxADS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #cpus = <1>;
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 PowerPC,8560@0 {
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         d-cache-line-size = <20>;       // 32 bytes
  28                         i-cache-line-size = <20>;       // 32 bytes
  29                         d-cache-size = <8000>;          // L1, 32K
  30                         i-cache-size = <8000>;          // L1, 32K
  31                         timebase-frequency = <04ead9a0>;
  32                         bus-frequency = <13ab6680>;
  33                         clock-frequency = <312c8040>;
  34                         32-bit;
  35                 };
  36         };
  37
  38         memory {
  39                 device_type = "memory";
  40                 reg = <00000000 10000000>;
  41         };
  42
  43         soc8560@e0000000 {
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46                 #interrupt-cells = <2>;
  47                 device_type = "soc";
  48                 ranges = <0 e0000000 00100000>;
  49                 reg = <e0000000 00000200>;
  50                 bus-frequency = <13ab6680>;
  51
  52                 mdio@24520 {
  53                         device_type = "mdio";
  54                         compatible = "gianfar";
  55                         reg = <24520 20>;
  56                         #address-cells = <1>;
  57                         #size-cells = <0>;
  58                         phy0: ethernet-phy@0 {
  59                                 interrupt-parent = <&mpic>;
  60                                 interrupts = <35 1>;
  61                                 reg = <0>;
  62                                 device_type = "ethernet-phy";
  63                         };
  64                         phy1: ethernet-phy@1 {
  65                                 interrupt-parent = <&mpic>;
  66                                 interrupts = <35 1>;
  67                                 reg = <1>;
  68                                 device_type = "ethernet-phy";
  69                         };
  70                         phy2: ethernet-phy@2 {
  71                                 interrupt-parent = <&mpic>;
  72                                 interrupts = <37 1>;
  73                                 reg = <2>;
  74                                 device_type = "ethernet-phy";
  75                         };
  76                         phy3: ethernet-phy@3 {
  77                                 interrupt-parent = <&mpic>;
  78                                 interrupts = <37 1>;
  79                                 reg = <3>;
  80                                 device_type = "ethernet-phy";
  81                         };
  82                 };
  83
  84                 ethernet@24000 {
  85                         device_type = "network";
  86                         model = "TSEC";
  87                         compatible = "gianfar";
  88                         reg = <24000 1000>;
  89                         address = [ 00 00 0C 00 00 FD ];
  90                         interrupts = <d 2 e 2 12 2>;
  91                         interrupt-parent = <&mpic>;
  92                         phy-handle = <&phy0>;
  93                 };
  94
  95                 ethernet@25000 {
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         device_type = "network";
  99                         model = "TSEC";
 100                         compatible = "gianfar";
 101                         reg = <25000 1000>;
 102                         address = [ 00 00 0C 00 01 FD ];
 103                         interrupts = <13 2 14 2 18 2>;
 104                         interrupt-parent = <&mpic>;
 105                         phy-handle = <&phy1>;
 106                 };
 107
 108                 pci@8000 {
 109                         #interrupt-cells = <1>;
 110                         #size-cells = <2>;
 111                         #address-cells = <3>;
 112                         compatible = "85xx";
 113                         device_type = "pci";
 114                         reg = <8000 400>;
 115                         clock-frequency = <3f940aa>;
 116                         interrupt-map-mask = <f800 0 0 7>;
 117                         interrupt-map = <
 118
 119                                         /* IDSEL 0x2 */
 120                                          1000 0 0 1 &mpic 31 1
 121                                          1000 0 0 2 &mpic 32 1
 122                                          1000 0 0 3 &mpic 33 1
 123                                          1000 0 0 4 &mpic 34 1
 124
 125                                         /* IDSEL 0x3 */
 126                                          1800 0 0 1 &mpic 34 1
 127                                          1800 0 0 2 &mpic 31 1
 128                                          1800 0 0 3 &mpic 32 1
 129                                          1800 0 0 4 &mpic 33 1
 130
 131                                         /* IDSEL 0x4 */
 132                                          2000 0 0 1 &mpic 33 1
 133                                          2000 0 0 2 &mpic 34 1
 134                                          2000 0 0 3 &mpic 31 1
 135                                          2000 0 0 4 &mpic 32 1
 136
 137                                         /* IDSEL 0x5  */
 138                                          2800 0 0 1 &mpic 32 1
 139                                          2800 0 0 2 &mpic 33 1
 140                                          2800 0 0 3 &mpic 34 1
 141                                          2800 0 0 4 &mpic 31 1
 142
 143                                         /* IDSEL 12 */
 144                                          6000 0 0 1 &mpic 31 1
 145                                          6000 0 0 2 &mpic 32 1
 146                                          6000 0 0 3 &mpic 33 1
 147                                          6000 0 0 4 &mpic 34 1
 148
 149                                         /* IDSEL 13 */
 150                                          6800 0 0 1 &mpic 34 1
 151                                          6800 0 0 2 &mpic 31 1
 152                                          6800 0 0 3 &mpic 32 1
 153                                          6800 0 0 4 &mpic 33 1
 154
 155                                         /* IDSEL 14*/
 156                                          7000 0 0 1 &mpic 33 1
 157                                          7000 0 0 2 &mpic 34 1
 158                                          7000 0 0 3 &mpic 31 1
 159                                          7000 0 0 4 &mpic 32 1
 160
 161                                         /* IDSEL 15 */
 162                                          7800 0 0 1 &mpic 32 1
 163                                          7800 0 0 2 &mpic 33 1
 164                                          7800 0 0 3 &mpic 34 1
 165                                          7800 0 0 4 &mpic 31 1
 166
 167                                         /* IDSEL 18 */
 168                                          9000 0 0 1 &mpic 31 1
 169                                          9000 0 0 2 &mpic 32 1
 170                                          9000 0 0 3 &mpic 33 1
 171                                          9000 0 0 4 &mpic 34 1
 172
 173                                         /* IDSEL 19 */
 174                                          9800 0 0 1 &mpic 34 1
 175                                          9800 0 0 2 &mpic 31 1
 176                                          9800 0 0 3 &mpic 32 1
 177                                          9800 0 0 4 &mpic 33 1
 178
 179                                         /* IDSEL 20 */
 180                                          a000 0 0 1 &mpic 33 1
 181                                          a000 0 0 2 &mpic 34 1
 182                                          a000 0 0 3 &mpic 31 1
 183                                          a000 0 0 4 &mpic 32 1
 184
 185                                         /* IDSEL 21 */
 186                                          a800 0 0 1 &mpic 32 1
 187                                          a800 0 0 2 &mpic 33 1
 188                                          a800 0 0 3 &mpic 34 1
 189                                          a800 0 0 4 &mpic 31 1>;
 190
 191                         interrupt-parent = <&mpic>;
 192                         interrupts = <8 0>;
 193                         bus-range = <0 0>;
 194                         ranges = <02000000 0 80000000 80000000 0 20000000
 195                                   01000000 0 00000000 e2000000 0 01000000>;
 196                 };
 197
 198                 mpic: pic@40000 {
 199                         interrupt-controller;
 200                         #address-cells = <0>;
 201                         #interrupt-cells = <2>;
 202                         reg = <40000 40000>;
 203                         built-in;
 204                         device_type = "open-pic";
 205                 };
 206
 207                 cpm@e0000000 {
 208                         #address-cells = <1>;
 209                         #size-cells = <1>;
 210                         #interrupt-cells = <2>;
 211                         device_type = "cpm";
 212                         model = "CPM2";
 213                         ranges = <0 0 c0000>;
 214                         reg = <80000 40000>;
 215                         command-proc = <919c0>;
 216                         brg-frequency = <9d5b340>;
 217
 218                         cpmpic: pic@90c00 {
 219                                 interrupt-controller;
 220                                 #address-cells = <0>;
 221                                 #interrupt-cells = <2>;
 222                                 interrupts = <1e 0>;
 223                                 interrupt-parent = <&mpic>;
 224                                 reg = <90c00 80>;
 225                                 built-in;
 226                                 device_type = "cpm-pic";
 227                         };
 228
 229                         scc@91a00 {
 230                                 device_type = "serial";
 231                                 compatible = "cpm_uart";
 232                                 model = "SCC";
 233                                 device-id = <1>;
 234                                 reg = <91a00 20 88000 100>;
 235                                 clock-setup = <00ffffff 0>;
 236                                 rx-clock = <1>;
 237                                 tx-clock = <1>;
 238                                 current-speed = <1c200>;
 239                                 interrupts = <28 8>;
 240                                 interrupt-parent = <&cpmpic>;
 241                         };
 242
 243                         scc@91a20 {
 244                                 device_type = "serial";
 245                                 compatible = "cpm_uart";
 246                                 model = "SCC";
 247                                 device-id = <2>;
 248                                 reg = <91a20 20 88100 100>;
 249                                 clock-setup = <ff00ffff 90000>;
 250                                 rx-clock = <2>;
 251                                 tx-clock = <2>;
 252                                 current-speed = <1c200>;
 253                                 interrupts = <29 8>;
 254                                 interrupt-parent = <&cpmpic>;
 255                         };
 256
 257                         fcc@91320 {
 258                                 device_type = "network";
 259                                 compatible = "fs_enet";
 260                                 model = "FCC";
 261                                 device-id = <2>;
 262                                 reg = <91320 20 88500 100 913a0 30>;
 263                                 mac-address = [ 00 00 0C 00 02 FD ];
 264                                 clock-setup = <ff00ffff 250000>;
 265                                 rx-clock = <15>;
 266                                 tx-clock = <16>;
 267                                 interrupts = <21 8>;
 268                                 interrupt-parent = <&cpmpic>;
 269                                 phy-handle = <&phy2>;
 270                         };
 271
 272                         fcc@91340 {
 273                                 device_type = "network";
 274                                 compatible = "fs_enet";
 275                                 model = "FCC";
 276                                 device-id = <3>;
 277                                 reg = <91340 20 88600 100 913d0 30>;
 278                                 mac-address = [ 00 00 0C 00 03 FD ];
 279                                 clock-setup = <ffff00ff 3700>;
 280                                 rx-clock = <17>;
 281                                 tx-clock = <18>;
 282                                 interrupts = <22 8>;
 283                                 interrupt-parent = <&cpmpic>;
 284                                 phy-handle = <&phy3>;
 285                         };
 286                 };
 287         };
 288 };