arch/powerpc/boot/dts/mpc8555cds.dts

   1 /*
   2  * MPC8555 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8555CDS";
  16         compatible = "MPC8555CDS", "MPC85xxCDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8555@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         d-cache-line-size = <32>;       // 32 bytes
  37                         i-cache-line-size = <32>;       // 32 bytes
  38                         d-cache-size = <0x8000>;                // L1, 32K
  39                         i-cache-size = <0x8000>;                // L1, 32K
  40                         timebase-frequency = <0>;       //  33 MHz, from uboot
  41                         bus-frequency = <0>;    // 166 MHz
  42                         clock-frequency = <0>;  // 825 MHz, from uboot
  43                         next-level-cache = <&L2>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x0 0x8000000>;  // 128M at 0x0
  50         };
  51
  52         soc8555@e0000000 {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 device_type = "soc";
  56                 ranges = <0x0 0xe0000000 0x100000>;
  57                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
  58                 bus-frequency = <0>;
  59
  60                 memory-controller@2000 {
  61                         compatible = "fsl,8555-memory-controller";
  62                         reg = <0x2000 0x1000>;
  63                         interrupt-parent = <&mpic>;
  64                         interrupts = <18 2>;
  65                 };
  66
  67                 L2: l2-cache-controller@20000 {
  68                         compatible = "fsl,8555-l2-cache-controller";
  69                         reg = <0x20000 0x1000>;
  70                         cache-line-size = <32>; // 32 bytes
  71                         cache-size = <0x40000>; // L2, 256K
  72                         interrupt-parent = <&mpic>;
  73                         interrupts = <16 2>;
  74                 };
  75
  76                 i2c@3000 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         cell-index = <0>;
  80                         compatible = "fsl-i2c";
  81                         reg = <0x3000 0x100>;
  82                         interrupts = <43 2>;
  83                         interrupt-parent = <&mpic>;
  84                         dfsrr;
  85                 };
  86
  87                 dma@21300 {
  88                         #address-cells = <1>;
  89                         #size-cells = <1>;
  90                         compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
  91                         reg = <0x21300 0x4>;
  92                         ranges = <0x0 0x21100 0x200>;
  93                         cell-index = <0>;
  94                         dma-channel@0 {
  95                                 compatible = "fsl,mpc8555-dma-channel",
  96                                                 "fsl,eloplus-dma-channel";
  97                                 reg = <0x0 0x80>;
  98                                 cell-index = <0>;
  99                                 interrupt-parent = <&mpic>;
 100                                 interrupts = <20 2>;
 101                         };
 102                         dma-channel@80 {
 103                                 compatible = "fsl,mpc8555-dma-channel",
 104                                                 "fsl,eloplus-dma-channel";
 105                                 reg = <0x80 0x80>;
 106                                 cell-index = <1>;
 107                                 interrupt-parent = <&mpic>;
 108                                 interrupts = <21 2>;
 109                         };
 110                         dma-channel@100 {
 111                                 compatible = "fsl,mpc8555-dma-channel",
 112                                                 "fsl,eloplus-dma-channel";
 113                                 reg = <0x100 0x80>;
 114                                 cell-index = <2>;
 115                                 interrupt-parent = <&mpic>;
 116                                 interrupts = <22 2>;
 117                         };
 118                         dma-channel@180 {
 119                                 compatible = "fsl,mpc8555-dma-channel",
 120                                                 "fsl,eloplus-dma-channel";
 121                                 reg = <0x180 0x80>;
 122                                 cell-index = <3>;
 123                                 interrupt-parent = <&mpic>;
 124                                 interrupts = <23 2>;
 125                         };
 126                 };
 127
 128                 mdio@24520 {
 129                         #address-cells = <1>;
 130                         #size-cells = <0>;
 131                         compatible = "fsl,gianfar-mdio";
 132                         reg = <0x24520 0x20>;
 133
 134                         phy0: ethernet-phy@0 {
 135                                 interrupt-parent = <&mpic>;
 136                                 interrupts = <5 1>;
 137                                 reg = <0x0>;
 138                                 device_type = "ethernet-phy";
 139                         };
 140                         phy1: ethernet-phy@1 {
 141                                 interrupt-parent = <&mpic>;
 142                                 interrupts = <5 1>;
 143                                 reg = <0x1>;
 144                                 device_type = "ethernet-phy";
 145                         };
 146                 };
 147
 148                 enet0: ethernet@24000 {
 149                         cell-index = <0>;
 150                         device_type = "network";
 151                         model = "TSEC";
 152                         compatible = "gianfar";
 153                         reg = <0x24000 0x1000>;
 154                         local-mac-address = [ 00 00 00 00 00 00 ];
 155                         interrupts = <29 2 30 2 34 2>;
 156                         interrupt-parent = <&mpic>;
 157                         phy-handle = <&phy0>;
 158                 };
 159
 160                 enet1: ethernet@25000 {
 161                         cell-index = <1>;
 162                         device_type = "network";
 163                         model = "TSEC";
 164                         compatible = "gianfar";
 165                         reg = <0x25000 0x1000>;
 166                         local-mac-address = [ 00 00 00 00 00 00 ];
 167                         interrupts = <35 2 36 2 40 2>;
 168                         interrupt-parent = <&mpic>;
 169                         phy-handle = <&phy1>;
 170                 };
 171
 172                 serial0: serial@4500 {
 173                         cell-index = <0>;
 174                         device_type = "serial";
 175                         compatible = "ns16550";
 176                         reg = <0x4500 0x100>;   // reg base, size
 177                         clock-frequency = <0>;  // should we fill in in uboot?
 178                         interrupts = <42 2>;
 179                         interrupt-parent = <&mpic>;
 180                 };
 181
 182                 serial1: serial@4600 {
 183                         cell-index = <1>;
 184                         device_type = "serial";
 185                         compatible = "ns16550";
 186                         reg = <0x4600 0x100>;   // reg base, size
 187                         clock-frequency = <0>;  // should we fill in in uboot?
 188                         interrupts = <42 2>;
 189                         interrupt-parent = <&mpic>;
 190                 };
 191
 192                 crypto@30000 {
 193                         compatible = "fsl,sec2.0";
 194                         reg = <0x30000 0x10000>;
 195                         interrupts = <45 2>;
 196                         interrupt-parent = <&mpic>;
 197                         fsl,num-channels = <4>;
 198                         fsl,channel-fifo-len = <24>;
 199                         fsl,exec-units-mask = <0x7e>;
 200                         fsl,descriptor-types-mask = <0x01010ebf>;
 201                 };
 202
 203                 mpic: pic@40000 {
 204                         interrupt-controller;
 205                         #address-cells = <0>;
 206                         #interrupt-cells = <2>;
 207                         reg = <0x40000 0x40000>;
 208                         compatible = "chrp,open-pic";
 209                         device_type = "open-pic";
 210                 };
 211
 212                 cpm@919c0 {
 213                         #address-cells = <1>;
 214                         #size-cells = <1>;
 215                         compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
 216                         reg = <0x919c0 0x30>;
 217                         ranges;
 218
 219                         muram@80000 {
 220                                 #address-cells = <1>;
 221                                 #size-cells = <1>;
 222                                 ranges = <0x0 0x80000 0x10000>;
 223
 224                                 data@0 {
 225                                         compatible = "fsl,cpm-muram-data";
 226                                         reg = <0x0 0x2000 0x9000 0x1000>;
 227                                 };
 228                         };
 229
 230                         brg@919f0 {
 231                                 compatible = "fsl,mpc8555-brg",
 232                                              "fsl,cpm2-brg",
 233                                              "fsl,cpm-brg";
 234                                 reg = <0x919f0 0x10 0x915f0 0x10>;
 235                         };
 236
 237                         cpmpic: pic@90c00 {
 238                                 interrupt-controller;
 239                                 #address-cells = <0>;
 240                                 #interrupt-cells = <2>;
 241                                 interrupts = <46 2>;
 242                                 interrupt-parent = <&mpic>;
 243                                 reg = <0x90c00 0x80>;
 244                                 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
 245                         };
 246                 };
 247         };
 248
 249         pci0: pci@e0008000 {
 250                 cell-index = <0>;
 251                 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
 252                 interrupt-map = <
 253
 254                         /* IDSEL 0x10 */
 255                         0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
 256                         0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
 257                         0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
 258                         0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
 259
 260                         /* IDSEL 0x11 */
 261                         0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
 262                         0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
 263                         0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
 264                         0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
 265
 266                         /* IDSEL 0x12 (Slot 1) */
 267                         0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
 268                         0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
 269                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 270                         0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
 271
 272                         /* IDSEL 0x13 (Slot 2) */
 273                         0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
 274                         0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
 275                         0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
 276                         0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
 277
 278                         /* IDSEL 0x14 (Slot 3) */
 279                         0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
 280                         0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
 281                         0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
 282                         0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
 283
 284                         /* IDSEL 0x15 (Slot 4) */
 285                         0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
 286                         0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
 287                         0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
 288                         0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
 289
 290                         /* Bus 1 (Tundra Bridge) */
 291                         /* IDSEL 0x12 (ISA bridge) */
 292                         0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
 293                         0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
 294                         0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
 295                         0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 296                 interrupt-parent = <&mpic>;
 297                 interrupts = <24 2>;
 298                 bus-range = <0 0>;
 299                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 300                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
 301                 clock-frequency = <66666666>;
 302                 #interrupt-cells = <1>;
 303                 #size-cells = <2>;
 304                 #address-cells = <3>;
 305                 reg = <0xe0008000 0x1000>;
 306                 compatible = "fsl,mpc8540-pci";
 307                 device_type = "pci";
 308
 309                 i8259@19000 {
 310                         interrupt-controller;
 311                         device_type = "interrupt-controller";
 312                         reg = <0x19000 0x0 0x0 0x0 0x1>;
 313                         #address-cells = <0>;
 314                         #interrupt-cells = <2>;
 315                         compatible = "chrp,iic";
 316                         interrupts = <1>;
 317                         interrupt-parent = <&pci0>;
 318                 };
 319         };
 320
 321         pci1: pci@e0009000 {
 322                 cell-index = <1>;
 323                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 324                 interrupt-map = <
 325
 326                         /* IDSEL 0x15 */
 327                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 328                         0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
 329                         0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
 330                         0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
 331                 interrupt-parent = <&mpic>;
 332                 interrupts = <25 2>;
 333                 bus-range = <0 0>;
 334                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 335                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 336                 clock-frequency = <66666666>;
 337                 #interrupt-cells = <1>;
 338                 #size-cells = <2>;
 339                 #address-cells = <3>;
 340                 reg = <0xe0009000 0x1000>;
 341                 compatible = "fsl,mpc8540-pci";
 342                 device_type = "pci";
 343         };
 344 };