arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8548CDS";
  15         compatible = "MPC8548CDS", "MPC85xxCDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22 /*
  23                 ethernet2 = &enet2;
  24                 ethernet3 = &enet3;
  25 */
  26                 serial0 = &serial0;
  27                 serial1 = &serial1;
  28                 pci0 = &pci0;
  29                 pci1 = &pci1;
  30                 pci2 = &pci2;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 PowerPC,8548@0 {
  38                         device_type = "cpu";
  39                         reg = <0>;
  40                         d-cache-line-size = <20>;       // 32 bytes
  41                         i-cache-line-size = <20>;       // 32 bytes
  42                         d-cache-size = <8000>;          // L1, 32K
  43                         i-cache-size = <8000>;          // L1, 32K
  44                         timebase-frequency = <0>;       //  33 MHz, from uboot
  45                         bus-frequency = <0>;    // 166 MHz
  46                         clock-frequency = <0>;  // 825 MHz, from uboot
  47                 };
  48         };
  49
  50         memory {
  51                 device_type = "memory";
  52                 reg = <00000000 08000000>;      // 128M at 0x0
  53         };
  54
  55         soc8548@e0000000 {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 device_type = "soc";
  59                 ranges = <00000000 e0000000 00100000>;
  60                 reg = <e0000000 00001000>;      // CCSRBAR
  61                 bus-frequency = <0>;
  62
  63                 memory-controller@2000 {
  64                         compatible = "fsl,8548-memory-controller";
  65                         reg = <2000 1000>;
  66                         interrupt-parent = <&mpic>;
  67                         interrupts = <12 2>;
  68                 };
  69
  70                 l2-cache-controller@20000 {
  71                         compatible = "fsl,8548-l2-cache-controller";
  72                         reg = <20000 1000>;
  73                         cache-line-size = <20>; // 32 bytes
  74                         cache-size = <80000>;   // L2, 512K
  75                         interrupt-parent = <&mpic>;
  76                         interrupts = <10 2>;
  77                 };
  78
  79                 i2c@3000 {
  80                         #address-cells = <1>;
  81                         #size-cells = <0>;
  82                         cell-index = <0>;
  83                         compatible = "fsl-i2c";
  84                         reg = <3000 100>;
  85                         interrupts = <2b 2>;
  86                         interrupt-parent = <&mpic>;
  87                         dfsrr;
  88                 };
  89
  90                 i2c@3100 {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93                         cell-index = <1>;
  94                         compatible = "fsl-i2c";
  95                         reg = <3100 100>;
  96                         interrupts = <2b 2>;
  97                         interrupt-parent = <&mpic>;
  98                         dfsrr;
  99                 };
 100
 101                 mdio@24520 {
 102                         #address-cells = <1>;
 103                         #size-cells = <0>;
 104                         compatible = "fsl,gianfar-mdio";
 105                         reg = <24520 20>;
 106
 107                         phy0: ethernet-phy@0 {
 108                                 interrupt-parent = <&mpic>;
 109                                 interrupts = <5 1>;
 110                                 reg = <0>;
 111                                 device_type = "ethernet-phy";
 112                         };
 113                         phy1: ethernet-phy@1 {
 114                                 interrupt-parent = <&mpic>;
 115                                 interrupts = <5 1>;
 116                                 reg = <1>;
 117                                 device_type = "ethernet-phy";
 118                         };
 119                         phy2: ethernet-phy@2 {
 120                                 interrupt-parent = <&mpic>;
 121                                 interrupts = <5 1>;
 122                                 reg = <2>;
 123                                 device_type = "ethernet-phy";
 124                         };
 125                         phy3: ethernet-phy@3 {
 126                                 interrupt-parent = <&mpic>;
 127                                 interrupts = <5 1>;
 128                                 reg = <3>;
 129                                 device_type = "ethernet-phy";
 130                         };
 131                 };
 132
 133                 enet0: ethernet@24000 {
 134                         cell-index = <0>;
 135                         device_type = "network";
 136                         model = "eTSEC";
 137                         compatible = "gianfar";
 138                         reg = <24000 1000>;
 139                         local-mac-address = [ 00 00 00 00 00 00 ];
 140                         interrupts = <1d 2 1e 2 22 2>;
 141                         interrupt-parent = <&mpic>;
 142                         phy-handle = <&phy0>;
 143                 };
 144
 145                 enet1: ethernet@25000 {
 146                         cell-index = <1>;
 147                         device_type = "network";
 148                         model = "eTSEC";
 149                         compatible = "gianfar";
 150                         reg = <25000 1000>;
 151                         local-mac-address = [ 00 00 00 00 00 00 ];
 152                         interrupts = <23 2 24 2 28 2>;
 153                         interrupt-parent = <&mpic>;
 154                         phy-handle = <&phy1>;
 155                 };
 156
 157 /* eTSEC 3/4 are currently broken
 158                 enet2: ethernet@26000 {
 159                         cell-index = <2>;
 160                         device_type = "network";
 161                         model = "eTSEC";
 162                         compatible = "gianfar";
 163                         reg = <26000 1000>;
 164                         local-mac-address = [ 00 00 00 00 00 00 ];
 165                         interrupts = <1f 2 20 2 21 2>;
 166                         interrupt-parent = <&mpic>;
 167                         phy-handle = <&phy2>;
 168                 };
 169
 170                 enet3: ethernet@27000 {
 171                         cell-index = <3>;
 172                         device_type = "network";
 173                         model = "eTSEC";
 174                         compatible = "gianfar";
 175                         reg = <27000 1000>;
 176                         local-mac-address = [ 00 00 00 00 00 00 ];
 177                         interrupts = <25 2 26 2 27 2>;
 178                         interrupt-parent = <&mpic>;
 179                         phy-handle = <&phy3>;
 180                 };
 181  */
 182
 183                 serial0: serial@4500 {
 184                         cell-index = <0>;
 185                         device_type = "serial";
 186                         compatible = "ns16550";
 187                         reg = <4500 100>;       // reg base, size
 188                         clock-frequency = <0>;  // should we fill in in uboot?
 189                         interrupts = <2a 2>;
 190                         interrupt-parent = <&mpic>;
 191                 };
 192
 193                 serial1: serial@4600 {
 194                         cell-index = <1>;
 195                         device_type = "serial";
 196                         compatible = "ns16550";
 197                         reg = <4600 100>;       // reg base, size
 198                         clock-frequency = <0>;  // should we fill in in uboot?
 199                         interrupts = <2a 2>;
 200                         interrupt-parent = <&mpic>;
 201                 };
 202
 203                 global-utilities@e0000 {        //global utilities reg
 204                         compatible = "fsl,mpc8548-guts";
 205                         reg = <e0000 1000>;
 206                         fsl,has-rstcr;
 207                 };
 208
 209                 mpic: pic@40000 {
 210                         clock-frequency = <0>;
 211                         interrupt-controller;
 212                         #address-cells = <0>;
 213                         #interrupt-cells = <2>;
 214                         reg = <40000 40000>;
 215                         compatible = "chrp,open-pic";
 216                         device_type = "open-pic";
 217                         big-endian;
 218                 };
 219         };
 220
 221         pci0: pci@e0008000 {
 222                 cell-index = <0>;
 223                 interrupt-map-mask = <f800 0 0 7>;
 224                 interrupt-map = <
 225                         /* IDSEL 0x4 (PCIX Slot 2) */
 226                         02000 0 0 1 &mpic 0 1
 227                         02000 0 0 2 &mpic 1 1
 228                         02000 0 0 3 &mpic 2 1
 229                         02000 0 0 4 &mpic 3 1
 230
 231                         /* IDSEL 0x5 (PCIX Slot 3) */
 232                         02800 0 0 1 &mpic 1 1
 233                         02800 0 0 2 &mpic 2 1
 234                         02800 0 0 3 &mpic 3 1
 235                         02800 0 0 4 &mpic 0 1
 236
 237                         /* IDSEL 0x6 (PCIX Slot 4) */
 238                         03000 0 0 1 &mpic 2 1
 239                         03000 0 0 2 &mpic 3 1
 240                         03000 0 0 3 &mpic 0 1
 241                         03000 0 0 4 &mpic 1 1
 242
 243                         /* IDSEL 0x8 (PCIX Slot 5) */
 244                         04000 0 0 1 &mpic 0 1
 245                         04000 0 0 2 &mpic 1 1
 246                         04000 0 0 3 &mpic 2 1
 247                         04000 0 0 4 &mpic 3 1
 248
 249                         /* IDSEL 0xC (Tsi310 bridge) */
 250                         06000 0 0 1 &mpic 0 1
 251                         06000 0 0 2 &mpic 1 1
 252                         06000 0 0 3 &mpic 2 1
 253                         06000 0 0 4 &mpic 3 1
 254
 255                         /* IDSEL 0x14 (Slot 2) */
 256                         0a000 0 0 1 &mpic 0 1
 257                         0a000 0 0 2 &mpic 1 1
 258                         0a000 0 0 3 &mpic 2 1
 259                         0a000 0 0 4 &mpic 3 1
 260
 261                         /* IDSEL 0x15 (Slot 3) */
 262                         0a800 0 0 1 &mpic 1 1
 263                         0a800 0 0 2 &mpic 2 1
 264                         0a800 0 0 3 &mpic 3 1
 265                         0a800 0 0 4 &mpic 0 1
 266
 267                         /* IDSEL 0x16 (Slot 4) */
 268                         0b000 0 0 1 &mpic 2 1
 269                         0b000 0 0 2 &mpic 3 1
 270                         0b000 0 0 3 &mpic 0 1
 271                         0b000 0 0 4 &mpic 1 1
 272
 273                         /* IDSEL 0x18 (Slot 5) */
 274                         0c000 0 0 1 &mpic 0 1
 275                         0c000 0 0 2 &mpic 1 1
 276                         0c000 0 0 3 &mpic 2 1
 277                         0c000 0 0 4 &mpic 3 1
 278
 279                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 280                         0E000 0 0 1 &mpic 0 1
 281                         0E000 0 0 2 &mpic 1 1
 282                         0E000 0 0 3 &mpic 2 1
 283                         0E000 0 0 4 &mpic 3 1>;
 284
 285                 interrupt-parent = <&mpic>;
 286                 interrupts = <18 2>;
 287                 bus-range = <0 0>;
 288                 ranges = <02000000 0 80000000 80000000 0 10000000
 289                           01000000 0 00000000 e2000000 0 00800000>;
 290                 clock-frequency = <3f940aa>;
 291                 #interrupt-cells = <1>;
 292                 #size-cells = <2>;
 293                 #address-cells = <3>;
 294                 reg = <e0008000 1000>;
 295                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 296                 device_type = "pci";
 297
 298                 pci_bridge@1c {
 299                         interrupt-map-mask = <f800 0 0 7>;
 300                         interrupt-map = <
 301
 302                                 /* IDSEL 0x00 (PrPMC Site) */
 303                                 0000 0 0 1 &mpic 0 1
 304                                 0000 0 0 2 &mpic 1 1
 305                                 0000 0 0 3 &mpic 2 1
 306                                 0000 0 0 4 &mpic 3 1
 307
 308                                 /* IDSEL 0x04 (VIA chip) */
 309                                 2000 0 0 1 &mpic 0 1
 310                                 2000 0 0 2 &mpic 1 1
 311                                 2000 0 0 3 &mpic 2 1
 312                                 2000 0 0 4 &mpic 3 1
 313
 314                                 /* IDSEL 0x05 (8139) */
 315                                 2800 0 0 1 &mpic 1 1
 316
 317                                 /* IDSEL 0x06 (Slot 6) */
 318                                 3000 0 0 1 &mpic 2 1
 319                                 3000 0 0 2 &mpic 3 1
 320                                 3000 0 0 3 &mpic 0 1
 321                                 3000 0 0 4 &mpic 1 1
 322
 323                                 /* IDESL 0x07 (Slot 7) */
 324                                 3800 0 0 1 &mpic 3 1
 325                                 3800 0 0 2 &mpic 0 1
 326                                 3800 0 0 3 &mpic 1 1
 327                                 3800 0 0 4 &mpic 2 1>;
 328
 329                         reg = <e000 0 0 0 0>;
 330                         #interrupt-cells = <1>;
 331                         #size-cells = <2>;
 332                         #address-cells = <3>;
 333                         ranges = <02000000 0 80000000
 334                                   02000000 0 80000000
 335                                   0 20000000
 336                                   01000000 0 00000000
 337                                   01000000 0 00000000
 338                                   0 00080000>;
 339                         clock-frequency = <1fca055>;
 340
 341                         isa@4 {
 342                                 device_type = "isa";
 343                                 #interrupt-cells = <2>;
 344                                 #size-cells = <1>;
 345                                 #address-cells = <2>;
 346                                 reg = <2000 0 0 0 0>;
 347                                 ranges = <1 0 01000000 0 0 00001000>;
 348                                 interrupt-parent = <&i8259>;
 349
 350                                 i8259: interrupt-controller@20 {
 351                                         interrupt-controller;
 352                                         device_type = "interrupt-controller";
 353                                         reg = <1 20 2
 354                                                1 a0 2
 355                                                1 4d0 2>;
 356                                         #address-cells = <0>;
 357                                         #interrupt-cells = <2>;
 358                                         compatible = "chrp,iic";
 359                                         interrupts = <0 1>;
 360                                         interrupt-parent = <&mpic>;
 361                                 };
 362
 363                                 rtc@70 {
 364                                         compatible = "pnpPNP,b00";
 365                                         reg = <1 70 2>;
 366                                 };
 367                         };
 368                 };
 369         };
 370
 371         pci1: pci@e0009000 {
 372                 cell-index = <1>;
 373                 interrupt-map-mask = <f800 0 0 7>;
 374                 interrupt-map = <
 375
 376                         /* IDSEL 0x15 */
 377                         a800 0 0 1 &mpic b 1
 378                         a800 0 0 2 &mpic 1 1
 379                         a800 0 0 3 &mpic 2 1
 380                         a800 0 0 4 &mpic 3 1>;
 381
 382                 interrupt-parent = <&mpic>;
 383                 interrupts = <19 2>;
 384                 bus-range = <0 0>;
 385                 ranges = <02000000 0 90000000 90000000 0 10000000
 386                           01000000 0 00000000 e2800000 0 00800000>;
 387                 clock-frequency = <3f940aa>;
 388                 #interrupt-cells = <1>;
 389                 #size-cells = <2>;
 390                 #address-cells = <3>;
 391                 reg = <e0009000 1000>;
 392                 compatible = "fsl,mpc8540-pci";
 393                 device_type = "pci";
 394         };
 395
 396         pci2: pcie@e000a000 {
 397                 cell-index = <2>;
 398                 interrupt-map-mask = <f800 0 0 7>;
 399                 interrupt-map = <
 400
 401                         /* IDSEL 0x0 (PEX) */
 402                         00000 0 0 1 &mpic 0 1
 403                         00000 0 0 2 &mpic 1 1
 404                         00000 0 0 3 &mpic 2 1
 405                         00000 0 0 4 &mpic 3 1>;
 406
 407                 interrupt-parent = <&mpic>;
 408                 interrupts = <1a 2>;
 409                 bus-range = <0 ff>;
 410                 ranges = <02000000 0 a0000000 a0000000 0 20000000
 411                           01000000 0 00000000 e3000000 0 08000000>;
 412                 clock-frequency = <1fca055>;
 413                 #interrupt-cells = <1>;
 414                 #size-cells = <2>;
 415                 #address-cells = <3>;
 416                 reg = <e000a000 1000>;
 417                 compatible = "fsl,mpc8548-pcie";
 418                 device_type = "pci";
 419                 pcie@0 {
 420                         reg = <0 0 0 0 0>;
 421                         #size-cells = <2>;
 422                         #address-cells = <3>;
 423                         device_type = "pci";
 424                         ranges = <02000000 0 a0000000
 425                                   02000000 0 a0000000
 426                                   0 20000000
 427
 428                                   01000000 0 00000000
 429                                   01000000 0 00000000
 430                                   0 08000000>;
 431                 };
 432         };
 433 };