arch/powerpc/boot/dts/mpc8544ds.dts

   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "MPC8544DS";
  15         compatible = "MPC8544DS", "MPC85xxDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27                 pci3 = &pci3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8544@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;       // 32 bytes
  38                         i-cache-line-size = <32>;       // 32 bytes
  39                         d-cache-size = <0x8000>;                // L1, 32K
  40                         i-cache-size = <0x8000>;                // L1, 32K
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x0 0x0>;        // Filled by U-Boot
  51         };
  52
  53         soc8544@e0000000 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 device_type = "soc";
  57                 compatible = "simple-bus";
  58
  59                 ranges = <0x0 0xe0000000 0x100000>;
  60                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
  61                 bus-frequency = <0>;            // Filled out by uboot.
  62
  63                 memory-controller@2000 {
  64                         compatible = "fsl,8544-memory-controller";
  65                         reg = <0x2000 0x1000>;
  66                         interrupt-parent = <&mpic>;
  67                         interrupts = <18 2>;
  68                 };
  69
  70                 L2: l2-cache-controller@20000 {
  71                         compatible = "fsl,8544-l2-cache-controller";
  72                         reg = <0x20000 0x1000>;
  73                         cache-line-size = <32>; // 32 bytes
  74                         cache-size = <0x40000>; // L2, 256K
  75                         interrupt-parent = <&mpic>;
  76                         interrupts = <16 2>;
  77                 };
  78
  79                 i2c@3000 {
  80                         #address-cells = <1>;
  81                         #size-cells = <0>;
  82                         cell-index = <0>;
  83                         compatible = "fsl-i2c";
  84                         reg = <0x3000 0x100>;
  85                         interrupts = <43 2>;
  86                         interrupt-parent = <&mpic>;
  87                         dfsrr;
  88                 };
  89
  90                 i2c@3100 {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93                         cell-index = <1>;
  94                         compatible = "fsl-i2c";
  95                         reg = <0x3100 0x100>;
  96                         interrupts = <43 2>;
  97                         interrupt-parent = <&mpic>;
  98                         dfsrr;
  99                 };
 100
 101                 mdio@24520 {
 102                         #address-cells = <1>;
 103                         #size-cells = <0>;
 104                         compatible = "fsl,gianfar-mdio";
 105                         reg = <0x24520 0x20>;
 106
 107                         phy0: ethernet-phy@0 {
 108                                 interrupt-parent = <&mpic>;
 109                                 interrupts = <10 1>;
 110                                 reg = <0x0>;
 111                                 device_type = "ethernet-phy";
 112                         };
 113                         phy1: ethernet-phy@1 {
 114                                 interrupt-parent = <&mpic>;
 115                                 interrupts = <10 1>;
 116                                 reg = <0x1>;
 117                                 device_type = "ethernet-phy";
 118                         };
 119                 };
 120
 121                 dma@21300 {
 122                         #address-cells = <1>;
 123                         #size-cells = <1>;
 124                         compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
 125                         reg = <0x21300 0x4>;
 126                         ranges = <0x0 0x21100 0x200>;
 127                         cell-index = <0>;
 128                         dma-channel@0 {
 129                                 compatible = "fsl,mpc8544-dma-channel",
 130                                                 "fsl,eloplus-dma-channel";
 131                                 reg = <0x0 0x80>;
 132                                 cell-index = <0>;
 133                                 interrupt-parent = <&mpic>;
 134                                 interrupts = <20 2>;
 135                         };
 136                         dma-channel@80 {
 137                                 compatible = "fsl,mpc8544-dma-channel",
 138                                                 "fsl,eloplus-dma-channel";
 139                                 reg = <0x80 0x80>;
 140                                 cell-index = <1>;
 141                                 interrupt-parent = <&mpic>;
 142                                 interrupts = <21 2>;
 143                         };
 144                         dma-channel@100 {
 145                                 compatible = "fsl,mpc8544-dma-channel",
 146                                                 "fsl,eloplus-dma-channel";
 147                                 reg = <0x100 0x80>;
 148                                 cell-index = <2>;
 149                                 interrupt-parent = <&mpic>;
 150                                 interrupts = <22 2>;
 151                         };
 152                         dma-channel@180 {
 153                                 compatible = "fsl,mpc8544-dma-channel",
 154                                                 "fsl,eloplus-dma-channel";
 155                                 reg = <0x180 0x80>;
 156                                 cell-index = <3>;
 157                                 interrupt-parent = <&mpic>;
 158                                 interrupts = <23 2>;
 159                         };
 160                 };
 161
 162                 enet0: ethernet@24000 {
 163                         cell-index = <0>;
 164                         device_type = "network";
 165                         model = "TSEC";
 166                         compatible = "gianfar";
 167                         reg = <0x24000 0x1000>;
 168                         local-mac-address = [ 00 00 00 00 00 00 ];
 169                         interrupts = <29 2 30 2 34 2>;
 170                         interrupt-parent = <&mpic>;
 171                         phy-handle = <&phy0>;
 172                         phy-connection-type = "rgmii-id";
 173                 };
 174
 175                 enet1: ethernet@26000 {
 176                         cell-index = <1>;
 177                         device_type = "network";
 178                         model = "TSEC";
 179                         compatible = "gianfar";
 180                         reg = <0x26000 0x1000>;
 181                         local-mac-address = [ 00 00 00 00 00 00 ];
 182                         interrupts = <31 2 32 2 33 2>;
 183                         interrupt-parent = <&mpic>;
 184                         phy-handle = <&phy1>;
 185                         phy-connection-type = "rgmii-id";
 186                 };
 187
 188                 serial0: serial@4500 {
 189                         cell-index = <0>;
 190                         device_type = "serial";
 191                         compatible = "ns16550";
 192                         reg = <0x4500 0x100>;
 193                         clock-frequency = <0>;
 194                         interrupts = <42 2>;
 195                         interrupt-parent = <&mpic>;
 196                 };
 197
 198                 serial1: serial@4600 {
 199                         cell-index = <1>;
 200                         device_type = "serial";
 201                         compatible = "ns16550";
 202                         reg = <0x4600 0x100>;
 203                         clock-frequency = <0>;
 204                         interrupts = <42 2>;
 205                         interrupt-parent = <&mpic>;
 206                 };
 207
 208                 global-utilities@e0000 {        //global utilities block
 209                         compatible = "fsl,mpc8548-guts";
 210                         reg = <0xe0000 0x1000>;
 211                         fsl,has-rstcr;
 212                 };
 213
 214                 crypto@30000 {
 215                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 216                         reg = <0x30000 0x10000>;
 217                         interrupts = <45 2>;
 218                         interrupt-parent = <&mpic>;
 219                         fsl,num-channels = <4>;
 220                         fsl,channel-fifo-len = <24>;
 221                         fsl,exec-units-mask = <0xfe>;
 222                         fsl,descriptor-types-mask = <0x12b0ebf>;
 223                 };
 224
 225                 mpic: pic@40000 {
 226                         interrupt-controller;
 227                         #address-cells = <0>;
 228                         #interrupt-cells = <2>;
 229                         reg = <0x40000 0x40000>;
 230                         compatible = "chrp,open-pic";
 231                         device_type = "open-pic";
 232                 };
 233
 234                 msi@41600 {
 235                         compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
 236                         reg = <0x41600 0x80>;
 237                         msi-available-ranges = <0 0x100>;
 238                         interrupts = <
 239                                 0xe0 0
 240                                 0xe1 0
 241                                 0xe2 0
 242                                 0xe3 0
 243                                 0xe4 0
 244                                 0xe5 0
 245                                 0xe6 0
 246                                 0xe7 0>;
 247                         interrupt-parent = <&mpic>;
 248                 };
 249         };
 250
 251         pci0: pci@e0008000 {
 252                 cell-index = <0>;
 253                 compatible = "fsl,mpc8540-pci";
 254                 device_type = "pci";
 255                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 256                 interrupt-map = <
 257
 258                         /* IDSEL 0x11 J17 Slot 1 */
 259                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 260                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 261                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 262                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 263
 264                         /* IDSEL 0x12 J16 Slot 2 */
 265
 266                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
 267                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
 268                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 269                         0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
 270
 271                 interrupt-parent = <&mpic>;
 272                 interrupts = <24 2>;
 273                 bus-range = <0 255>;
 274                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 275                           0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
 276                 clock-frequency = <66666666>;
 277                 #interrupt-cells = <1>;
 278                 #size-cells = <2>;
 279                 #address-cells = <3>;
 280                 reg = <0xe0008000 0x1000>;
 281         };
 282
 283         pci1: pcie@e0009000 {
 284                 cell-index = <1>;
 285                 compatible = "fsl,mpc8548-pcie";
 286                 device_type = "pci";
 287                 #interrupt-cells = <1>;
 288                 #size-cells = <2>;
 289                 #address-cells = <3>;
 290                 reg = <0xe0009000 0x1000>;
 291                 bus-range = <0 255>;
 292                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 293                           0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
 294                 clock-frequency = <33333333>;
 295                 interrupt-parent = <&mpic>;
 296                 interrupts = <26 2>;
 297                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 298                 interrupt-map = <
 299                         /* IDSEL 0x0 */
 300                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
 301                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
 302                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
 303                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
 304                         >;
 305                 pcie@0 {
 306                         reg = <0x0 0x0 0x0 0x0 0x0>;
 307                         #size-cells = <2>;
 308                         #address-cells = <3>;
 309                         device_type = "pci";
 310                         ranges = <0x2000000 0x0 0x80000000
 311                                   0x2000000 0x0 0x80000000
 312                                   0x0 0x20000000
 313
 314                                   0x1000000 0x0 0x0
 315                                   0x1000000 0x0 0x0
 316                                   0x0 0x10000>;
 317                 };
 318         };
 319
 320         pci2: pcie@e000a000 {
 321                 cell-index = <2>;
 322                 compatible = "fsl,mpc8548-pcie";
 323                 device_type = "pci";
 324                 #interrupt-cells = <1>;
 325                 #size-cells = <2>;
 326                 #address-cells = <3>;
 327                 reg = <0xe000a000 0x1000>;
 328                 bus-range = <0 255>;
 329                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 330                           0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
 331                 clock-frequency = <33333333>;
 332                 interrupt-parent = <&mpic>;
 333                 interrupts = <25 2>;
 334                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 335                 interrupt-map = <
 336                         /* IDSEL 0x0 */
 337                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 338                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 339                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 340                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 341                         >;
 342                 pcie@0 {
 343                         reg = <0x0 0x0 0x0 0x0 0x0>;
 344                         #size-cells = <2>;
 345                         #address-cells = <3>;
 346                         device_type = "pci";
 347                         ranges = <0x2000000 0x0 0xa0000000
 348                                   0x2000000 0x0 0xa0000000
 349                                   0x0 0x10000000
 350
 351                                   0x1000000 0x0 0x0
 352                                   0x1000000 0x0 0x0
 353                                   0x0 0x10000>;
 354                 };
 355         };
 356
 357         pci3: pcie@e000b000 {
 358                 cell-index = <3>;
 359                 compatible = "fsl,mpc8548-pcie";
 360                 device_type = "pci";
 361                 #interrupt-cells = <1>;
 362                 #size-cells = <2>;
 363                 #address-cells = <3>;
 364                 reg = <0xe000b000 0x1000>;
 365                 bus-range = <0 255>;
 366                 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
 367                           0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
 368                 clock-frequency = <33333333>;
 369                 interrupt-parent = <&mpic>;
 370                 interrupts = <27 2>;
 371                 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
 372                 interrupt-map = <
 373                         // IDSEL 0x1c  USB
 374                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 375                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 376                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 377                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 378
 379                         // IDSEL 0x1d  Audio
 380                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 381
 382                         // IDSEL 0x1e Legacy
 383                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 384                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 385
 386                         // IDSEL 0x1f IDE/SATA
 387                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 388                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 389                 >;
 390
 391                 pcie@0 {
 392                         reg = <0x0 0x0 0x0 0x0 0x0>;
 393                         #size-cells = <2>;
 394                         #address-cells = <3>;
 395                         device_type = "pci";
 396                         ranges = <0x2000000 0x0 0xb0000000
 397                                   0x2000000 0x0 0xb0000000
 398                                   0x0 0x100000
 399
 400                                   0x1000000 0x0 0x0
 401                                   0x1000000 0x0 0x0
 402                                   0x0 0x100000>;
 403
 404                         uli1575@0 {
 405                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 406                                 #size-cells = <2>;
 407                                 #address-cells = <3>;
 408                                 ranges = <0x2000000 0x0 0xb0000000
 409                                           0x2000000 0x0 0xb0000000
 410                                           0x0 0x100000
 411
 412                                           0x1000000 0x0 0x0
 413                                           0x1000000 0x0 0x0
 414                                           0x0 0x100000>;
 415                                 isa@1e {
 416                                         device_type = "isa";
 417                                         #interrupt-cells = <2>;
 418                                         #size-cells = <1>;
 419                                         #address-cells = <2>;
 420                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 421                                         ranges = <0x1 0x0
 422                                                   0x1000000 0x0 0x0
 423                                                   0x1000>;
 424                                         interrupt-parent = <&i8259>;
 425
 426                                         i8259: interrupt-controller@20 {
 427                                                 reg = <0x1 0x20 0x2
 428                                                        0x1 0xa0 0x2
 429                                                        0x1 0x4d0 0x2>;
 430                                                 interrupt-controller;
 431                                                 device_type = "interrupt-controller";
 432                                                 #address-cells = <0>;
 433                                                 #interrupt-cells = <2>;
 434                                                 compatible = "chrp,iic";
 435                                                 interrupts = <9 2>;
 436                                                 interrupt-parent = <&mpic>;
 437                                         };
 438
 439                                         i8042@60 {
 440                                                 #size-cells = <0>;
 441                                                 #address-cells = <1>;
 442                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 443                                                 interrupts = <1 3 12 3>;
 444                                                 interrupt-parent = <&i8259>;
 445
 446                                                 keyboard@0 {
 447                                                         reg = <0x0>;
 448                                                         compatible = "pnpPNP,303";
 449                                                 };
 450
 451                                                 mouse@1 {
 452                                                         reg = <0x1>;
 453                                                         compatible = "pnpPNP,f03";
 454                                                 };
 455                                         };
 456
 457                                         rtc@70 {
 458                                                 compatible = "pnpPNP,b00";
 459                                                 reg = <0x1 0x70 0x2>;
 460                                         };
 461
 462                                         gpio@400 {
 463                                                 reg = <0x1 0x400 0x80>;
 464                                         };
 465                                 };
 466                         };
 467                 };
 468         };
 469 };