arch/powerpc/boot/dts/mpc8544ds.dts

   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "MPC8544DS";
  15         compatible = "MPC8544DS", "MPC85xxDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27                 pci3 = &pci3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8544@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;       // 32 bytes
  38                         i-cache-line-size = <32>;       // 32 bytes
  39                         d-cache-size = <0x8000>;                // L1, 32K
  40                         i-cache-size = <0x8000>;                // L1, 32K
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x0 0x0>;        // Filled by U-Boot
  51         };
  52
  53         soc8544@e0000000 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 device_type = "soc";
  57
  58                 ranges = <0x0 0xe0000000 0x100000>;
  59                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
  60                 bus-frequency = <0>;            // Filled out by uboot.
  61
  62                 memory-controller@2000 {
  63                         compatible = "fsl,8544-memory-controller";
  64                         reg = <0x2000 0x1000>;
  65                         interrupt-parent = <&mpic>;
  66                         interrupts = <18 2>;
  67                 };
  68
  69                 L2: l2-cache-controller@20000 {
  70                         compatible = "fsl,8544-l2-cache-controller";
  71                         reg = <0x20000 0x1000>;
  72                         cache-line-size = <32>; // 32 bytes
  73                         cache-size = <0x40000>; // L2, 256K
  74                         interrupt-parent = <&mpic>;
  75                         interrupts = <16 2>;
  76                 };
  77
  78                 i2c@3000 {
  79                         #address-cells = <1>;
  80                         #size-cells = <0>;
  81                         cell-index = <0>;
  82                         compatible = "fsl-i2c";
  83                         reg = <0x3000 0x100>;
  84                         interrupts = <43 2>;
  85                         interrupt-parent = <&mpic>;
  86                         dfsrr;
  87                 };
  88
  89                 i2c@3100 {
  90                         #address-cells = <1>;
  91                         #size-cells = <0>;
  92                         cell-index = <1>;
  93                         compatible = "fsl-i2c";
  94                         reg = <0x3100 0x100>;
  95                         interrupts = <43 2>;
  96                         interrupt-parent = <&mpic>;
  97                         dfsrr;
  98                 };
  99
 100                 mdio@24520 {
 101                         #address-cells = <1>;
 102                         #size-cells = <0>;
 103                         compatible = "fsl,gianfar-mdio";
 104                         reg = <0x24520 0x20>;
 105
 106                         phy0: ethernet-phy@0 {
 107                                 interrupt-parent = <&mpic>;
 108                                 interrupts = <10 1>;
 109                                 reg = <0x0>;
 110                                 device_type = "ethernet-phy";
 111                         };
 112                         phy1: ethernet-phy@1 {
 113                                 interrupt-parent = <&mpic>;
 114                                 interrupts = <10 1>;
 115                                 reg = <0x1>;
 116                                 device_type = "ethernet-phy";
 117                         };
 118                 };
 119
 120                 dma@21300 {
 121                         #address-cells = <1>;
 122                         #size-cells = <1>;
 123                         compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
 124                         reg = <0x21300 0x4>;
 125                         ranges = <0x0 0x21100 0x200>;
 126                         cell-index = <0>;
 127                         dma-channel@0 {
 128                                 compatible = "fsl,mpc8544-dma-channel",
 129                                                 "fsl,eloplus-dma-channel";
 130                                 reg = <0x0 0x80>;
 131                                 cell-index = <0>;
 132                                 interrupt-parent = <&mpic>;
 133                                 interrupts = <20 2>;
 134                         };
 135                         dma-channel@80 {
 136                                 compatible = "fsl,mpc8544-dma-channel",
 137                                                 "fsl,eloplus-dma-channel";
 138                                 reg = <0x80 0x80>;
 139                                 cell-index = <1>;
 140                                 interrupt-parent = <&mpic>;
 141                                 interrupts = <21 2>;
 142                         };
 143                         dma-channel@100 {
 144                                 compatible = "fsl,mpc8544-dma-channel",
 145                                                 "fsl,eloplus-dma-channel";
 146                                 reg = <0x100 0x80>;
 147                                 cell-index = <2>;
 148                                 interrupt-parent = <&mpic>;
 149                                 interrupts = <22 2>;
 150                         };
 151                         dma-channel@180 {
 152                                 compatible = "fsl,mpc8544-dma-channel",
 153                                                 "fsl,eloplus-dma-channel";
 154                                 reg = <0x180 0x80>;
 155                                 cell-index = <3>;
 156                                 interrupt-parent = <&mpic>;
 157                                 interrupts = <23 2>;
 158                         };
 159                 };
 160
 161                 enet0: ethernet@24000 {
 162                         cell-index = <0>;
 163                         device_type = "network";
 164                         model = "TSEC";
 165                         compatible = "gianfar";
 166                         reg = <0x24000 0x1000>;
 167                         local-mac-address = [ 00 00 00 00 00 00 ];
 168                         interrupts = <29 2 30 2 34 2>;
 169                         interrupt-parent = <&mpic>;
 170                         phy-handle = <&phy0>;
 171                         phy-connection-type = "rgmii-id";
 172                 };
 173
 174                 enet1: ethernet@26000 {
 175                         cell-index = <1>;
 176                         device_type = "network";
 177                         model = "TSEC";
 178                         compatible = "gianfar";
 179                         reg = <0x26000 0x1000>;
 180                         local-mac-address = [ 00 00 00 00 00 00 ];
 181                         interrupts = <31 2 32 2 33 2>;
 182                         interrupt-parent = <&mpic>;
 183                         phy-handle = <&phy1>;
 184                         phy-connection-type = "rgmii-id";
 185                 };
 186
 187                 serial0: serial@4500 {
 188                         cell-index = <0>;
 189                         device_type = "serial";
 190                         compatible = "ns16550";
 191                         reg = <0x4500 0x100>;
 192                         clock-frequency = <0>;
 193                         interrupts = <42 2>;
 194                         interrupt-parent = <&mpic>;
 195                 };
 196
 197                 serial1: serial@4600 {
 198                         cell-index = <1>;
 199                         device_type = "serial";
 200                         compatible = "ns16550";
 201                         reg = <0x4600 0x100>;
 202                         clock-frequency = <0>;
 203                         interrupts = <42 2>;
 204                         interrupt-parent = <&mpic>;
 205                 };
 206
 207                 global-utilities@e0000 {        //global utilities block
 208                         compatible = "fsl,mpc8548-guts";
 209                         reg = <0xe0000 0x1000>;
 210                         fsl,has-rstcr;
 211                 };
 212
 213                 crypto@30000 {
 214                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 215                         reg = <0x30000 0x10000>;
 216                         interrupts = <45 2>;
 217                         interrupt-parent = <&mpic>;
 218                         fsl,num-channels = <4>;
 219                         fsl,channel-fifo-len = <24>;
 220                         fsl,exec-units-mask = <0xfe>;
 221                         fsl,descriptor-types-mask = <0x12b0ebf>;
 222                 };
 223
 224                 mpic: pic@40000 {
 225                         interrupt-controller;
 226                         #address-cells = <0>;
 227                         #interrupt-cells = <2>;
 228                         reg = <0x40000 0x40000>;
 229                         compatible = "chrp,open-pic";
 230                         device_type = "open-pic";
 231                 };
 232
 233                 msi@41600 {
 234                         compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
 235                         reg = <0x41600 0x80>;
 236                         msi-available-ranges = <0 0x100>;
 237                         interrupts = <
 238                                 0xe0 0
 239                                 0xe1 0
 240                                 0xe2 0
 241                                 0xe3 0
 242                                 0xe4 0
 243                                 0xe5 0
 244                                 0xe6 0
 245                                 0xe7 0>;
 246                         interrupt-parent = <&mpic>;
 247                 };
 248         };
 249
 250         pci0: pci@e0008000 {
 251                 cell-index = <0>;
 252                 compatible = "fsl,mpc8540-pci";
 253                 device_type = "pci";
 254                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 255                 interrupt-map = <
 256
 257                         /* IDSEL 0x11 J17 Slot 1 */
 258                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 259                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 260                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 261                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 262
 263                         /* IDSEL 0x12 J16 Slot 2 */
 264
 265                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
 266                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
 267                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 268                         0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
 269
 270                 interrupt-parent = <&mpic>;
 271                 interrupts = <24 2>;
 272                 bus-range = <0 255>;
 273                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 274                           0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
 275                 clock-frequency = <66666666>;
 276                 #interrupt-cells = <1>;
 277                 #size-cells = <2>;
 278                 #address-cells = <3>;
 279                 reg = <0xe0008000 0x1000>;
 280         };
 281
 282         pci1: pcie@e0009000 {
 283                 cell-index = <1>;
 284                 compatible = "fsl,mpc8548-pcie";
 285                 device_type = "pci";
 286                 #interrupt-cells = <1>;
 287                 #size-cells = <2>;
 288                 #address-cells = <3>;
 289                 reg = <0xe0009000 0x1000>;
 290                 bus-range = <0 255>;
 291                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 292                           0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
 293                 clock-frequency = <33333333>;
 294                 interrupt-parent = <&mpic>;
 295                 interrupts = <26 2>;
 296                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 297                 interrupt-map = <
 298                         /* IDSEL 0x0 */
 299                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
 300                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
 301                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
 302                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
 303                         >;
 304                 pcie@0 {
 305                         reg = <0x0 0x0 0x0 0x0 0x0>;
 306                         #size-cells = <2>;
 307                         #address-cells = <3>;
 308                         device_type = "pci";
 309                         ranges = <0x2000000 0x0 0x80000000
 310                                   0x2000000 0x0 0x80000000
 311                                   0x0 0x20000000
 312
 313                                   0x1000000 0x0 0x0
 314                                   0x1000000 0x0 0x0
 315                                   0x0 0x10000>;
 316                 };
 317         };
 318
 319         pci2: pcie@e000a000 {
 320                 cell-index = <2>;
 321                 compatible = "fsl,mpc8548-pcie";
 322                 device_type = "pci";
 323                 #interrupt-cells = <1>;
 324                 #size-cells = <2>;
 325                 #address-cells = <3>;
 326                 reg = <0xe000a000 0x1000>;
 327                 bus-range = <0 255>;
 328                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 329                           0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
 330                 clock-frequency = <33333333>;
 331                 interrupt-parent = <&mpic>;
 332                 interrupts = <25 2>;
 333                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 334                 interrupt-map = <
 335                         /* IDSEL 0x0 */
 336                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 337                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 338                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 339                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 340                         >;
 341                 pcie@0 {
 342                         reg = <0x0 0x0 0x0 0x0 0x0>;
 343                         #size-cells = <2>;
 344                         #address-cells = <3>;
 345                         device_type = "pci";
 346                         ranges = <0x2000000 0x0 0xa0000000
 347                                   0x2000000 0x0 0xa0000000
 348                                   0x0 0x10000000
 349
 350                                   0x1000000 0x0 0x0
 351                                   0x1000000 0x0 0x0
 352                                   0x0 0x10000>;
 353                 };
 354         };
 355
 356         pci3: pcie@e000b000 {
 357                 cell-index = <3>;
 358                 compatible = "fsl,mpc8548-pcie";
 359                 device_type = "pci";
 360                 #interrupt-cells = <1>;
 361                 #size-cells = <2>;
 362                 #address-cells = <3>;
 363                 reg = <0xe000b000 0x1000>;
 364                 bus-range = <0 255>;
 365                 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
 366                           0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
 367                 clock-frequency = <33333333>;
 368                 interrupt-parent = <&mpic>;
 369                 interrupts = <27 2>;
 370                 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
 371                 interrupt-map = <
 372                         // IDSEL 0x1c  USB
 373                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 374                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 375                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 376                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 377
 378                         // IDSEL 0x1d  Audio
 379                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 380
 381                         // IDSEL 0x1e Legacy
 382                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 383                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 384
 385                         // IDSEL 0x1f IDE/SATA
 386                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 387                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 388                 >;
 389
 390                 pcie@0 {
 391                         reg = <0x0 0x0 0x0 0x0 0x0>;
 392                         #size-cells = <2>;
 393                         #address-cells = <3>;
 394                         device_type = "pci";
 395                         ranges = <0x2000000 0x0 0xb0000000
 396                                   0x2000000 0x0 0xb0000000
 397                                   0x0 0x100000
 398
 399                                   0x1000000 0x0 0x0
 400                                   0x1000000 0x0 0x0
 401                                   0x0 0x100000>;
 402
 403                         uli1575@0 {
 404                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 405                                 #size-cells = <2>;
 406                                 #address-cells = <3>;
 407                                 ranges = <0x2000000 0x0 0xb0000000
 408                                           0x2000000 0x0 0xb0000000
 409                                           0x0 0x100000
 410
 411                                           0x1000000 0x0 0x0
 412                                           0x1000000 0x0 0x0
 413                                           0x0 0x100000>;
 414                                 isa@1e {
 415                                         device_type = "isa";
 416                                         #interrupt-cells = <2>;
 417                                         #size-cells = <1>;
 418                                         #address-cells = <2>;
 419                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 420                                         ranges = <0x1 0x0
 421                                                   0x1000000 0x0 0x0
 422                                                   0x1000>;
 423                                         interrupt-parent = <&i8259>;
 424
 425                                         i8259: interrupt-controller@20 {
 426                                                 reg = <0x1 0x20 0x2
 427                                                        0x1 0xa0 0x2
 428                                                        0x1 0x4d0 0x2>;
 429                                                 interrupt-controller;
 430                                                 device_type = "interrupt-controller";
 431                                                 #address-cells = <0>;
 432                                                 #interrupt-cells = <2>;
 433                                                 compatible = "chrp,iic";
 434                                                 interrupts = <9 2>;
 435                                                 interrupt-parent = <&mpic>;
 436                                         };
 437
 438                                         i8042@60 {
 439                                                 #size-cells = <0>;
 440                                                 #address-cells = <1>;
 441                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 442                                                 interrupts = <1 3 12 3>;
 443                                                 interrupt-parent = <&i8259>;
 444
 445                                                 keyboard@0 {
 446                                                         reg = <0x0>;
 447                                                         compatible = "pnpPNP,303";
 448                                                 };
 449
 450                                                 mouse@1 {
 451                                                         reg = <0x1>;
 452                                                         compatible = "pnpPNP,f03";
 453                                                 };
 454                                         };
 455
 456                                         rtc@70 {
 457                                                 compatible = "pnpPNP,b00";
 458                                                 reg = <0x1 0x70 0x2>;
 459                                         };
 460
 461                                         gpio@400 {
 462                                                 reg = <0x1 0x400 0x80>;
 463                                         };
 464                                 };
 465                         };
 466                 };
 467         };
 468 };