arch/powerpc/boot/dts/mpc8544ds.dts

   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13 / {
  14         model = "MPC8544DS";
  15         compatible = "MPC8544DS", "MPC85xxDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 ethernet0 = &enet0;
  21                 ethernet1 = &enet1;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27                 pci3 = &pci3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8544@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;       // 32 bytes
  38                         i-cache-line-size = <32>;       // 32 bytes
  39                         d-cache-size = <0x8000>;                // L1, 32K
  40                         i-cache-size = <0x8000>;                // L1, 32K
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x0 0x0>;        // Filled by U-Boot
  51         };
  52
  53         soc8544@e0000000 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 device_type = "soc";
  57                 compatible = "simple-bus";
  58
  59                 ranges = <0x0 0xe0000000 0x100000>;
  60                 reg = <0xe0000000 0x1000>;      // CCSRBAR 1M
  61                 bus-frequency = <0>;            // Filled out by uboot.
  62
  63                 memory-controller@2000 {
  64                         compatible = "fsl,8544-memory-controller";
  65                         reg = <0x2000 0x1000>;
  66                         interrupt-parent = <&mpic>;
  67                         interrupts = <18 2>;
  68                 };
  69
  70                 L2: l2-cache-controller@20000 {
  71                         compatible = "fsl,8544-l2-cache-controller";
  72                         reg = <0x20000 0x1000>;
  73                         cache-line-size = <32>; // 32 bytes
  74                         cache-size = <0x40000>; // L2, 256K
  75                         interrupt-parent = <&mpic>;
  76                         interrupts = <16 2>;
  77                 };
  78
  79                 i2c@3000 {
  80                         #address-cells = <1>;
  81                         #size-cells = <0>;
  82                         cell-index = <0>;
  83                         compatible = "fsl-i2c";
  84                         reg = <0x3000 0x100>;
  85                         interrupts = <43 2>;
  86                         interrupt-parent = <&mpic>;
  87                         dfsrr;
  88                 };
  89
  90                 i2c@3100 {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93                         cell-index = <1>;
  94                         compatible = "fsl-i2c";
  95                         reg = <0x3100 0x100>;
  96                         interrupts = <43 2>;
  97                         interrupt-parent = <&mpic>;
  98                         dfsrr;
  99                 };
 100
 101                 dma@21300 {
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
 105                         reg = <0x21300 0x4>;
 106                         ranges = <0x0 0x21100 0x200>;
 107                         cell-index = <0>;
 108                         dma-channel@0 {
 109                                 compatible = "fsl,mpc8544-dma-channel",
 110                                                 "fsl,eloplus-dma-channel";
 111                                 reg = <0x0 0x80>;
 112                                 cell-index = <0>;
 113                                 interrupt-parent = <&mpic>;
 114                                 interrupts = <20 2>;
 115                         };
 116                         dma-channel@80 {
 117                                 compatible = "fsl,mpc8544-dma-channel",
 118                                                 "fsl,eloplus-dma-channel";
 119                                 reg = <0x80 0x80>;
 120                                 cell-index = <1>;
 121                                 interrupt-parent = <&mpic>;
 122                                 interrupts = <21 2>;
 123                         };
 124                         dma-channel@100 {
 125                                 compatible = "fsl,mpc8544-dma-channel",
 126                                                 "fsl,eloplus-dma-channel";
 127                                 reg = <0x100 0x80>;
 128                                 cell-index = <2>;
 129                                 interrupt-parent = <&mpic>;
 130                                 interrupts = <22 2>;
 131                         };
 132                         dma-channel@180 {
 133                                 compatible = "fsl,mpc8544-dma-channel",
 134                                                 "fsl,eloplus-dma-channel";
 135                                 reg = <0x180 0x80>;
 136                                 cell-index = <3>;
 137                                 interrupt-parent = <&mpic>;
 138                                 interrupts = <23 2>;
 139                         };
 140                 };
 141
 142                 enet0: ethernet@24000 {
 143                         #address-cells = <1>;
 144                         #size-cells = <1>;
 145                         cell-index = <0>;
 146                         device_type = "network";
 147                         model = "TSEC";
 148                         compatible = "gianfar";
 149                         reg = <0x24000 0x1000>;
 150                         ranges = <0x0 0x24000 0x1000>;
 151                         local-mac-address = [ 00 00 00 00 00 00 ];
 152                         interrupts = <29 2 30 2 34 2>;
 153                         interrupt-parent = <&mpic>;
 154                         phy-handle = <&phy0>;
 155                         tbi-handle = <&tbi0>;
 156                         phy-connection-type = "rgmii-id";
 157
 158                         mdio@520 {
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                                 compatible = "fsl,gianfar-mdio";
 162                                 reg = <0x520 0x20>;
 163
 164                                 phy0: ethernet-phy@0 {
 165                                         interrupt-parent = <&mpic>;
 166                                         interrupts = <10 1>;
 167                                         reg = <0x0>;
 168                                         device_type = "ethernet-phy";
 169                                 };
 170                                 phy1: ethernet-phy@1 {
 171                                         interrupt-parent = <&mpic>;
 172                                         interrupts = <10 1>;
 173                                         reg = <0x1>;
 174                                         device_type = "ethernet-phy";
 175                                 };
 176
 177                                 tbi0: tbi-phy@11 {
 178                                         reg = <0x11>;
 179                                         device_type = "tbi-phy";
 180                                 };
 181                         };
 182                 };
 183
 184                 enet1: ethernet@26000 {
 185                         #address-cells = <1>;
 186                         #size-cells = <1>;
 187                         cell-index = <1>;
 188                         device_type = "network";
 189                         model = "TSEC";
 190                         compatible = "gianfar";
 191                         reg = <0x26000 0x1000>;
 192                         ranges = <0x0 0x26000 0x1000>;
 193                         local-mac-address = [ 00 00 00 00 00 00 ];
 194                         interrupts = <31 2 32 2 33 2>;
 195                         interrupt-parent = <&mpic>;
 196                         phy-handle = <&phy1>;
 197                         tbi-handle = <&tbi1>;
 198                         phy-connection-type = "rgmii-id";
 199
 200                         mdio@520 {
 201                                 #address-cells = <1>;
 202                                 #size-cells = <0>;
 203                                 compatible = "fsl,gianfar-tbi";
 204                                 reg = <0x520 0x20>;
 205
 206                                 tbi1: tbi-phy@11 {
 207                                         reg = <0x11>;
 208                                         device_type = "tbi-phy";
 209                                 };
 210                         };
 211                 };
 212
 213                 serial0: serial@4500 {
 214                         cell-index = <0>;
 215                         device_type = "serial";
 216                         compatible = "ns16550";
 217                         reg = <0x4500 0x100>;
 218                         clock-frequency = <0>;
 219                         interrupts = <42 2>;
 220                         interrupt-parent = <&mpic>;
 221                 };
 222
 223                 serial1: serial@4600 {
 224                         cell-index = <1>;
 225                         device_type = "serial";
 226                         compatible = "ns16550";
 227                         reg = <0x4600 0x100>;
 228                         clock-frequency = <0>;
 229                         interrupts = <42 2>;
 230                         interrupt-parent = <&mpic>;
 231                 };
 232
 233                 global-utilities@e0000 {        //global utilities block
 234                         compatible = "fsl,mpc8548-guts";
 235                         reg = <0xe0000 0x1000>;
 236                         fsl,has-rstcr;
 237                 };
 238
 239                 crypto@30000 {
 240                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 241                         reg = <0x30000 0x10000>;
 242                         interrupts = <45 2>;
 243                         interrupt-parent = <&mpic>;
 244                         fsl,num-channels = <4>;
 245                         fsl,channel-fifo-len = <24>;
 246                         fsl,exec-units-mask = <0xfe>;
 247                         fsl,descriptor-types-mask = <0x12b0ebf>;
 248                 };
 249
 250                 mpic: pic@40000 {
 251                         interrupt-controller;
 252                         #address-cells = <0>;
 253                         #interrupt-cells = <2>;
 254                         reg = <0x40000 0x40000>;
 255                         compatible = "chrp,open-pic";
 256                         device_type = "open-pic";
 257                 };
 258
 259                 msi@41600 {
 260                         compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
 261                         reg = <0x41600 0x80>;
 262                         msi-available-ranges = <0 0x100>;
 263                         interrupts = <
 264                                 0xe0 0
 265                                 0xe1 0
 266                                 0xe2 0
 267                                 0xe3 0
 268                                 0xe4 0
 269                                 0xe5 0
 270                                 0xe6 0
 271                                 0xe7 0>;
 272                         interrupt-parent = <&mpic>;
 273                 };
 274         };
 275
 276         pci0: pci@e0008000 {
 277                 cell-index = <0>;
 278                 compatible = "fsl,mpc8540-pci";
 279                 device_type = "pci";
 280                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 281                 interrupt-map = <
 282
 283                         /* IDSEL 0x11 J17 Slot 1 */
 284                         0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
 285                         0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
 286                         0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
 287                         0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
 288
 289                         /* IDSEL 0x12 J16 Slot 2 */
 290
 291                         0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
 292                         0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
 293                         0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
 294                         0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
 295
 296                 interrupt-parent = <&mpic>;
 297                 interrupts = <24 2>;
 298                 bus-range = <0 255>;
 299                 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
 300                           0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
 301                 clock-frequency = <66666666>;
 302                 #interrupt-cells = <1>;
 303                 #size-cells = <2>;
 304                 #address-cells = <3>;
 305                 reg = <0xe0008000 0x1000>;
 306         };
 307
 308         pci1: pcie@e0009000 {
 309                 cell-index = <1>;
 310                 compatible = "fsl,mpc8548-pcie";
 311                 device_type = "pci";
 312                 #interrupt-cells = <1>;
 313                 #size-cells = <2>;
 314                 #address-cells = <3>;
 315                 reg = <0xe0009000 0x1000>;
 316                 bus-range = <0 255>;
 317                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 318                           0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
 319                 clock-frequency = <33333333>;
 320                 interrupt-parent = <&mpic>;
 321                 interrupts = <25 2>;
 322                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 323                 interrupt-map = <
 324                         /* IDSEL 0x0 */
 325                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
 326                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
 327                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
 328                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
 329                         >;
 330                 pcie@0 {
 331                         reg = <0x0 0x0 0x0 0x0 0x0>;
 332                         #size-cells = <2>;
 333                         #address-cells = <3>;
 334                         device_type = "pci";
 335                         ranges = <0x2000000 0x0 0x80000000
 336                                   0x2000000 0x0 0x80000000
 337                                   0x0 0x20000000
 338
 339                                   0x1000000 0x0 0x0
 340                                   0x1000000 0x0 0x0
 341                                   0x0 0x10000>;
 342                 };
 343         };
 344
 345         pci2: pcie@e000a000 {
 346                 cell-index = <2>;
 347                 compatible = "fsl,mpc8548-pcie";
 348                 device_type = "pci";
 349                 #interrupt-cells = <1>;
 350                 #size-cells = <2>;
 351                 #address-cells = <3>;
 352                 reg = <0xe000a000 0x1000>;
 353                 bus-range = <0 255>;
 354                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 355                           0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
 356                 clock-frequency = <33333333>;
 357                 interrupt-parent = <&mpic>;
 358                 interrupts = <26 2>;
 359                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 360                 interrupt-map = <
 361                         /* IDSEL 0x0 */
 362                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 363                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 364                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 365                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 366                         >;
 367                 pcie@0 {
 368                         reg = <0x0 0x0 0x0 0x0 0x0>;
 369                         #size-cells = <2>;
 370                         #address-cells = <3>;
 371                         device_type = "pci";
 372                         ranges = <0x2000000 0x0 0xa0000000
 373                                   0x2000000 0x0 0xa0000000
 374                                   0x0 0x10000000
 375
 376                                   0x1000000 0x0 0x0
 377                                   0x1000000 0x0 0x0
 378                                   0x0 0x10000>;
 379                 };
 380         };
 381
 382         pci3: pcie@e000b000 {
 383                 cell-index = <3>;
 384                 compatible = "fsl,mpc8548-pcie";
 385                 device_type = "pci";
 386                 #interrupt-cells = <1>;
 387                 #size-cells = <2>;
 388                 #address-cells = <3>;
 389                 reg = <0xe000b000 0x1000>;
 390                 bus-range = <0 255>;
 391                 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
 392                           0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
 393                 clock-frequency = <33333333>;
 394                 interrupt-parent = <&mpic>;
 395                 interrupts = <27 2>;
 396                 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
 397                 interrupt-map = <
 398                         // IDSEL 0x1c  USB
 399                         0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
 400                         0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
 401                         0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
 402                         0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
 403
 404                         // IDSEL 0x1d  Audio
 405                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 406
 407                         // IDSEL 0x1e Legacy
 408                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 409                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 410
 411                         // IDSEL 0x1f IDE/SATA
 412                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 413                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 414                 >;
 415
 416                 pcie@0 {
 417                         reg = <0x0 0x0 0x0 0x0 0x0>;
 418                         #size-cells = <2>;
 419                         #address-cells = <3>;
 420                         device_type = "pci";
 421                         ranges = <0x2000000 0x0 0xb0000000
 422                                   0x2000000 0x0 0xb0000000
 423                                   0x0 0x100000
 424
 425                                   0x1000000 0x0 0x0
 426                                   0x1000000 0x0 0x0
 427                                   0x0 0x100000>;
 428
 429                         uli1575@0 {
 430                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 431                                 #size-cells = <2>;
 432                                 #address-cells = <3>;
 433                                 ranges = <0x2000000 0x0 0xb0000000
 434                                           0x2000000 0x0 0xb0000000
 435                                           0x0 0x100000
 436
 437                                           0x1000000 0x0 0x0
 438                                           0x1000000 0x0 0x0
 439                                           0x0 0x100000>;
 440                                 isa@1e {
 441                                         device_type = "isa";
 442                                         #interrupt-cells = <2>;
 443                                         #size-cells = <1>;
 444                                         #address-cells = <2>;
 445                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 446                                         ranges = <0x1 0x0
 447                                                   0x1000000 0x0 0x0
 448                                                   0x1000>;
 449                                         interrupt-parent = <&i8259>;
 450
 451                                         i8259: interrupt-controller@20 {
 452                                                 reg = <0x1 0x20 0x2
 453                                                        0x1 0xa0 0x2
 454                                                        0x1 0x4d0 0x2>;
 455                                                 interrupt-controller;
 456                                                 device_type = "interrupt-controller";
 457                                                 #address-cells = <0>;
 458                                                 #interrupt-cells = <2>;
 459                                                 compatible = "chrp,iic";
 460                                                 interrupts = <9 2>;
 461                                                 interrupt-parent = <&mpic>;
 462                                         };
 463
 464                                         i8042@60 {
 465                                                 #size-cells = <0>;
 466                                                 #address-cells = <1>;
 467                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 468                                                 interrupts = <1 3 12 3>;
 469                                                 interrupt-parent = <&i8259>;
 470
 471                                                 keyboard@0 {
 472                                                         reg = <0x0>;
 473                                                         compatible = "pnpPNP,303";
 474                                                 };
 475
 476                                                 mouse@1 {
 477                                                         reg = <0x1>;
 478                                                         compatible = "pnpPNP,f03";
 479                                                 };
 480                                         };
 481
 482                                         rtc@70 {
 483                                                 compatible = "pnpPNP,b00";
 484                                                 reg = <0x1 0x70 0x2>;
 485                                         };
 486
 487                                         gpio@400 {
 488                                                 reg = <0x1 0x400 0x80>;
 489                                         };
 490                                 };
 491                         };
 492                 };
 493         };
 494 };