arch/powerpc/boot/dts/mpc8540ads.dts

   1 /*
   2  * MPC8540 ADS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8540ADS";
  15         compatible = "MPC8540ADS", "MPC85xxADS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8540@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       //  33 MHz, from uboot
  31                         bus-frequency = <0>;    // 166 MHz
  32                         clock-frequency = <0>;  // 825 MHz, from uboot
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 08000000>;      // 128M at 0x0
  40         };
  41
  42         soc8540@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47                 ranges = <0 e0000000 00100000>;
  48                 reg = <e0000000 00100000>;      // CCSRBAR 1M
  49                 bus-frequency = <0>;
  50
  51                 i2c@3000 {
  52                         device_type = "i2c";
  53                         compatible = "fsl-i2c";
  54                         reg = <3000 100>;
  55                         interrupts = <1b 2>;
  56                         interrupt-parent = <&mpic>;
  57                         dfsrr;
  58                 };
  59
  60                 mdio@24520 {
  61                         #address-cells = <1>;
  62                         #size-cells = <0>;
  63                         device_type = "mdio";
  64                         compatible = "gianfar";
  65                         reg = <24520 20>;
  66                         phy0: ethernet-phy@0 {
  67                                 interrupt-parent = <&mpic>;
  68                                 interrupts = <35 1>;
  69                                 reg = <0>;
  70                                 device_type = "ethernet-phy";
  71                         };
  72                         phy1: ethernet-phy@1 {
  73                                 interrupt-parent = <&mpic>;
  74                                 interrupts = <35 1>;
  75                                 reg = <1>;
  76                                 device_type = "ethernet-phy";
  77                         };
  78                         phy3: ethernet-phy@3 {
  79                                 interrupt-parent = <&mpic>;
  80                                 interrupts = <37 1>;
  81                                 reg = <3>;
  82                                 device_type = "ethernet-phy";
  83                         };
  84                 };
  85
  86                 ethernet@24000 {
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                         device_type = "network";
  90                         model = "TSEC";
  91                         compatible = "gianfar";
  92                         reg = <24000 1000>;
  93                         address = [ 00 E0 0C 00 73 00 ];
  94                         local-mac-address = [ 00 E0 0C 00 73 00 ];
  95                         interrupts = <d 2 e 2 12 2>;
  96                         interrupt-parent = <&mpic>;
  97                         phy-handle = <&phy0>;
  98                 };
  99
 100                 ethernet@25000 {
 101                         #address-cells = <1>;
 102                         #size-cells = <0>;
 103                         device_type = "network";
 104                         model = "TSEC";
 105                         compatible = "gianfar";
 106                         reg = <25000 1000>;
 107                         address = [ 00 E0 0C 00 73 01 ];
 108                         local-mac-address = [ 00 E0 0C 00 73 01 ];
 109                         interrupts = <13 2 14 2 18 2>;
 110                         interrupt-parent = <&mpic>;
 111                         phy-handle = <&phy1>;
 112                 };
 113
 114                 ethernet@26000 {
 115                         #address-cells = <1>;
 116                         #size-cells = <0>;
 117                         device_type = "network";
 118                         model = "FEC";
 119                         compatible = "gianfar";
 120                         reg = <26000 1000>;
 121                         address = [ 00 E0 0C 00 73 02 ];
 122                         local-mac-address = [ 00 E0 0C 00 73 02 ];
 123                         interrupts = <19 2>;
 124                         interrupt-parent = <&mpic>;
 125                         phy-handle = <&phy3>;
 126                 };
 127
 128                 serial@4500 {
 129                         device_type = "serial";
 130                         compatible = "ns16550";
 131                         reg = <4500 100>;       // reg base, size
 132                         clock-frequency = <0>;  // should we fill in in uboot?
 133                         interrupts = <1a 2>;
 134                         interrupt-parent = <&mpic>;
 135                 };
 136
 137                 serial@4600 {
 138                         device_type = "serial";
 139                         compatible = "ns16550";
 140                         reg = <4600 100>;       // reg base, size
 141                         clock-frequency = <0>;  // should we fill in in uboot?
 142                         interrupts = <1a 2>;
 143                         interrupt-parent = <&mpic>;
 144                 };
 145                 pci@8000 {
 146                         interrupt-map-mask = <f800 0 0 7>;
 147                         interrupt-map = <
 148
 149                                 /* IDSEL 0x02 */
 150                                 1000 0 0 1 &mpic 31 1
 151                                 1000 0 0 2 &mpic 32 1
 152                                 1000 0 0 3 &mpic 33 1
 153                                 1000 0 0 4 &mpic 34 1
 154
 155                                 /* IDSEL 0x03 */
 156                                 1800 0 0 1 &mpic 34 1
 157                                 1800 0 0 2 &mpic 31 1
 158                                 1800 0 0 3 &mpic 32 1
 159                                 1800 0 0 4 &mpic 33 1
 160
 161                                 /* IDSEL 0x04 */
 162                                 2000 0 0 1 &mpic 33 1
 163                                 2000 0 0 2 &mpic 34 1
 164                                 2000 0 0 3 &mpic 31 1
 165                                 2000 0 0 4 &mpic 32 1
 166
 167                                 /* IDSEL 0x05 */
 168                                 2800 0 0 1 &mpic 32 1
 169                                 2800 0 0 2 &mpic 33 1
 170                                 2800 0 0 3 &mpic 34 1
 171                                 2800 0 0 4 &mpic 31 1
 172
 173                                 /* IDSEL 0x0c */
 174                                 6000 0 0 1 &mpic 31 1
 175                                 6000 0 0 2 &mpic 32 1
 176                                 6000 0 0 3 &mpic 33 1
 177                                 6000 0 0 4 &mpic 34 1
 178
 179                                 /* IDSEL 0x0d */
 180                                 6800 0 0 1 &mpic 34 1
 181                                 6800 0 0 2 &mpic 31 1
 182                                 6800 0 0 3 &mpic 32 1
 183                                 6800 0 0 4 &mpic 33 1
 184
 185                                 /* IDSEL 0x0e */
 186                                 7000 0 0 1 &mpic 33 1
 187                                 7000 0 0 2 &mpic 34 1
 188                                 7000 0 0 3 &mpic 31 1
 189                                 7000 0 0 4 &mpic 32 1
 190
 191                                 /* IDSEL 0x0f */
 192                                 7800 0 0 1 &mpic 32 1
 193                                 7800 0 0 2 &mpic 33 1
 194                                 7800 0 0 3 &mpic 34 1
 195                                 7800 0 0 4 &mpic 31 1
 196
 197                                 /* IDSEL 0x12 */
 198                                 9000 0 0 1 &mpic 31 1
 199                                 9000 0 0 2 &mpic 32 1
 200                                 9000 0 0 3 &mpic 33 1
 201                                 9000 0 0 4 &mpic 34 1
 202
 203                                 /* IDSEL 0x13 */
 204                                 9800 0 0 1 &mpic 34 1
 205                                 9800 0 0 2 &mpic 31 1
 206                                 9800 0 0 3 &mpic 32 1
 207                                 9800 0 0 4 &mpic 33 1
 208
 209                                 /* IDSEL 0x14 */
 210                                 a000 0 0 1 &mpic 33 1
 211                                 a000 0 0 2 &mpic 34 1
 212                                 a000 0 0 3 &mpic 31 1
 213                                 a000 0 0 4 &mpic 32 1
 214
 215                                 /* IDSEL 0x15 */
 216                                 a800 0 0 1 &mpic 32 1
 217                                 a800 0 0 2 &mpic 33 1
 218                                 a800 0 0 3 &mpic 34 1
 219                                 a800 0 0 4 &mpic 31 1>;
 220                         interrupt-parent = <&mpic>;
 221                         interrupts = <08 2>;
 222                         bus-range = <0 0>;
 223                         ranges = <02000000 0 80000000 80000000 0 20000000
 224                                   01000000 0 00000000 e2000000 0 00100000>;
 225                         clock-frequency = <3f940aa>;
 226                         #interrupt-cells = <1>;
 227                         #size-cells = <2>;
 228                         #address-cells = <3>;
 229                         reg = <8000 1000>;
 230                         compatible = "85xx";
 231                         device_type = "pci";
 232                 };
 233
 234                 mpic: pic@40000 {
 235                         clock-frequency = <0>;
 236                         interrupt-controller;
 237                         #address-cells = <0>;
 238                         #interrupt-cells = <2>;
 239                         reg = <40000 40000>;
 240                         built-in;
 241                         compatible = "chrp,open-pic";
 242                         device_type = "open-pic";
 243                         big-endian;
 244                 };
 245         };
 246 };