arch/powerpc/boot/dts/mpc8540ads.dts

   1 /*
   2  * MPC8540 ADS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8540ADS";
  16         compatible = "MPC8540ADS", "MPC85xxADS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 serial0 = &serial0;
  25                 serial1 = &serial1;
  26                 pci0 = &pci0;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8540@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         d-cache-line-size = <32>;       // 32 bytes
  37                         i-cache-line-size = <32>;       // 32 bytes
  38                         d-cache-size = <0x8000>;                // L1, 32K
  39                         i-cache-size = <0x8000>;                // L1, 32K
  40                         timebase-frequency = <0>;       //  33 MHz, from uboot
  41                         bus-frequency = <0>;    // 166 MHz
  42                         clock-frequency = <0>;  // 825 MHz, from uboot
  43                         next-level-cache = <&L2>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x0 0x8000000>;  // 128M at 0x0
  50         };
  51
  52         soc8540@e0000000 {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 device_type = "soc";
  56                 compatible = "simple-bus";
  57                 ranges = <0x0 0xe0000000 0x100000>;
  58                 reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
  59                 bus-frequency = <0>;
  60
  61                 memory-controller@2000 {
  62                         compatible = "fsl,8540-memory-controller";
  63                         reg = <0x2000 0x1000>;
  64                         interrupt-parent = <&mpic>;
  65                         interrupts = <18 2>;
  66                 };
  67
  68                 L2: l2-cache-controller@20000 {
  69                         compatible = "fsl,8540-l2-cache-controller";
  70                         reg = <0x20000 0x1000>;
  71                         cache-line-size = <32>; // 32 bytes
  72                         cache-size = <0x40000>; // L2, 256K
  73                         interrupt-parent = <&mpic>;
  74                         interrupts = <16 2>;
  75                 };
  76
  77                 i2c@3000 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         cell-index = <0>;
  81                         compatible = "fsl-i2c";
  82                         reg = <0x3000 0x100>;
  83                         interrupts = <43 2>;
  84                         interrupt-parent = <&mpic>;
  85                         dfsrr;
  86                 };
  87
  88                 dma@21300 {
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
  92                         reg = <0x21300 0x4>;
  93                         ranges = <0x0 0x21100 0x200>;
  94                         cell-index = <0>;
  95                         dma-channel@0 {
  96                                 compatible = "fsl,mpc8540-dma-channel",
  97                                                 "fsl,eloplus-dma-channel";
  98                                 reg = <0x0 0x80>;
  99                                 cell-index = <0>;
 100                                 interrupt-parent = <&mpic>;
 101                                 interrupts = <20 2>;
 102                         };
 103                         dma-channel@80 {
 104                                 compatible = "fsl,mpc8540-dma-channel",
 105                                                 "fsl,eloplus-dma-channel";
 106                                 reg = <0x80 0x80>;
 107                                 cell-index = <1>;
 108                                 interrupt-parent = <&mpic>;
 109                                 interrupts = <21 2>;
 110                         };
 111                         dma-channel@100 {
 112                                 compatible = "fsl,mpc8540-dma-channel",
 113                                                 "fsl,eloplus-dma-channel";
 114                                 reg = <0x100 0x80>;
 115                                 cell-index = <2>;
 116                                 interrupt-parent = <&mpic>;
 117                                 interrupts = <22 2>;
 118                         };
 119                         dma-channel@180 {
 120                                 compatible = "fsl,mpc8540-dma-channel",
 121                                                 "fsl,eloplus-dma-channel";
 122                                 reg = <0x180 0x80>;
 123                                 cell-index = <3>;
 124                                 interrupt-parent = <&mpic>;
 125                                 interrupts = <23 2>;
 126                         };
 127                 };
 128
 129                 mdio@24520 {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         compatible = "fsl,gianfar-mdio";
 133                         reg = <0x24520 0x20>;
 134
 135                         phy0: ethernet-phy@0 {
 136                                 interrupt-parent = <&mpic>;
 137                                 interrupts = <5 1>;
 138                                 reg = <0x0>;
 139                                 device_type = "ethernet-phy";
 140                         };
 141                         phy1: ethernet-phy@1 {
 142                                 interrupt-parent = <&mpic>;
 143                                 interrupts = <5 1>;
 144                                 reg = <0x1>;
 145                                 device_type = "ethernet-phy";
 146                         };
 147                         phy3: ethernet-phy@3 {
 148                                 interrupt-parent = <&mpic>;
 149                                 interrupts = <7 1>;
 150                                 reg = <0x3>;
 151                                 device_type = "ethernet-phy";
 152                         };
 153                         tbi0: tbi-phy@11 {
 154                                 reg = <0x11>;
 155                                 device_type = "tbi-phy";
 156                         };
 157                 };
 158
 159                 mdio@25520 {
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         compatible = "fsl,gianfar-tbi";
 163                         reg = <0x25520 0x20>;
 164
 165                         tbi1: tbi-phy@11 {
 166                                 reg = <0x11>;
 167                                 device_type = "tbi-phy";
 168                         };
 169                 };
 170
 171                 mdio@26520 {
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         compatible = "fsl,gianfar-tbi";
 175                         reg = <0x26520 0x20>;
 176
 177                         tbi2: tbi-phy@11 {
 178                                 reg = <0x11>;
 179                                 device_type = "tbi-phy";
 180                         };
 181                 };
 182
 183                 enet0: ethernet@24000 {
 184                         cell-index = <0>;
 185                         device_type = "network";
 186                         model = "TSEC";
 187                         compatible = "gianfar";
 188                         reg = <0x24000 0x1000>;
 189                         local-mac-address = [ 00 00 00 00 00 00 ];
 190                         interrupts = <29 2 30 2 34 2>;
 191                         interrupt-parent = <&mpic>;
 192                         tbi-handle = <&tbi0>;
 193                         phy-handle = <&phy0>;
 194                 };
 195
 196                 enet1: ethernet@25000 {
 197                         cell-index = <1>;
 198                         device_type = "network";
 199                         model = "TSEC";
 200                         compatible = "gianfar";
 201                         reg = <0x25000 0x1000>;
 202                         local-mac-address = [ 00 00 00 00 00 00 ];
 203                         interrupts = <35 2 36 2 40 2>;
 204                         interrupt-parent = <&mpic>;
 205                         tbi-handle = <&tbi1>;
 206                         phy-handle = <&phy1>;
 207                 };
 208
 209                 enet2: ethernet@26000 {
 210                         cell-index = <2>;
 211                         device_type = "network";
 212                         model = "FEC";
 213                         compatible = "gianfar";
 214                         reg = <0x26000 0x1000>;
 215                         local-mac-address = [ 00 00 00 00 00 00 ];
 216                         interrupts = <41 2>;
 217                         interrupt-parent = <&mpic>;
 218                         tbi-handle = <&tbi2>;
 219                         phy-handle = <&phy3>;
 220                 };
 221
 222                 serial0: serial@4500 {
 223                         cell-index = <0>;
 224                         device_type = "serial";
 225                         compatible = "ns16550";
 226                         reg = <0x4500 0x100>;   // reg base, size
 227                         clock-frequency = <0>;  // should we fill in in uboot?
 228                         interrupts = <42 2>;
 229                         interrupt-parent = <&mpic>;
 230                 };
 231
 232                 serial1: serial@4600 {
 233                         cell-index = <1>;
 234                         device_type = "serial";
 235                         compatible = "ns16550";
 236                         reg = <0x4600 0x100>;   // reg base, size
 237                         clock-frequency = <0>;  // should we fill in in uboot?
 238                         interrupts = <42 2>;
 239                         interrupt-parent = <&mpic>;
 240                 };
 241                 mpic: pic@40000 {
 242                         interrupt-controller;
 243                         #address-cells = <0>;
 244                         #interrupt-cells = <2>;
 245                         reg = <0x40000 0x40000>;
 246                         compatible = "chrp,open-pic";
 247                         device_type = "open-pic";
 248                 };
 249         };
 250
 251         pci0: pci@e0008000 {
 252                 cell-index = <0>;
 253                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 254                 interrupt-map = <
 255
 256                         /* IDSEL 0x02 */
 257                         0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
 258                         0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
 259                         0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
 260                         0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 261
 262                         /* IDSEL 0x03 */
 263                         0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
 264                         0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
 265                         0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
 266                         0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 267
 268                         /* IDSEL 0x04 */
 269                         0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
 270                         0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
 271                         0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
 272                         0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 273
 274                         /* IDSEL 0x05 */
 275                         0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
 276                         0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
 277                         0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
 278                         0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 279
 280                         /* IDSEL 0x0c */
 281                         0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
 282                         0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
 283                         0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
 284                         0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 285
 286                         /* IDSEL 0x0d */
 287                         0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
 288                         0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
 289                         0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
 290                         0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 291
 292                         /* IDSEL 0x0e */
 293                         0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
 294                         0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
 295                         0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
 296                         0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 297
 298                         /* IDSEL 0x0f */
 299                         0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
 300                         0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
 301                         0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
 302                         0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 303
 304                         /* IDSEL 0x12 */
 305                         0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
 306                         0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
 307                         0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
 308                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 309
 310                         /* IDSEL 0x13 */
 311                         0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
 312                         0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
 313                         0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
 314                         0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 315
 316                         /* IDSEL 0x14 */
 317                         0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
 318                         0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
 319                         0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
 320                         0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 321
 322                         /* IDSEL 0x15 */
 323                         0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
 324                         0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
 325                         0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
 326                         0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
 327                 interrupt-parent = <&mpic>;
 328                 interrupts = <24 2>;
 329                 bus-range = <0 0>;
 330                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 331                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
 332                 clock-frequency = <66666666>;
 333                 #interrupt-cells = <1>;
 334                 #size-cells = <2>;
 335                 #address-cells = <3>;
 336                 reg = <0xe0008000 0x1000>;
 337                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 338                 device_type = "pci";
 339         };
 340 };