arch/powerpc/boot/dts/mpc8378_mds.dts

   1 /*
   2  * MPC8378E MDS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "fsl,mpc8378emds";
  16         compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 PowerPC,8378@0 {
  33                         device_type = "cpu";
  34                         reg = <0x0>;
  35                         d-cache-line-size = <32>;
  36                         i-cache-line-size = <32>;
  37                         d-cache-size = <32768>;
  38                         i-cache-size = <32768>;
  39                         timebase-frequency = <0>;
  40                         bus-frequency = <0>;
  41                         clock-frequency = <0>;
  42                 };
  43         };
  44
  45         memory {
  46                 device_type = "memory";
  47                 reg = <0x00000000 0x20000000>;  // 512MB at 0
  48         };
  49
  50         localbus@e0005000 {
  51                 #address-cells = <2>;
  52                 #size-cells = <1>;
  53                 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
  54                 reg = <0xe0005000 0x1000>;
  55                 interrupts = <77 0x8>;
  56                 interrupt-parent = <&ipic>;
  57
  58                 // booting from NOR flash
  59                 ranges = <0 0x0 0xfe000000 0x02000000
  60                           1 0x0 0xf8000000 0x00008000
  61                           3 0x0 0xe0600000 0x00008000>;
  62
  63                 flash@0,0 {
  64                         #address-cells = <1>;
  65                         #size-cells = <1>;
  66                         compatible = "cfi-flash";
  67                         reg = <0 0x0 0x2000000>;
  68                         bank-width = <2>;
  69                         device-width = <1>;
  70
  71                         u-boot@0 {
  72                                 reg = <0x0 0x100000>;
  73                                 read-only;
  74                         };
  75
  76                         fs@100000 {
  77                                 reg = <0x100000 0x800000>;
  78                         };
  79
  80                         kernel@1d00000 {
  81                                 reg = <0x1d00000 0x200000>;
  82                         };
  83
  84                         dtb@1f00000 {
  85                                 reg = <0x1f00000 0x100000>;
  86                         };
  87                 };
  88
  89                 bcsr@1,0 {
  90                         reg = <1 0x0 0x8000>;
  91                         compatible = "fsl,mpc837xmds-bcsr";
  92                 };
  93
  94                 nand@3,0 {
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         compatible = "fsl,mpc8378-fcm-nand",
  98                                      "fsl,elbc-fcm-nand";
  99                         reg = <3 0x0 0x8000>;
 100
 101                         u-boot@0 {
 102                                 reg = <0x0 0x100000>;
 103                                 read-only;
 104                         };
 105
 106                         kernel@100000 {
 107                                 reg = <0x100000 0x300000>;
 108                         };
 109
 110                         fs@400000 {
 111                                 reg = <0x400000 0x1c00000>;
 112                         };
 113                 };
 114         };
 115
 116         soc@e0000000 {
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 device_type = "soc";
 120                 ranges = <0x0 0xe0000000 0x00100000>;
 121                 reg = <0xe0000000 0x00000200>;
 122                 bus-frequency = <0>;
 123
 124                 wdt@200 {
 125                         compatible = "mpc83xx_wdt";
 126                         reg = <0x200 0x100>;
 127                 };
 128
 129                 i2c@3000 {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         cell-index = <0>;
 133                         compatible = "fsl-i2c";
 134                         reg = <0x3000 0x100>;
 135                         interrupts = <14 0x8>;
 136                         interrupt-parent = <&ipic>;
 137                         dfsrr;
 138                 };
 139
 140                 i2c@3100 {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         cell-index = <1>;
 144                         compatible = "fsl-i2c";
 145                         reg = <0x3100 0x100>;
 146                         interrupts = <15 0x8>;
 147                         interrupt-parent = <&ipic>;
 148                         dfsrr;
 149                 };
 150
 151                 spi@7000 {
 152                         cell-index = <0>;
 153                         compatible = "fsl,spi";
 154                         reg = <0x7000 0x1000>;
 155                         interrupts = <16 0x8>;
 156                         interrupt-parent = <&ipic>;
 157                         mode = "cpu";
 158                 };
 159
 160                 dma@82a8 {
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
 164                         reg = <0x82a8 4>;
 165                         ranges = <0 0x8100 0x1a8>;
 166                         interrupt-parent = <&ipic>;
 167                         interrupts = <71 8>;
 168                         cell-index = <0>;
 169                         dma-channel@0 {
 170                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 171                                 reg = <0 0x80>;
 172                                 interrupt-parent = <&ipic>;
 173                                 interrupts = <71 8>;
 174                         };
 175                         dma-channel@80 {
 176                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 177                                 reg = <0x80 0x80>;
 178                                 interrupt-parent = <&ipic>;
 179                                 interrupts = <71 8>;
 180                         };
 181                         dma-channel@100 {
 182                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 183                                 reg = <0x100 0x80>;
 184                                 interrupt-parent = <&ipic>;
 185                                 interrupts = <71 8>;
 186                         };
 187                         dma-channel@180 {
 188                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
 189                                 reg = <0x180 0x28>;
 190                                 interrupt-parent = <&ipic>;
 191                                 interrupts = <71 8>;
 192                         };
 193                 };
 194
 195                 usb@23000 {
 196                         compatible = "fsl-usb2-dr";
 197                         reg = <0x23000 0x1000>;
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200                         interrupt-parent = <&ipic>;
 201                         interrupts = <38 0x8>;
 202                         dr_mode = "host";
 203                         phy_type = "ulpi";
 204                 };
 205
 206                 mdio@24520 {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209                         compatible = "fsl,gianfar-mdio";
 210                         reg = <0x24520 0x20>;
 211                         phy2: ethernet-phy@2 {
 212                                 interrupt-parent = <&ipic>;
 213                                 interrupts = <17 0x8>;
 214                                 reg = <0x2>;
 215                                 device_type = "ethernet-phy";
 216                         };
 217                         phy3: ethernet-phy@3 {
 218                                 interrupt-parent = <&ipic>;
 219                                 interrupts = <18 0x8>;
 220                                 reg = <0x3>;
 221                                 device_type = "ethernet-phy";
 222                         };
 223                 };
 224
 225                 enet0: ethernet@24000 {
 226                         cell-index = <0>;
 227                         device_type = "network";
 228                         model = "eTSEC";
 229                         compatible = "gianfar";
 230                         reg = <0x24000 0x1000>;
 231                         local-mac-address = [ 00 00 00 00 00 00 ];
 232                         interrupts = <32 0x8 33 0x8 34 0x8>;
 233                         phy-connection-type = "mii";
 234                         interrupt-parent = <&ipic>;
 235                         phy-handle = <&phy2>;
 236                 };
 237
 238                 enet1: ethernet@25000 {
 239                         cell-index = <1>;
 240                         device_type = "network";
 241                         model = "eTSEC";
 242                         compatible = "gianfar";
 243                         reg = <0x25000 0x1000>;
 244                         local-mac-address = [ 00 00 00 00 00 00 ];
 245                         interrupts = <35 0x8 36 0x8 37 0x8>;
 246                         phy-connection-type = "mii";
 247                         interrupt-parent = <&ipic>;
 248                         phy-handle = <&phy3>;
 249                 };
 250
 251                 serial0: serial@4500 {
 252                         cell-index = <0>;
 253                         device_type = "serial";
 254                         compatible = "ns16550";
 255                         reg = <0x4500 0x100>;
 256                         clock-frequency = <0>;
 257                         interrupts = <9 0x8>;
 258                         interrupt-parent = <&ipic>;
 259                 };
 260
 261                 serial1: serial@4600 {
 262                         cell-index = <1>;
 263                         device_type = "serial";
 264                         compatible = "ns16550";
 265                         reg = <0x4600 0x100>;
 266                         clock-frequency = <0>;
 267                         interrupts = <10 0x8>;
 268                         interrupt-parent = <&ipic>;
 269                 };
 270
 271                 crypto@30000 {
 272                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 273                                      "fsl,sec2.1", "fsl,sec2.0";
 274                         reg = <0x30000 0x10000>;
 275                         interrupts = <11 0x8>;
 276                         interrupt-parent = <&ipic>;
 277                         fsl,num-channels = <4>;
 278                         fsl,channel-fifo-len = <24>;
 279                         fsl,exec-units-mask = <0x9fe>;
 280                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 281                 };
 282
 283                 sdhc@2e000 {
 284                         model = "eSDHC";
 285                         compatible = "fsl,esdhc";
 286                         reg = <0x2e000 0x1000>;
 287                         interrupts = <42 0x8>;
 288                         interrupt-parent = <&ipic>;
 289                 };
 290
 291                 /* IPIC
 292                  * interrupts cell = <intr #, sense>
 293                  * sense values match linux IORESOURCE_IRQ_* defines:
 294                  * sense == 8: Level, low assertion
 295                  * sense == 2: Edge, high-to-low change
 296                  */
 297                 ipic: pic@700 {
 298                         compatible = "fsl,ipic";
 299                         interrupt-controller;
 300                         #address-cells = <0>;
 301                         #interrupt-cells = <2>;
 302                         reg = <0x700 0x100>;
 303                 };
 304         };
 305
 306         pci0: pci@e0008500 {
 307                 cell-index = <0>;
 308                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 309                 interrupt-map = <
 310
 311                                 /* IDSEL 0x11 */
 312                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 313                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 314                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 315                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 316
 317                                 /* IDSEL 0x12 */
 318                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 319                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 320                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 321                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 322
 323                                 /* IDSEL 0x13 */
 324                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 325                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 326                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 327                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 328
 329                                 /* IDSEL 0x15 */
 330                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 331                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 332                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 333                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 334
 335                                 /* IDSEL 0x16 */
 336                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 337                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 338                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 339                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 340
 341                                 /* IDSEL 0x17 */
 342                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 343                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 344                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 345                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 346
 347                                 /* IDSEL 0x18 */
 348                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 349                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 350                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 351                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 352                 interrupt-parent = <&ipic>;
 353                 interrupts = <66 0x8>;
 354                 bus-range = <0x0 0x0>;
 355                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 356                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 357                           0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
 358                 clock-frequency = <0>;
 359                 #interrupt-cells = <1>;
 360                 #size-cells = <2>;
 361                 #address-cells = <3>;
 362                 reg = <0xe0008500 0x100>;
 363                 compatible = "fsl,mpc8349-pci";
 364                 device_type = "pci";
 365         };
 366 };