arch/powerpc/boot/dts/mpc8377_mds.dts

   1 /*
   2  * MPC8377E MDS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "fsl,mpc8377emds";
  16         compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 serial0 = &serial0;
  24                 serial1 = &serial1;
  25                 pci0 = &pci0;
  26                 pci1 = &pci1;
  27                 pci2 = &pci2;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8377@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;
  38                         i-cache-line-size = <32>;
  39                         d-cache-size = <32768>;
  40                         i-cache-size = <32768>;
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x00000000 0x20000000>;  // 512MB at 0
  50         };
  51
  52         localbus@e0005000 {
  53                 #address-cells = <2>;
  54                 #size-cells = <1>;
  55                 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
  56                 reg = <0xe0005000 0x1000>;
  57                 interrupts = <77 0x8>;
  58                 interrupt-parent = <&ipic>;
  59
  60                 // booting from NOR flash
  61                 ranges = <0 0x0 0xfe000000 0x02000000
  62                           1 0x0 0xf8000000 0x00008000
  63                           3 0x0 0xe0600000 0x00008000>;
  64
  65                 flash@0,0 {
  66                         #address-cells = <1>;
  67                         #size-cells = <1>;
  68                         compatible = "cfi-flash";
  69                         reg = <0 0x0 0x2000000>;
  70                         bank-width = <2>;
  71                         device-width = <1>;
  72
  73                         u-boot@0 {
  74                                 reg = <0x0 0x100000>;
  75                                 read-only;
  76                         };
  77
  78                         fs@100000 {
  79                                 reg = <0x100000 0x800000>;
  80                         };
  81
  82                         kernel@1d00000 {
  83                                 reg = <0x1d00000 0x200000>;
  84                         };
  85
  86                         dtb@1f00000 {
  87                                 reg = <0x1f00000 0x100000>;
  88                         };
  89                 };
  90
  91                 bcsr@1,0 {
  92                         reg = <1 0x0 0x8000>;
  93                         compatible = "fsl,mpc837xmds-bcsr";
  94                 };
  95
  96                 nand@3,0 {
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         compatible = "fsl,mpc8377-fcm-nand",
 100                                      "fsl,elbc-fcm-nand";
 101                         reg = <3 0x0 0x8000>;
 102
 103                         u-boot@0 {
 104                                 reg = <0x0 0x100000>;
 105                                 read-only;
 106                         };
 107
 108                         kernel@100000 {
 109                                 reg = <0x100000 0x300000>;
 110                         };
 111
 112                         fs@400000 {
 113                                 reg = <0x400000 0x1c00000>;
 114                         };
 115                 };
 116         };
 117
 118         soc@e0000000 {
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 device_type = "soc";
 122                 compatible = "simple-bus";
 123                 ranges = <0x0 0xe0000000 0x00100000>;
 124                 reg = <0xe0000000 0x00000200>;
 125                 bus-frequency = <0>;
 126
 127                 wdt@200 {
 128                         compatible = "mpc83xx_wdt";
 129                         reg = <0x200 0x100>;
 130                 };
 131
 132                 sleep-nexus {
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         compatible = "simple-bus";
 136                         sleep = <&pmc 0x0c000000>;
 137                         ranges;
 138
 139                         i2c@3000 {
 140                                 #address-cells = <1>;
 141                                 #size-cells = <0>;
 142                                 cell-index = <0>;
 143                                 compatible = "fsl-i2c";
 144                                 reg = <0x3000 0x100>;
 145                                 interrupts = <14 0x8>;
 146                                 interrupt-parent = <&ipic>;
 147                                 dfsrr;
 148
 149                                 rtc@68 {
 150                                         compatible = "dallas,ds1374";
 151                                         reg = <0x68>;
 152                                         interrupts = <19 0x8>;
 153                                         interrupt-parent = <&ipic>;
 154                                 };
 155                         };
 156
 157                         sdhci@2e000 {
 158                                 compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
 159                                 reg = <0x2e000 0x1000>;
 160                                 interrupts = <42 0x8>;
 161                                 interrupt-parent = <&ipic>;
 162                                 /* Filled in by U-Boot */
 163                                 clock-frequency = <0>;
 164                         };
 165                 };
 166
 167                 i2c@3100 {
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         cell-index = <1>;
 171                         compatible = "fsl-i2c";
 172                         reg = <0x3100 0x100>;
 173                         interrupts = <15 0x8>;
 174                         interrupt-parent = <&ipic>;
 175                         dfsrr;
 176                 };
 177
 178                 spi@7000 {
 179                         cell-index = <0>;
 180                         compatible = "fsl,spi";
 181                         reg = <0x7000 0x1000>;
 182                         interrupts = <16 0x8>;
 183                         interrupt-parent = <&ipic>;
 184                         mode = "cpu";
 185                 };
 186
 187                 usb@23000 {
 188                         compatible = "fsl-usb2-dr";
 189                         reg = <0x23000 0x1000>;
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192                         interrupt-parent = <&ipic>;
 193                         interrupts = <38 0x8>;
 194                         dr_mode = "host";
 195                         phy_type = "ulpi";
 196                         sleep = <&pmc 0x00c00000>;
 197                 };
 198
 199                 enet0: ethernet@24000 {
 200                         #address-cells = <1>;
 201                         #size-cells = <1>;
 202                         cell-index = <0>;
 203                         device_type = "network";
 204                         model = "eTSEC";
 205                         compatible = "gianfar";
 206                         reg = <0x24000 0x1000>;
 207                         ranges = <0x0 0x24000 0x1000>;
 208                         local-mac-address = [ 00 00 00 00 00 00 ];
 209                         interrupts = <32 0x8 33 0x8 34 0x8>;
 210                         phy-connection-type = "mii";
 211                         interrupt-parent = <&ipic>;
 212                         tbi-handle = <&tbi0>;
 213                         phy-handle = <&phy2>;
 214                         sleep = <&pmc 0xc0000000>;
 215                         fsl,magic-packet;
 216
 217                         mdio@520 {
 218                                 #address-cells = <1>;
 219                                 #size-cells = <0>;
 220                                 compatible = "fsl,gianfar-mdio";
 221                                 reg = <0x520 0x20>;
 222
 223                                 phy2: ethernet-phy@2 {
 224                                         interrupt-parent = <&ipic>;
 225                                         interrupts = <17 0x8>;
 226                                         reg = <0x2>;
 227                                         device_type = "ethernet-phy";
 228                                 };
 229
 230                                 phy3: ethernet-phy@3 {
 231                                         interrupt-parent = <&ipic>;
 232                                         interrupts = <18 0x8>;
 233                                         reg = <0x3>;
 234                                         device_type = "ethernet-phy";
 235                                 };
 236
 237                                 tbi0: tbi-phy@11 {
 238                                         reg = <0x11>;
 239                                         device_type = "tbi-phy";
 240                                 };
 241                         };
 242                 };
 243
 244                 enet1: ethernet@25000 {
 245                         #address-cells = <1>;
 246                         #size-cells = <1>;
 247                         cell-index = <1>;
 248                         device_type = "network";
 249                         model = "eTSEC";
 250                         compatible = "gianfar";
 251                         reg = <0x25000 0x1000>;
 252                         ranges = <0x0 0x25000 0x1000>;
 253                         local-mac-address = [ 00 00 00 00 00 00 ];
 254                         interrupts = <35 0x8 36 0x8 37 0x8>;
 255                         phy-connection-type = "mii";
 256                         interrupt-parent = <&ipic>;
 257                         tbi-handle = <&tbi1>;
 258                         phy-handle = <&phy3>;
 259                         sleep = <&pmc 0x30000000>;
 260                         fsl,magic-packet;
 261
 262                         mdio@520 {
 263                                 #address-cells = <1>;
 264                                 #size-cells = <0>;
 265                                 compatible = "fsl,gianfar-tbi";
 266                                 reg = <0x520 0x20>;
 267
 268                                 tbi1: tbi-phy@11 {
 269                                         reg = <0x11>;
 270                                         device_type = "tbi-phy";
 271                                 };
 272                         };
 273                 };
 274
 275                 serial0: serial@4500 {
 276                         cell-index = <0>;
 277                         device_type = "serial";
 278                         compatible = "ns16550";
 279                         reg = <0x4500 0x100>;
 280                         clock-frequency = <0>;
 281                         interrupts = <9 0x8>;
 282                         interrupt-parent = <&ipic>;
 283                 };
 284
 285                 serial1: serial@4600 {
 286                         cell-index = <1>;
 287                         device_type = "serial";
 288                         compatible = "ns16550";
 289                         reg = <0x4600 0x100>;
 290                         clock-frequency = <0>;
 291                         interrupts = <10 0x8>;
 292                         interrupt-parent = <&ipic>;
 293                 };
 294
 295                 dma@82a8 {
 296                         #address-cells = <1>;
 297                         #size-cells = <1>;
 298                         compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
 299                         reg = <0x82a8 4>;
 300                         ranges = <0 0x8100 0x1a8>;
 301                         interrupt-parent = <&ipic>;
 302                         interrupts = <0x47 8>;
 303                         cell-index = <0>;
 304                         dma-channel@0 {
 305                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 306                                 reg = <0 0x80>;
 307                                 cell-index = <0>;
 308                                 interrupt-parent = <&ipic>;
 309                                 interrupts = <0x47 8>;
 310                         };
 311                         dma-channel@80 {
 312                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 313                                 reg = <0x80 0x80>;
 314                                 cell-index = <1>;
 315                                 interrupt-parent = <&ipic>;
 316                                 interrupts = <0x47 8>;
 317                         };
 318                         dma-channel@100 {
 319                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 320                                 reg = <0x100 0x80>;
 321                                 cell-index = <2>;
 322                                 interrupt-parent = <&ipic>;
 323                                 interrupts = <0x47 8>;
 324                         };
 325                         dma-channel@180 {
 326                                 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
 327                                 reg = <0x180 0x28>;
 328                                 cell-index = <3>;
 329                                 interrupt-parent = <&ipic>;
 330                                 interrupts = <0x47 8>;
 331                         };
 332                 };
 333
 334                 crypto@30000 {
 335                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
 336                                      "fsl,sec2.1", "fsl,sec2.0";
 337                         reg = <0x30000 0x10000>;
 338                         interrupts = <11 0x8>;
 339                         interrupt-parent = <&ipic>;
 340                         fsl,num-channels = <4>;
 341                         fsl,channel-fifo-len = <24>;
 342                         fsl,exec-units-mask = <0x9fe>;
 343                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 344                         sleep = <&pmc 0x03000000>;
 345                 };
 346
 347                 sata@18000 {
 348                         compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
 349                         reg = <0x18000 0x1000>;
 350                         interrupts = <44 0x8>;
 351                         interrupt-parent = <&ipic>;
 352                         sleep = <&pmc 0x000000c0>;
 353                 };
 354
 355                 sata@19000 {
 356                         compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
 357                         reg = <0x19000 0x1000>;
 358                         interrupts = <45 0x8>;
 359                         interrupt-parent = <&ipic>;
 360                         sleep = <&pmc 0x00000030>;
 361                 };
 362
 363                 /* IPIC
 364                  * interrupts cell = <intr #, sense>
 365                  * sense values match linux IORESOURCE_IRQ_* defines:
 366                  * sense == 8: Level, low assertion
 367                  * sense == 2: Edge, high-to-low change
 368                  */
 369                 ipic: pic@700 {
 370                         compatible = "fsl,ipic";
 371                         interrupt-controller;
 372                         #address-cells = <0>;
 373                         #interrupt-cells = <2>;
 374                         reg = <0x700 0x100>;
 375                 };
 376
 377                 pmc: power@b00 {
 378                         compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
 379                         reg = <0xb00 0x100 0xa00 0x100>;
 380                         interrupts = <80 0x8>;
 381                         interrupt-parent = <&ipic>;
 382                 };
 383         };
 384
 385         pci0: pci@e0008500 {
 386                 cell-index = <0>;
 387                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 388                 interrupt-map = <
 389
 390                                 /* IDSEL 0x11 */
 391                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 392                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 393                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 394                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 395
 396                                 /* IDSEL 0x12 */
 397                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 398                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 399                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 400                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 401
 402                                 /* IDSEL 0x13 */
 403                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 404                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 405                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 406                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 407
 408                                 /* IDSEL 0x15 */
 409                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 410                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 411                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 412                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 413
 414                                 /* IDSEL 0x16 */
 415                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 416                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 417                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 418                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 419
 420                                 /* IDSEL 0x17 */
 421                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 422                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 423                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 424                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 425
 426                                 /* IDSEL 0x18 */
 427                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 428                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 429                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 430                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 431                 interrupt-parent = <&ipic>;
 432                 interrupts = <66 0x8>;
 433                 bus-range = <0x0 0x0>;
 434                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 435                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 436                           0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
 437                 sleep = <&pmc 0x00010000>;
 438                 clock-frequency = <0>;
 439                 #interrupt-cells = <1>;
 440                 #size-cells = <2>;
 441                 #address-cells = <3>;
 442                 reg = <0xe0008500 0x100         /* internal registers */
 443                        0xe0008300 0x8>;         /* config space access registers */
 444                 compatible = "fsl,mpc8349-pci";
 445                 device_type = "pci";
 446         };
 447
 448         pci1: pcie@e0009000 {
 449                 #address-cells = <3>;
 450                 #size-cells = <2>;
 451                 #interrupt-cells = <1>;
 452                 device_type = "pci";
 453                 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
 454                 reg = <0xe0009000 0x00001000>;
 455                 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
 456                           0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
 457                 bus-range = <0 255>;
 458                 interrupt-map-mask = <0xf800 0 0 7>;
 459                 interrupt-map = <0 0 0 1 &ipic 1 8
 460                                  0 0 0 2 &ipic 1 8
 461                                  0 0 0 3 &ipic 1 8
 462                                  0 0 0 4 &ipic 1 8>;
 463                 sleep = <&pmc 0x00300000>;
 464                 clock-frequency = <0>;
 465
 466                 pcie@0 {
 467                         #address-cells = <3>;
 468                         #size-cells = <2>;
 469                         device_type = "pci";
 470                         reg = <0 0 0 0 0>;
 471                         ranges = <0x02000000 0 0xa8000000
 472                                   0x02000000 0 0xa8000000
 473                                   0 0x10000000
 474                                   0x01000000 0 0x00000000
 475                                   0x01000000 0 0x00000000
 476                                   0 0x00800000>;
 477                 };
 478         };
 479
 480         pci2: pcie@e000a000 {
 481                 #address-cells = <3>;
 482                 #size-cells = <2>;
 483                 #interrupt-cells = <1>;
 484                 device_type = "pci";
 485                 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
 486                 reg = <0xe000a000 0x00001000>;
 487                 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
 488                           0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
 489                 bus-range = <0 255>;
 490                 interrupt-map-mask = <0xf800 0 0 7>;
 491                 interrupt-map = <0 0 0 1 &ipic 2 8
 492                                  0 0 0 2 &ipic 2 8
 493                                  0 0 0 3 &ipic 2 8
 494                                  0 0 0 4 &ipic 2 8>;
 495                 sleep = <&pmc 0x000c0000>;
 496                 clock-frequency = <0>;
 497
 498                 pcie@0 {
 499                         #address-cells = <3>;
 500                         #size-cells = <2>;
 501                         device_type = "pci";
 502                         reg = <0 0 0 0 0>;
 503                         ranges = <0x02000000 0 0xc8000000
 504                                   0x02000000 0 0xc8000000
 505                                   0 0x10000000
 506                                   0x01000000 0 0x00000000
 507                                   0x01000000 0 0x00000000
 508                                   0 0x00800000>;
 509                 };
 510         };
 511 };