arch/powerpc/boot/dts/mpc836x_mds.dts

   1 /*
   2  * MPC8360E EMDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 /*
  14 /memreserve/    00000000 1000000;
  15 */
  16
  17 /dts-v1/;
  18
  19 / {
  20         model = "MPC8360MDS";
  21         compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
  22         #address-cells = <1>;
  23         #size-cells = <1>;
  24
  25         aliases {
  26                 ethernet0 = &enet0;
  27                 ethernet1 = &enet1;
  28                 serial0 = &serial0;
  29                 serial1 = &serial1;
  30                 pci0 = &pci0;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 PowerPC,8360@0 {
  38                         device_type = "cpu";
  39                         reg = <0x0>;
  40                         d-cache-line-size = <32>;       // 32 bytes
  41                         i-cache-line-size = <32>;       // 32 bytes
  42                         d-cache-size = <32768>;         // L1, 32K
  43                         i-cache-size = <32768>;         // L1, 32K
  44                         timebase-frequency = <66000000>;
  45                         bus-frequency = <264000000>;
  46                         clock-frequency = <528000000>;
  47                 };
  48         };
  49
  50         memory {
  51                 device_type = "memory";
  52                 reg = <0x00000000 0x10000000>;
  53         };
  54
  55         localbus@e0005000 {
  56                 #address-cells = <2>;
  57                 #size-cells = <1>;
  58                 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
  59                              "simple-bus";
  60                 reg = <0xe0005000 0xd8>;
  61                 ranges = <0 0 0xfe000000 0x02000000
  62                           1 0 0xf8000000 0x00008000>;
  63
  64                 flash@0,0 {
  65                         compatible = "cfi-flash";
  66                         reg = <0 0 0x2000000>;
  67                         bank-width = <2>;
  68                         device-width = <1>;
  69                 };
  70
  71                 bcsr@1,0 {
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         compatible = "fsl,mpc8360mds-bcsr";
  75                         reg = <1 0 0x8000>;
  76                         ranges = <0 1 0 0x8000>;
  77
  78                         bcsr13: gpio-controller@d {
  79                                 #gpio-cells = <2>;
  80                                 compatible = "fsl,mpc8360mds-bcsr-gpio";
  81                                 reg = <0xd 1>;
  82                                 gpio-controller;
  83                         };
  84                 };
  85         };
  86
  87         soc8360@e0000000 {
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 device_type = "soc";
  91                 compatible = "simple-bus";
  92                 ranges = <0x0 0xe0000000 0x00100000>;
  93                 reg = <0xe0000000 0x00000200>;
  94                 bus-frequency = <264000000>;
  95
  96                 wdt@200 {
  97                         device_type = "watchdog";
  98                         compatible = "mpc83xx_wdt";
  99                         reg = <0x200 0x100>;
 100                 };
 101
 102                 pmc: power@b00 {
 103                         compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
 104                         reg = <0xb00 0x100 0xa00 0x100>;
 105                         interrupts = <80 0x8>;
 106                         interrupt-parent = <&ipic>;
 107                 };
 108
 109                 i2c@3000 {
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         cell-index = <0>;
 113                         compatible = "fsl-i2c";
 114                         reg = <0x3000 0x100>;
 115                         interrupts = <14 0x8>;
 116                         interrupt-parent = <&ipic>;
 117                         dfsrr;
 118
 119                         rtc@68 {
 120                                 compatible = "dallas,ds1374";
 121                                 reg = <0x68>;
 122                         };
 123                 };
 124
 125                 i2c@3100 {
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         cell-index = <1>;
 129                         compatible = "fsl-i2c";
 130                         reg = <0x3100 0x100>;
 131                         interrupts = <15 0x8>;
 132                         interrupt-parent = <&ipic>;
 133                         dfsrr;
 134                 };
 135
 136                 serial0: serial@4500 {
 137                         cell-index = <0>;
 138                         device_type = "serial";
 139                         compatible = "ns16550";
 140                         reg = <0x4500 0x100>;
 141                         clock-frequency = <264000000>;
 142                         interrupts = <9 0x8>;
 143                         interrupt-parent = <&ipic>;
 144                 };
 145
 146                 serial1: serial@4600 {
 147                         cell-index = <1>;
 148                         device_type = "serial";
 149                         compatible = "ns16550";
 150                         reg = <0x4600 0x100>;
 151                         clock-frequency = <264000000>;
 152                         interrupts = <10 0x8>;
 153                         interrupt-parent = <&ipic>;
 154                 };
 155
 156                 dma@82a8 {
 157                         #address-cells = <1>;
 158                         #size-cells = <1>;
 159                         compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
 160                         reg = <0x82a8 4>;
 161                         ranges = <0 0x8100 0x1a8>;
 162                         interrupt-parent = <&ipic>;
 163                         interrupts = <71 8>;
 164                         cell-index = <0>;
 165                         dma-channel@0 {
 166                                 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
 167                                 reg = <0 0x80>;
 168                                 cell-index = <0>;
 169                                 interrupt-parent = <&ipic>;
 170                                 interrupts = <71 8>;
 171                         };
 172                         dma-channel@80 {
 173                                 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
 174                                 reg = <0x80 0x80>;
 175                                 cell-index = <1>;
 176                                 interrupt-parent = <&ipic>;
 177                                 interrupts = <71 8>;
 178                         };
 179                         dma-channel@100 {
 180                                 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
 181                                 reg = <0x100 0x80>;
 182                                 cell-index = <2>;
 183                                 interrupt-parent = <&ipic>;
 184                                 interrupts = <71 8>;
 185                         };
 186                         dma-channel@180 {
 187                                 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
 188                                 reg = <0x180 0x28>;
 189                                 cell-index = <3>;
 190                                 interrupt-parent = <&ipic>;
 191                                 interrupts = <71 8>;
 192                         };
 193                 };
 194
 195                 crypto@30000 {
 196                         compatible = "fsl,sec2.0";
 197                         reg = <0x30000 0x10000>;
 198                         interrupts = <11 0x8>;
 199                         interrupt-parent = <&ipic>;
 200                         fsl,num-channels = <4>;
 201                         fsl,channel-fifo-len = <24>;
 202                         fsl,exec-units-mask = <0x7e>;
 203                         fsl,descriptor-types-mask = <0x01010ebf>;
 204                         sleep = <&pmc 0x03000000>;
 205                 };
 206
 207                 ipic: pic@700 {
 208                         interrupt-controller;
 209                         #address-cells = <0>;
 210                         #interrupt-cells = <2>;
 211                         reg = <0x700 0x100>;
 212                         device_type = "ipic";
 213                 };
 214
 215                 par_io@1400 {
 216                         #address-cells = <1>;
 217                         #size-cells = <1>;
 218                         reg = <0x1400 0x100>;
 219                         ranges = <0 0x1400 0x100>;
 220                         device_type = "par_io";
 221                         num-ports = <7>;
 222
 223                         qe_pio_b: gpio-controller@18 {
 224                                 #gpio-cells = <2>;
 225                                 compatible = "fsl,mpc8360-qe-pario-bank",
 226                                              "fsl,mpc8323-qe-pario-bank";
 227                                 reg = <0x18 0x18>;
 228                                 gpio-controller;
 229                         };
 230
 231                         pio1: ucc_pin@01 {
 232                                 pio-map = <
 233                         /* port  pin  dir  open_drain  assignment  has_irq */
 234                                         0  3  1  0  1  0        /* TxD0 */
 235                                         0  4  1  0  1  0        /* TxD1 */
 236                                         0  5  1  0  1  0        /* TxD2 */
 237                                         0  6  1  0  1  0        /* TxD3 */
 238                                         1  6  1  0  3  0        /* TxD4 */
 239                                         1  7  1  0  1  0        /* TxD5 */
 240                                         1  9  1  0  2  0        /* TxD6 */
 241                                         1  10 1  0  2  0        /* TxD7 */
 242                                         0  9  2  0  1  0        /* RxD0 */
 243                                         0  10 2  0  1  0        /* RxD1 */
 244                                         0  11 2  0  1  0        /* RxD2 */
 245                                         0  12 2  0  1  0        /* RxD3 */
 246                                         0  13 2  0  1  0        /* RxD4 */
 247                                         1  1  2  0  2  0        /* RxD5 */
 248                                         1  0  2  0  2  0        /* RxD6 */
 249                                         1  4  2  0  2  0        /* RxD7 */
 250                                         0  7  1  0  1  0        /* TX_EN */
 251                                         0  8  1  0  1  0        /* TX_ER */
 252                                         0  15 2  0  1  0        /* RX_DV */
 253                                         0  16 2  0  1  0        /* RX_ER */
 254                                         0  0  2  0  1  0        /* RX_CLK */
 255                                         2  9  1  0  3  0        /* GTX_CLK - CLK10 */
 256                                         2  8  2  0  1  0>;      /* GTX125 - CLK9 */
 257                         };
 258                         pio2: ucc_pin@02 {
 259                                 pio-map = <
 260                         /* port  pin  dir  open_drain  assignment  has_irq */
 261                                         0  17 1  0  1  0   /* TxD0 */
 262                                         0  18 1  0  1  0   /* TxD1 */
 263                                         0  19 1  0  1  0   /* TxD2 */
 264                                         0  20 1  0  1  0   /* TxD3 */
 265                                         1  2  1  0  1  0   /* TxD4 */
 266                                         1  3  1  0  2  0   /* TxD5 */
 267                                         1  5  1  0  3  0   /* TxD6 */
 268                                         1  8  1  0  3  0   /* TxD7 */
 269                                         0  23 2  0  1  0   /* RxD0 */
 270                                         0  24 2  0  1  0   /* RxD1 */
 271                                         0  25 2  0  1  0   /* RxD2 */
 272                                         0  26 2  0  1  0   /* RxD3 */
 273                                         0  27 2  0  1  0   /* RxD4 */
 274                                         1  12 2  0  2  0   /* RxD5 */
 275                                         1  13 2  0  3  0   /* RxD6 */
 276                                         1  11 2  0  2  0   /* RxD7 */
 277                                         0  21 1  0  1  0   /* TX_EN */
 278                                         0  22 1  0  1  0   /* TX_ER */
 279                                         0  29 2  0  1  0   /* RX_DV */
 280                                         0  30 2  0  1  0   /* RX_ER */
 281                                         0  31 2  0  1  0   /* RX_CLK */
 282                                         2  2  1  0  2  0   /* GTX_CLK - CLK10 */
 283                                         2  3  2  0  1  0   /* GTX125 - CLK4 */
 284                                         0  1  3  0  2  0   /* MDIO */
 285                                         0  2  1  0  1  0>; /* MDC */
 286                         };
 287
 288                 };
 289         };
 290
 291         qe@e0100000 {
 292                 #address-cells = <1>;
 293                 #size-cells = <1>;
 294                 device_type = "qe";
 295                 compatible = "fsl,qe";
 296                 ranges = <0x0 0xe0100000 0x00100000>;
 297                 reg = <0xe0100000 0x480>;
 298                 brg-frequency = <0>;
 299                 bus-frequency = <396000000>;
 300                 fsl,qe-num-riscs = <2>;
 301                 fsl,qe-num-snums = <28>;
 302
 303                 muram@10000 {
 304                         #address-cells = <1>;
 305                         #size-cells = <1>;
 306                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 307                         ranges = <0x0 0x00010000 0x0000c000>;
 308
 309                         data-only@0 {
 310                                 compatible = "fsl,qe-muram-data",
 311                                              "fsl,cpm-muram-data";
 312                                 reg = <0x0 0xc000>;
 313                         };
 314                 };
 315
 316                 timer@440 {
 317                         compatible = "fsl,mpc8360-qe-gtm",
 318                                      "fsl,qe-gtm", "fsl,gtm";
 319                         reg = <0x440 0x40>;
 320                         clock-frequency = <132000000>;
 321                         interrupts = <12 13 14 15>;
 322                         interrupt-parent = <&qeic>;
 323                 };
 324
 325                 spi@4c0 {
 326                         cell-index = <0>;
 327                         compatible = "fsl,spi";
 328                         reg = <0x4c0 0x40>;
 329                         interrupts = <2>;
 330                         interrupt-parent = <&qeic>;
 331                         mode = "cpu";
 332                 };
 333
 334                 spi@500 {
 335                         cell-index = <1>;
 336                         compatible = "fsl,spi";
 337                         reg = <0x500 0x40>;
 338                         interrupts = <1>;
 339                         interrupt-parent = <&qeic>;
 340                         mode = "cpu";
 341                 };
 342
 343                 usb@6c0 {
 344                         compatible = "fsl,mpc8360-qe-usb",
 345                                      "fsl,mpc8323-qe-usb";
 346                         reg = <0x6c0 0x40 0x8b00 0x100>;
 347                         interrupts = <11>;
 348                         interrupt-parent = <&qeic>;
 349                         fsl,fullspeed-clock = "clk21";
 350                         fsl,lowspeed-clock = "brg9";
 351                         gpios = <&qe_pio_b  2 0   /* USBOE */
 352                                  &qe_pio_b  3 0   /* USBTP */
 353                                  &qe_pio_b  8 0   /* USBTN */
 354                                  &qe_pio_b  9 0   /* USBRP */
 355                                  &qe_pio_b 11 0   /* USBRN */
 356                                  &bcsr13    5 0   /* SPEED */
 357                                  &bcsr13    4 1>; /* POWER */
 358                 };
 359
 360                 enet0: ucc@2000 {
 361                         device_type = "network";
 362                         compatible = "ucc_geth";
 363                         cell-index = <1>;
 364                         reg = <0x2000 0x200>;
 365                         interrupts = <32>;
 366                         interrupt-parent = <&qeic>;
 367                         local-mac-address = [ 00 00 00 00 00 00 ];
 368                         rx-clock-name = "none";
 369                         tx-clock-name = "clk9";
 370                         phy-handle = <&phy0>;
 371                         phy-connection-type = "rgmii-id";
 372                         pio-handle = <&pio1>;
 373                 };
 374
 375                 enet1: ucc@3000 {
 376                         device_type = "network";
 377                         compatible = "ucc_geth";
 378                         cell-index = <2>;
 379                         reg = <0x3000 0x200>;
 380                         interrupts = <33>;
 381                         interrupt-parent = <&qeic>;
 382                         local-mac-address = [ 00 00 00 00 00 00 ];
 383                         rx-clock-name = "none";
 384                         tx-clock-name = "clk4";
 385                         phy-handle = <&phy1>;
 386                         phy-connection-type = "rgmii-id";
 387                         pio-handle = <&pio2>;
 388                 };
 389
 390                 mdio@2120 {
 391                         #address-cells = <1>;
 392                         #size-cells = <0>;
 393                         reg = <0x2120 0x18>;
 394                         compatible = "fsl,ucc-mdio";
 395
 396                         phy0: ethernet-phy@00 {
 397                                 interrupt-parent = <&ipic>;
 398                                 interrupts = <17 0x8>;
 399                                 reg = <0x0>;
 400                                 device_type = "ethernet-phy";
 401                         };
 402                         phy1: ethernet-phy@01 {
 403                                 interrupt-parent = <&ipic>;
 404                                 interrupts = <18 0x8>;
 405                                 reg = <0x1>;
 406                                 device_type = "ethernet-phy";
 407                         };
 408                 };
 409
 410                 qeic: interrupt-controller@80 {
 411                         interrupt-controller;
 412                         compatible = "fsl,qe-ic";
 413                         #address-cells = <0>;
 414                         #interrupt-cells = <1>;
 415                         reg = <0x80 0x80>;
 416                         big-endian;
 417                         interrupts = <32 0x8 33 0x8>; // high:32 low:33
 418                         interrupt-parent = <&ipic>;
 419                 };
 420         };
 421
 422         pci0: pci@e0008500 {
 423                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 424                 interrupt-map = <
 425
 426                                 /* IDSEL 0x11 AD17 */
 427                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
 428                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
 429                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
 430                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
 431
 432                                 /* IDSEL 0x12 AD18 */
 433                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
 434                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
 435                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
 436                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
 437
 438                                 /* IDSEL 0x13 AD19 */
 439                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
 440                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
 441                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
 442                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
 443
 444                                 /* IDSEL 0x15 AD21*/
 445                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
 446                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
 447                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
 448                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
 449
 450                                 /* IDSEL 0x16 AD22*/
 451                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
 452                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
 453                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
 454                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
 455
 456                                 /* IDSEL 0x17 AD23*/
 457                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
 458                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
 459                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
 460                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
 461
 462                                 /* IDSEL 0x18 AD24*/
 463                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
 464                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
 465                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
 466                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
 467                 interrupt-parent = <&ipic>;
 468                 interrupts = <66 0x8>;
 469                 bus-range = <0 0>;
 470                 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 471                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 472                           0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
 473                 clock-frequency = <66666666>;
 474                 #interrupt-cells = <1>;
 475                 #size-cells = <2>;
 476                 #address-cells = <3>;
 477                 reg = <0xe0008500 0x100         /* internal registers */
 478                        0xe0008300 0x8>;         /* config space access registers */
 479                 compatible = "fsl,mpc8349-pci";
 480                 device_type = "pci";
 481                 sleep = <&pmc 0x00010000>;
 482         };
 483 };