arch/powerpc/boot/dts/mpc832x_mds.dts

   1 /*
   2  * MPC8323E EMDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "MPC8323EMDS";
  14         compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #cpus = <1>;
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8323@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <4000>;          // L1, 16K
  29                         i-cache-size = <4000>;          // L1, 16K
  30                         timebase-frequency = <0>;
  31                         bus-frequency = <0>;
  32                         clock-frequency = <0>;
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 08000000>;
  40         };
  41
  42         bcsr@f8000000 {
  43                 device_type = "board-control";
  44                 reg = <f8000000 8000>;
  45         };
  46
  47         soc8323@e0000000 {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 #interrupt-cells = <2>;
  51                 device_type = "soc";
  52                 ranges = <0 e0000000 00100000>;
  53                 reg = <e0000000 00000200>;
  54                 bus-frequency = <7DE2900>;
  55
  56                 wdt@200 {
  57                         device_type = "watchdog";
  58                         compatible = "mpc83xx_wdt";
  59                         reg = <200 100>;
  60                 };
  61
  62                 i2c@3000 {
  63                         device_type = "i2c";
  64                         compatible = "fsl-i2c";
  65                         reg = <3000 100>;
  66                         interrupts = <e 8>;
  67                         interrupt-parent = < &ipic >;
  68                         dfsrr;
  69                 };
  70
  71                 serial@4500 {
  72                         device_type = "serial";
  73                         compatible = "ns16550";
  74                         reg = <4500 100>;
  75                         clock-frequency = <0>;
  76                         interrupts = <9 8>;
  77                         interrupt-parent = < &ipic >;
  78                 };
  79
  80                 serial@4600 {
  81                         device_type = "serial";
  82                         compatible = "ns16550";
  83                         reg = <4600 100>;
  84                         clock-frequency = <0>;
  85                         interrupts = <a 8>;
  86                         interrupt-parent = < &ipic >;
  87                 };
  88
  89                 crypto@30000 {
  90                         device_type = "crypto";
  91                         model = "SEC2";
  92                         compatible = "talitos";
  93                         reg = <30000 7000>;
  94                         interrupts = <b 8>;
  95                         interrupt-parent = < &ipic >;
  96                         /* Rev. 2.2 */
  97                         num-channels = <1>;
  98                         channel-fifo-len = <18>;
  99                         exec-units-mask = <0000004c>;
 100                         descriptor-types-mask = <0122003f>;
 101                 };
 102
 103                 pci@8500 {
 104                         interrupt-map-mask = <f800 0 0 7>;
 105                         interrupt-map = <
 106                                         /* IDSEL 0x11 AD17 */
 107                                          8800 0 0 1 &ipic 14 8
 108                                          8800 0 0 2 &ipic 15 8
 109                                          8800 0 0 3 &ipic 16 8
 110                                          8800 0 0 4 &ipic 17 8
 111
 112                                         /* IDSEL 0x12 AD18 */
 113                                          9000 0 0 1 &ipic 16 8
 114                                          9000 0 0 2 &ipic 17 8
 115                                          9000 0 0 3 &ipic 14 8
 116                                          9000 0 0 4 &ipic 15 8
 117
 118                                         /* IDSEL 0x13 AD19 */
 119                                          9800 0 0 1 &ipic 17 8
 120                                          9800 0 0 2 &ipic 14 8
 121                                          9800 0 0 3 &ipic 15 8
 122                                          9800 0 0 4 &ipic 16 8
 123
 124                                         /* IDSEL 0x15 AD21*/
 125                                          a800 0 0 1 &ipic 14 8
 126                                          a800 0 0 2 &ipic 15 8
 127                                          a800 0 0 3 &ipic 16 8
 128                                          a800 0 0 4 &ipic 17 8
 129
 130                                         /* IDSEL 0x16 AD22*/
 131                                          b000 0 0 1 &ipic 17 8
 132                                          b000 0 0 2 &ipic 14 8
 133                                          b000 0 0 3 &ipic 15 8
 134                                          b000 0 0 4 &ipic 16 8
 135
 136                                         /* IDSEL 0x17 AD23*/
 137                                          b800 0 0 1 &ipic 16 8
 138                                          b800 0 0 2 &ipic 17 8
 139                                          b800 0 0 3 &ipic 14 8
 140                                          b800 0 0 4 &ipic 15 8
 141
 142                                         /* IDSEL 0x18 AD24*/
 143                                          c000 0 0 1 &ipic 15 8
 144                                          c000 0 0 2 &ipic 16 8
 145                                          c000 0 0 3 &ipic 17 8
 146                                          c000 0 0 4 &ipic 14 8>;
 147                         interrupt-parent = < &ipic >;
 148                         interrupts = <42 8>;
 149                         bus-range = <0 0>;
 150                         ranges = <02000000 0 a0000000 90000000 0 10000000
 151                                   42000000 0 80000000 80000000 0 10000000
 152                                   01000000 0 00000000 d0000000 0 00100000>;
 153                         clock-frequency = <0>;
 154                         #interrupt-cells = <1>;
 155                         #size-cells = <2>;
 156                         #address-cells = <3>;
 157                         reg = <8500 100>;
 158                         compatible = "83xx";
 159                         device_type = "pci";
 160                 };
 161
 162                 ipic: pic@700 {
 163                         interrupt-controller;
 164                         #address-cells = <0>;
 165                         #interrupt-cells = <2>;
 166                         reg = <700 100>;
 167                         built-in;
 168                         device_type = "ipic";
 169                 };
 170
 171                 par_io@1400 {
 172                         reg = <1400 100>;
 173                         device_type = "par_io";
 174                         num-ports = <7>;
 175
 176                         pio3: ucc_pin@03 {
 177                                 pio-map = <
 178                         /* port  pin  dir  open_drain  assignment  has_irq */
 179                                         3  4  3  0  2  0  /* MDIO */
 180                                         3  5  1  0  2  0  /* MDC */
 181                                         0  d  2  0  1  0        /* RX_CLK (CLK9) */
 182                                         3 18  2  0  1  0        /* TX_CLK (CLK10) */
 183                                         1  1  1  0  1  0        /* TxD1 */
 184                                         1  0  1  0  1  0        /* TxD0 */
 185                                         1  1  1  0  1  0        /* TxD1 */
 186                                         1  2  1  0  1  0        /* TxD2 */
 187                                         1  3  1  0  1  0        /* TxD3 */
 188                                         1  4  2  0  1  0        /* RxD0 */
 189                                         1  5  2  0  1  0        /* RxD1 */
 190                                         1  6  2  0  1  0        /* RxD2 */
 191                                         1  7  2  0  1  0        /* RxD3 */
 192                                         1  8  2  0  1  0        /* RX_ER */
 193                                         1  9  1  0  1  0        /* TX_ER */
 194                                         1  a  2  0  1  0        /* RX_DV */
 195                                         1  b  2  0  1  0        /* COL */
 196                                         1  c  1  0  1  0        /* TX_EN */
 197                                         1  d  2  0  1  0>;/* CRS */
 198                         };
 199                         pio4: ucc_pin@04 {
 200                                 pio-map = <
 201                         /* port  pin  dir  open_drain  assignment  has_irq */
 202                                         3 1f  2  0  1  0        /* RX_CLK (CLK7) */
 203                                         3  6  2  0  1  0        /* TX_CLK (CLK8) */
 204                                         1 12  1  0  1  0        /* TxD0 */
 205                                         1 13  1  0  1  0        /* TxD1 */
 206                                         1 14  1  0  1  0        /* TxD2 */
 207                                         1 15  1  0  1  0        /* TxD3 */
 208                                         1 16  2  0  1  0        /* RxD0 */
 209                                         1 17  2  0  1  0        /* RxD1 */
 210                                         1 18  2  0  1  0        /* RxD2 */
 211                                         1 19  2  0  1  0        /* RxD3 */
 212                                         1 1a  2  0  1  0        /* RX_ER */
 213                                         1 1b  1  0  1  0        /* TX_ER */
 214                                         1 1c  2  0  1  0        /* RX_DV */
 215                                         1 1d  2  0  1  0        /* COL */
 216                                         1 1e  1  0  1  0        /* TX_EN */
 217                                         1 1f  2  0  1  0>;/* CRS */
 218                         };
 219                 };
 220         };
 221
 222         qe@e0100000 {
 223                 #address-cells = <1>;
 224                 #size-cells = <1>;
 225                 device_type = "qe";
 226                 model = "QE";
 227                 ranges = <0 e0100000 00100000>;
 228                 reg = <e0100000 480>;
 229                 brg-frequency = <0>;
 230                 bus-frequency = <BCD3D80>;
 231
 232                 muram@10000 {
 233                         device_type = "muram";
 234                         ranges = <0 00010000 00004000>;
 235
 236                         data-only@0 {
 237                                 reg = <0 4000>;
 238                         };
 239                 };
 240
 241                 spi@4c0 {
 242                         device_type = "spi";
 243                         compatible = "fsl_spi";
 244                         reg = <4c0 40>;
 245                         interrupts = <2>;
 246                         interrupt-parent = < &qeic >;
 247                         mode = "cpu";
 248                 };
 249
 250                 spi@500 {
 251                         device_type = "spi";
 252                         compatible = "fsl_spi";
 253                         reg = <500 40>;
 254                         interrupts = <1>;
 255                         interrupt-parent = < &qeic >;
 256                         mode = "cpu";
 257                 };
 258
 259                 usb@6c0 {
 260                         device_type = "usb";
 261                         compatible = "qe_udc";
 262                         reg = <6c0 40 8B00 100>;
 263                         interrupts = <b>;
 264                         interrupt-parent = < &qeic >;
 265                         mode = "slave";
 266                 };
 267
 268                 ucc@2200 {
 269                         device_type = "network";
 270                         compatible = "ucc_geth";
 271                         model = "UCC";
 272                         device-id = <3>;
 273                         reg = <2200 200>;
 274                         interrupts = <22>;
 275                         interrupt-parent = < &qeic >;
 276                         mac-address = [ 00 04 9f 00 23 23 ];
 277                         rx-clock = <19>;
 278                         tx-clock = <1a>;
 279                         phy-handle = < &phy3 >;
 280                         pio-handle = < &pio3 >;
 281                 };
 282
 283                 ucc@3200 {
 284                         device_type = "network";
 285                         compatible = "ucc_geth";
 286                         model = "UCC";
 287                         device-id = <4>;
 288                         reg = <3000 200>;
 289                         interrupts = <23>;
 290                         interrupt-parent = < &qeic >;
 291                         mac-address = [ 00 11 22 33 44 55 ];
 292                         rx-clock = <17>;
 293                         tx-clock = <18>;
 294                         phy-handle = < &phy4 >;
 295                         pio-handle = < &pio4 >;
 296                 };
 297
 298                 mdio@2320 {
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         reg = <2320 18>;
 302                         device_type = "mdio";
 303                         compatible = "ucc_geth_phy";
 304
 305                         phy3: ethernet-phy@03 {
 306                                 interrupt-parent = < &ipic >;
 307                                 interrupts = <11 8>;
 308                                 reg = <3>;
 309                                 device_type = "ethernet-phy";
 310                                 interface = <3>; //ENET_100_MII
 311                         };
 312                         phy4: ethernet-phy@04 {
 313                                 interrupt-parent = < &ipic >;
 314                                 interrupts = <12 8>;
 315                                 reg = <4>;
 316                                 device_type = "ethernet-phy";
 317                                 interface = <3>;
 318                         };
 319                 };
 320
 321                 qeic: qeic@80 {
 322                         interrupt-controller;
 323                         device_type = "qeic";
 324                         #address-cells = <0>;
 325                         #interrupt-cells = <1>;
 326                         reg = <80 80>;
 327                         built-in;
 328                         big-endian;
 329                         interrupts = <20 8 21 8>; //high:32 low:33
 330                         interrupt-parent = < &ipic >;
 331                 };
 332         };
 333 };