arch/powerpc/boot/dts/mpc5200b.dtsi

   1 /*
   2  * base MPC5200b Device Tree Source
   3  *
   4  * Copyright (C) 2010 SecretLab
   5  * Grant Likely <grant@secretlab.ca>
   6  * John Bonesio <bones@secretlab.ca>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 /dts-v1/;
  15
  16 / {
  17         model = "fsl,mpc5200b";
  18         compatible = "fsl,mpc5200b";
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         interrupt-parent = <&mpc5200_pic>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 powerpc: PowerPC,5200@0 {
  28                         device_type = "cpu";
  29                         reg = <0>;
  30                         d-cache-line-size = <32>;
  31                         i-cache-line-size = <32>;
  32                         d-cache-size = <0x4000>;        // L1, 16K
  33                         i-cache-size = <0x4000>;        // L1, 16K
  34                         timebase-frequency = <0>;       // from bootloader
  35                         bus-frequency = <0>;            // from bootloader
  36                         clock-frequency = <0>;          // from bootloader
  37                 };
  38         };
  39
  40         memory: memory {
  41                 device_type = "memory";
  42                 reg = <0x00000000 0x04000000>;  // 64MB
  43         };
  44
  45         soc: soc5200@f0000000 {
  46                 #address-cells = <1>;
  47                 #size-cells = <1>;
  48                 compatible = "fsl,mpc5200b-immr";
  49                 ranges = <0 0xf0000000 0x0000c000>;
  50                 reg = <0xf0000000 0x00000100>;
  51                 bus-frequency = <0>;            // from bootloader
  52                 system-frequency = <0>;         // from bootloader
  53
  54                 cdm@200 {
  55                         compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
  56                         reg = <0x200 0x38>;
  57                 };
  58
  59                 mpc5200_pic: interrupt-controller@500 {
  60                         // 5200 interrupts are encoded into two levels;
  61                         interrupt-controller;
  62                         #interrupt-cells = <3>;
  63                         compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
  64                         reg = <0x500 0x80>;
  65                 };
  66
  67                 timer@600 {     // General Purpose Timer
  68                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  69                         reg = <0x600 0x10>;
  70                         interrupts = <1 9 0>;
  71                 };
  72
  73                 timer@610 {     // General Purpose Timer
  74                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  75                         reg = <0x610 0x10>;
  76                         interrupts = <1 10 0>;
  77                 };
  78
  79                 timer@620 {     // General Purpose Timer
  80                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  81                         reg = <0x620 0x10>;
  82                         interrupts = <1 11 0>;
  83                 };
  84
  85                 timer@630 {     // General Purpose Timer
  86                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  87                         reg = <0x630 0x10>;
  88                         interrupts = <1 12 0>;
  89                 };
  90
  91                 timer@640 {     // General Purpose Timer
  92                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  93                         reg = <0x640 0x10>;
  94                         interrupts = <1 13 0>;
  95                 };
  96
  97                 timer@650 {     // General Purpose Timer
  98                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
  99                         reg = <0x650 0x10>;
 100                         interrupts = <1 14 0>;
 101                 };
 102
 103                 timer@660 {     // General Purpose Timer
 104                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 105                         reg = <0x660 0x10>;
 106                         interrupts = <1 15 0>;
 107                 };
 108
 109                 timer@670 {     // General Purpose Timer
 110                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
 111                         reg = <0x670 0x10>;
 112                         interrupts = <1 16 0>;
 113                 };
 114
 115                 rtc@800 {       // Real time clock
 116                         compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
 117                         reg = <0x800 0x100>;
 118                         interrupts = <1 5 0 1 6 0>;
 119                 };
 120
 121                 can@900 {
 122                         compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
 123                         interrupts = <2 17 0>;
 124                         reg = <0x900 0x80>;
 125                 };
 126
 127                 can@980 {
 128                         compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
 129                         interrupts = <2 18 0>;
 130                         reg = <0x980 0x80>;
 131                 };
 132
 133                 gpio_simple: gpio@b00 {
 134                         compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
 135                         reg = <0xb00 0x40>;
 136                         interrupts = <1 7 0>;
 137                         gpio-controller;
 138                         #gpio-cells = <2>;
 139                 };
 140
 141                 gpio_wkup: gpio@c00 {
 142                         compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
 143                         reg = <0xc00 0x40>;
 144                         interrupts = <1 8 0 0 3 0>;
 145                         gpio-controller;
 146                         #gpio-cells = <2>;
 147                 };
 148
 149                 spi@f00 {
 150                         compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
 151                         reg = <0xf00 0x20>;
 152                         interrupts = <2 13 0 2 14 0>;
 153                 };
 154
 155                 usb: usb@1000 {
 156                         compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
 157                         reg = <0x1000 0xff>;
 158                         interrupts = <2 6 0>;
 159                 };
 160
 161                 dma-controller@1200 {
 162                         compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
 163                         reg = <0x1200 0x80>;
 164                         interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
 165                                       3 4 0  3 5 0  3 6 0  3 7 0
 166                                       3 8 0  3 9 0  3 10 0  3 11 0
 167                                       3 12 0  3 13 0  3 14 0  3 15 0>;
 168                 };
 169
 170                 xlb@1f00 {
 171                         compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
 172                         reg = <0x1f00 0x100>;
 173                 };
 174
 175                 psc1: psc@2000 {                // PSC1
 176                         compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
 177                         reg = <0x2000 0x100>;
 178                         interrupts = <2 1 0>;
 179                 };
 180
 181                 psc2: psc@2200 {                // PSC2
 182                         compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
 183                         reg = <0x2200 0x100>;
 184                         interrupts = <2 2 0>;
 185                 };
 186
 187                 psc3: psc@2400 {                // PSC3
 188                         compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
 189                         reg = <0x2400 0x100>;
 190                         interrupts = <2 3 0>;
 191                 };
 192
 193                 psc4: psc@2600 {                // PSC4
 194                         compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
 195                         reg = <0x2600 0x100>;
 196                         interrupts = <2 11 0>;
 197                 };
 198
 199                 psc5: psc@2800 {                // PSC5
 200                         compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
 201                         reg = <0x2800 0x100>;
 202                         interrupts = <2 12 0>;
 203                 };
 204
 205                 psc6: psc@2c00 {                // PSC6
 206                         compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
 207                         reg = <0x2c00 0x100>;
 208                         interrupts = <2 4 0>;
 209                 };
 210
 211                 eth0: ethernet@3000 {
 212                         compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
 213                         reg = <0x3000 0x400>;
 214                         local-mac-address = [ 00 00 00 00 00 00 ];
 215                         interrupts = <2 5 0>;
 216                 };
 217
 218                 mdio@3000 {
 219                         #address-cells = <1>;
 220                         #size-cells = <0>;
 221                         compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
 222                         reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
 223                         interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
 224                 };
 225
 226                 ata@3a00 {
 227                         compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
 228                         reg = <0x3a00 0x100>;
 229                         interrupts = <2 7 0>;
 230                 };
 231
 232                 i2c@3d00 {
 233                         #address-cells = <1>;
 234                         #size-cells = <0>;
 235                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
 236                         reg = <0x3d00 0x40>;
 237                         interrupts = <2 15 0>;
 238                 };
 239
 240                 i2c@3d40 {
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
 244                         reg = <0x3d40 0x40>;
 245                         interrupts = <2 16 0>;
 246                 };
 247
 248                 sram@8000 {
 249                         compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
 250                         reg = <0x8000 0x4000>;
 251                 };
 252         };
 253
 254         pci: pci@f0000d00 {
 255                 #interrupt-cells = <1>;
 256                 #size-cells = <2>;
 257                 #address-cells = <3>;
 258                 device_type = "pci";
 259                 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
 260                 reg = <0xf0000d00 0x100>;
 261                 // interrupt-map-mask = need to add
 262                 // interrupt-map = need to add
 263                 clock-frequency = <0>; // From boot loader
 264                 interrupts = <2 8 0 2 9 0 2 10 0>;
 265                 bus-range = <0 0>;
 266                 // ranges = need to add
 267         };
 268
 269         localbus: localbus {
 270                 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
 271                 #address-cells = <2>;
 272                 #size-cells = <1>;
 273                 ranges = <0 0 0xfc000000 0x2000000>;
 274         };
 275 };