arch/mn10300/proc-mn2ws0050/include/proc/nand-regs.h

   1 /* NAND flash interface register definitions
   2  *
   3  * Copyright (C) 2008-2009 Panasonic Corporation
   4  * All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _PROC_NAND_REGS_H_
  17 #define _PROC_NAND_REGS_H_
  18
  19 /* command register */
  20 #define FCOMMAND_0              __SYSREG(0xd8f00000, u8) /* fcommand[24:31] */
  21 #define FCOMMAND_1              __SYSREG(0xd8f00001, u8) /* fcommand[16:23] */
  22 #define FCOMMAND_2              __SYSREG(0xd8f00002, u8) /* fcommand[8:15] */
  23 #define FCOMMAND_3              __SYSREG(0xd8f00003, u8) /* fcommand[0:7] */
  24
  25 /* for dma 16 byte trans, use FCOMMAND2 register */
  26 #define FCOMMAND2_0             __SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */
  27 #define FCOMMAND2_1             __SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */
  28 #define FCOMMAND2_2             __SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */
  29 #define FCOMMAND2_3             __SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */
  30
  31 #define FCOMMAND_FIEN           0x80            /* nand flash I/F enable */
  32 #define FCOMMAND_BW_8BIT        0x00            /* 8bit bus width */
  33 #define FCOMMAND_BW_16BIT       0x40            /* 16bit bus width */
  34 #define FCOMMAND_BLOCKSZ_SMALL  0x00            /* small block */
  35 #define FCOMMAND_BLOCKSZ_LARGE  0x20            /* large block */
  36 #define FCOMMAND_DMASTART       0x10            /* dma start */
  37 #define FCOMMAND_RYBY           0x08            /* ready/busy flag */
  38 #define FCOMMAND_RYBYINTMSK     0x04            /* mask ready/busy interrupt */
  39 #define FCOMMAND_XFWP           0x02            /* write protect enable */
  40 #define FCOMMAND_XFCE           0x01            /* flash device disable */
  41 #define FCOMMAND_SEQKILL        0x10            /* stop seq-read */
  42 #define FCOMMAND_ANUM           0x07            /* address cycle */
  43 #define FCOMMAND_ANUM_NONE      0x00            /* address cycle none */
  44 #define FCOMMAND_ANUM_1CYC      0x01            /* address cycle 1cycle */
  45 #define FCOMMAND_ANUM_2CYC      0x02            /* address cycle 2cycle */
  46 #define FCOMMAND_ANUM_3CYC      0x03            /* address cycle 3cycle */
  47 #define FCOMMAND_ANUM_4CYC      0x04            /* address cycle 4cycle */
  48 #define FCOMMAND_ANUM_5CYC      0x05            /* address cycle 5cycle */
  49 #define FCOMMAND_FCMD_READ0     0x00            /* read1 command */
  50 #define FCOMMAND_FCMD_SEQIN     0x80            /* page program 1st command */
  51 #define FCOMMAND_FCMD_PAGEPROG  0x10            /* page program 2nd command */
  52 #define FCOMMAND_FCMD_RESET     0xff            /* reset command */
  53 #define FCOMMAND_FCMD_ERASE1    0x60            /* erase 1st command */
  54 #define FCOMMAND_FCMD_ERASE2    0xd0            /* erase 2nd command */
  55 #define FCOMMAND_FCMD_STATUS    0x70            /* read status command */
  56 #define FCOMMAND_FCMD_READID    0x90            /* read id command */
  57 #define FCOMMAND_FCMD_READOOB   0x50            /* read3 command */
  58 /* address register */
  59 #define FADD                    __SYSREG(0xd8f00004, u32)
  60 /* address register 2 */
  61 #define FADD2                   __SYSREG(0xd8f00008, u32)
  62 /* error judgement register */
  63 #define FJUDGE                  __SYSREG(0xd8f0000c, u32)
  64 #define FJUDGE_NOERR            0x0             /* no error */
  65 #define FJUDGE_1BITERR          0x1             /* 1bit error in data area */
  66 #define FJUDGE_PARITYERR        0x2             /* parity error */
  67 #define FJUDGE_UNCORRECTABLE    0x3             /* uncorrectable error */
  68 #define FJUDGE_ERRJDG_MSK       0x3             /* mask of judgement result */
  69 /* 1st ECC store register */
  70 #define FECC11                  __SYSREG(0xd8f00010, u32)
  71 /* 2nd ECC store register */
  72 #define FECC12                  __SYSREG(0xd8f00014, u32)
  73 /* 3rd ECC store register */
  74 #define FECC21                  __SYSREG(0xd8f00018, u32)
  75 /* 4th ECC store register */
  76 #define FECC22                  __SYSREG(0xd8f0001c, u32)
  77 /* 5th ECC store register */
  78 #define FECC31                  __SYSREG(0xd8f00020, u32)
  79 /* 6th ECC store register */
  80 #define FECC32                  __SYSREG(0xd8f00024, u32)
  81 /* 7th ECC store register */
  82 #define FECC41                  __SYSREG(0xd8f00028, u32)
  83 /* 8th ECC store register */
  84 #define FECC42                  __SYSREG(0xd8f0002c, u32)
  85 /* data register */
  86 #define FDATA                   __SYSREG(0xd8f00030, u32)
  87 /* access pulse register */
  88 #define FPWS                    __SYSREG(0xd8f00100, u32)
  89 #define FPWS_PWS1W_2CLK         0x00000000 /* write pulse width 1clock */
  90 #define FPWS_PWS1W_3CLK         0x01000000 /* write pulse width 2clock */
  91 #define FPWS_PWS1W_4CLK         0x02000000 /* write pulse width 4clock */
  92 #define FPWS_PWS1W_5CLK         0x03000000 /* write pulse width 5clock */
  93 #define FPWS_PWS1W_6CLK         0x04000000 /* write pulse width 6clock */
  94 #define FPWS_PWS1W_7CLK         0x05000000 /* write pulse width 7clock */
  95 #define FPWS_PWS1W_8CLK         0x06000000 /* write pulse width 8clock */
  96 #define FPWS_PWS1R_3CLK         0x00010000 /* read pulse width 3clock */
  97 #define FPWS_PWS1R_4CLK         0x00020000 /* read pulse width 4clock */
  98 #define FPWS_PWS1R_5CLK         0x00030000 /* read pulse width 5clock */
  99 #define FPWS_PWS1R_6CLK         0x00040000 /* read pulse width 6clock */
 100 #define FPWS_PWS1R_7CLK         0x00050000 /* read pulse width 7clock */
 101 #define FPWS_PWS1R_8CLK         0x00060000 /* read pulse width 8clock */
 102 #define FPWS_PWS2W_2CLK         0x00000100 /* write pulse interval 2clock */
 103 #define FPWS_PWS2W_3CLK         0x00000200 /* write pulse interval 3clock */
 104 #define FPWS_PWS2W_4CLK         0x00000300 /* write pulse interval 4clock */
 105 #define FPWS_PWS2W_5CLK         0x00000400 /* write pulse interval 5clock */
 106 #define FPWS_PWS2W_6CLK         0x00000500 /* write pulse interval 6clock */
 107 #define FPWS_PWS2R_2CLK         0x00000001 /* read pulse interval 2clock */
 108 #define FPWS_PWS2R_3CLK         0x00000002 /* read pulse interval 3clock */
 109 #define FPWS_PWS2R_4CLK         0x00000003 /* read pulse interval 4clock */
 110 #define FPWS_PWS2R_5CLK         0x00000004 /* read pulse interval 5clock */
 111 #define FPWS_PWS2R_6CLK         0x00000005 /* read pulse interval 6clock */
 112 /* command register 2 */
 113 #define FCOMMAND2               __SYSREG(0xd8f00110, u32)
 114 /* transfer frequency register */
 115 #define FNUM                    __SYSREG(0xd8f00114, u32)
 116 #define FSDATA_ADDR             0xd8f00400
 117 /* active data register */
 118 #define FSDATA                  __SYSREG(FSDATA_ADDR, u32)
 119
 120 #endif /* _PROC_NAND_REGS_H_ */