arch/mips/sibyte/common/sb_tbprof.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License
   4  * as published by the Free Software Foundation; either version 2
   5  * of the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  15  *
  16  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
  17  * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
  18  * Copyright (C) 2007 MIPS Technologies, Inc.
  19  *    written by Ralf Baechle <ralf@linux-mips.org>
  20  */
  21
  22 #undef DEBUG
  23
  24 #include <linux/device.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/slab.h>
  31 #include <linux/smp_lock.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/fs.h>
  34 #include <linux/errno.h>
  35 #include <linux/wait.h>
  36 #include <asm/io.h>
  37 #include <asm/sibyte/sb1250.h>
  38
  39 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  40 #include <asm/sibyte/bcm1480_regs.h>
  41 #include <asm/sibyte/bcm1480_scd.h>
  42 #include <asm/sibyte/bcm1480_int.h>
  43 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  44 #include <asm/sibyte/sb1250_regs.h>
  45 #include <asm/sibyte/sb1250_scd.h>
  46 #include <asm/sibyte/sb1250_int.h>
  47 #else
  48 #error invalid SiByte UART configuation
  49 #endif
  50
  51 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  52 #undef K_INT_TRACE_FREEZE
  53 #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
  54 #undef K_INT_PERF_CNT
  55 #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
  56 #endif
  57
  58 #include <asm/system.h>
  59 #include <asm/uaccess.h>
  60
  61 #define SBPROF_TB_MAJOR 240
  62
  63 typedef u64 tb_sample_t[6*256];
  64
  65 enum open_status {
  66         SB_CLOSED,
  67         SB_OPENING,
  68         SB_OPEN
  69 };
  70
  71 struct sbprof_tb {
  72         wait_queue_head_t       tb_sync;
  73         wait_queue_head_t       tb_read;
  74         struct mutex            lock;
  75         enum open_status        open;
  76         tb_sample_t             *sbprof_tbbuf;
  77         int                     next_tb_sample;
  78
  79         volatile int            tb_enable;
  80         volatile int            tb_armed;
  81
  82 };
  83
  84 static struct sbprof_tb sbp;
  85
  86 #define MAX_SAMPLE_BYTES (24*1024*1024)
  87 #define MAX_TBSAMPLE_BYTES (12*1024*1024)
  88
  89 #define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
  90 #define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
  91 #define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
  92
  93 /* ioctls */
  94 #define SBPROF_ZBSTART          _IOW('s', 0, int)
  95 #define SBPROF_ZBSTOP           _IOW('s', 1, int)
  96 #define SBPROF_ZBWAITFULL       _IOW('s', 2, int)
  97
  98 /*
  99  * Routines for using 40-bit SCD cycle counter
 100  *
 101  * Client responsible for either handling interrupts or making sure
 102  * the cycles counter never saturates, e.g., by doing
 103  * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
 104  */
 105
 106 /*
 107  * Configures SCD counter 0 to count ZCLKs starting from val;
 108  * Configures SCD counters1,2,3 to count nothing.
 109  * Must not be called while gathering ZBbus profiles.
 110  */
 111
 112 #define zclk_timer_init(val) \
 113   __asm__ __volatile__ (".set push;" \
 114                         ".set mips64;" \
 115                         "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
 116                         "sd   %0, 0x10($8);"   /* write val to counter0 */ \
 117                         "sd   %1, 0($8);"      /* config counter0 for zclks*/ \
 118                         ".set pop" \
 119                         : /* no outputs */ \
 120                                                      /* enable, counter0 */ \
 121                         : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
 122                         : /* modifies */ "$8" )
 123
 124
 125 /* Reads SCD counter 0 and puts result in value
 126    unsigned long long val; */
 127 #define zclk_get(val) \
 128   __asm__ __volatile__ (".set push;" \
 129                         ".set mips64;" \
 130                         "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
 131                         "ld   %0, 0x10($8);"   /* write val to counter0 */ \
 132                         ".set pop" \
 133                         : /* outputs */ "=r"(val) \
 134                         : /* inputs */ \
 135                         : /* modifies */ "$8" )
 136
 137 #define DEVNAME "sb_tbprof"
 138
 139 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
 140
 141 /*
 142  * Support for ZBbus sampling using the trace buffer
 143  *
 144  * We use the SCD performance counter interrupt, caused by a Zclk counter
 145  * overflow, to trigger the start of tracing.
 146  *
 147  * We set the trace buffer to sample everything and freeze on
 148  * overflow.
 149  *
 150  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
 151  *
 152  */
 153
 154 static u64 tb_period;
 155
 156 static void arm_tb(void)
 157 {
 158         u64 scdperfcnt;
 159         u64 next = (1ULL << 40) - tb_period;
 160         u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
 161
 162         /*
 163          * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
 164          * trigger start of trace.  XXX vary sampling period
 165          */
 166         __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
 167         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 168
 169         /*
 170          * Unfortunately, in Pass 2 we must clear all counters to knock down
 171          * a previous interrupt request.  This means that bus profiling
 172          * requires ALL of the SCD perf counters.
 173          */
 174 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 175         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
 176                                                 /* keep counters 0,2,3,4,5,6,7 as is */
 177                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 178                      IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
 179         __raw_writeq(
 180                      M_SPC_CFG_ENABLE |         /* enable counting */
 181                      M_SPC_CFG_CLEAR |          /* clear all counters */
 182                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 183                      IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
 184 #else
 185         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
 186                                                 /* keep counters 0,2,3 as is */
 187                      M_SPC_CFG_ENABLE |         /* enable counting */
 188                      M_SPC_CFG_CLEAR |          /* clear all counters */
 189                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 190                      IOADDR(A_SCD_PERF_CNT_CFG));
 191 #endif
 192         __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
 193         /* Reset the trace buffer */
 194         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 195 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
 196         /* XXXKW may want to expose control to the data-collector */
 197         tb_options |= M_SCD_TRACE_CFG_FORCECNT;
 198 #endif
 199         __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
 200         sbp.tb_armed = 1;
 201 }
 202
 203 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
 204 {
 205         int i;
 206
 207         pr_debug(DEVNAME ": tb_intr\n");
 208
 209         if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
 210                 /* XXX should use XKPHYS to make writes bypass L2 */
 211                 u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
 212                 /* Read out trace */
 213                 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
 214                              IOADDR(A_SCD_TRACE_CFG));
 215                 __asm__ __volatile__ ("sync" : : : "memory");
 216                 /* Loop runs backwards because bundles are read out in reverse order */
 217                 for (i = 256 * 6; i > 0; i -= 6) {
 218                         /* Subscripts decrease to put bundle in the order */
 219                         /*   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
 220                         p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 221                         /* read t2 hi */
 222                         p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 223                         /* read t2 lo */
 224                         p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 225                         /* read t1 hi */
 226                         p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 227                         /* read t1 lo */
 228                         p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 229                         /* read t0 hi */
 230                         p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 231                         /* read t0 lo */
 232                 }
 233                 if (!sbp.tb_enable) {
 234                         pr_debug(DEVNAME ": tb_intr shutdown\n");
 235                         __raw_writeq(M_SCD_TRACE_CFG_RESET,
 236                                      IOADDR(A_SCD_TRACE_CFG));
 237                         sbp.tb_armed = 0;
 238                         wake_up_interruptible(&sbp.tb_sync);
 239                 } else {
 240                         /* knock down current interrupt and get another one later */
 241                         arm_tb();
 242                 }
 243         } else {
 244                 /* No more trace buffer samples */
 245                 pr_debug(DEVNAME ": tb_intr full\n");
 246                 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 247                 sbp.tb_armed = 0;
 248                 if (!sbp.tb_enable)
 249                         wake_up_interruptible(&sbp.tb_sync);
 250                 wake_up_interruptible(&sbp.tb_read);
 251         }
 252         return IRQ_HANDLED;
 253 }
 254
 255 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
 256 {
 257         printk(DEVNAME ": unexpected pc_intr");
 258         return IRQ_NONE;
 259 }
 260
 261 /*
 262  * Requires: Already called zclk_timer_init with a value that won't
 263  *           saturate 40 bits.  No subsequent use of SCD performance counters
 264  *           or trace buffer.
 265  */
 266
 267 static int sbprof_zbprof_start(struct file *filp)
 268 {
 269         u64 scdperfcnt;
 270         int err;
 271
 272         if (xchg(&sbp.tb_enable, 1))
 273                 return -EBUSY;
 274
 275         pr_debug(DEVNAME ": starting\n");
 276
 277         sbp.next_tb_sample = 0;
 278         filp->f_pos = 0;
 279
 280         err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
 281                           DEVNAME " trace freeze", &sbp);
 282         if (err)
 283                 return -EBUSY;
 284
 285         /* Make sure there isn't a perf-cnt interrupt waiting */
 286         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 287         /* Disable and clear counters, override SRC_1 */
 288         __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
 289                      M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
 290                      IOADDR(A_SCD_PERF_CNT_CFG));
 291
 292         /*
 293          * We grab this interrupt to prevent others from trying to use
 294          * it, even though we don't want to service the interrupts
 295          * (they only feed into the trace-on-interrupt mechanism)
 296          */
 297         if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
 298                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 299                 return -EBUSY;
 300         }
 301
 302         /*
 303          * I need the core to mask these, but the interrupt mapper to
 304          *  pass them through.  I am exploiting my knowledge that
 305          *  cp0_status masks out IP[5]. krw
 306          */
 307 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 308         __raw_writeq(K_BCM1480_INT_MAP_I3,
 309                      IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
 310                             ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
 311 #else
 312         __raw_writeq(K_INT_MAP_I3,
 313                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 314                             (K_INT_PERF_CNT << 3)));
 315 #endif
 316
 317         /* Initialize address traps */
 318         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
 319         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
 320         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
 321         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
 322
 323         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
 324         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
 325         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
 326         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
 327
 328         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
 329         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
 330         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
 331         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 332
 333         /* Initialize Trace Event 0-7 */
 334         /*                              when interrupt  */
 335         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
 336         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
 337         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
 338         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
 339         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
 340         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
 341         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
 342         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
 343
 344         /* Initialize Trace Sequence 0-7 */
 345         /*                                   Start on event 0 (interrupt) */
 346         __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
 347                      IOADDR(A_SCD_TRACE_SEQUENCE_0));
 348         /*                        dsamp when d used | asamp when a used */
 349         __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
 350                      K_SCD_TRSEQ_TRIGGER_ALL,
 351                      IOADDR(A_SCD_TRACE_SEQUENCE_1));
 352         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
 353         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
 354         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
 355         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
 356         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
 357         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
 358
 359         /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
 360 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 361         __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
 362                      IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
 363 #else
 364         __raw_writeq(1ULL << K_INT_PERF_CNT,
 365                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
 366 #endif
 367         arm_tb();
 368
 369         pr_debug(DEVNAME ": done starting\n");
 370
 371         return 0;
 372 }
 373
 374 static int sbprof_zbprof_stop(void)
 375 {
 376         int err = 0;
 377
 378         pr_debug(DEVNAME ": stopping\n");
 379
 380         if (sbp.tb_enable) {
 381                 /*
 382                  * XXXKW there is a window here where the intr handler may run,
 383                  * see the disable, and do the wake_up before this sleep
 384                  * happens.
 385                  */
 386                 pr_debug(DEVNAME ": wait for disarm\n");
 387                 err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
 388                 pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
 389
 390                 if (err)
 391                         return err;
 392
 393                 sbp.tb_enable = 0;
 394                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 395                 free_irq(K_INT_PERF_CNT, &sbp);
 396         }
 397
 398         pr_debug(DEVNAME ": done stopping\n");
 399
 400         return err;
 401 }
 402
 403 static int sbprof_tb_open(struct inode *inode, struct file *filp)
 404 {
 405         int minor;
 406         int err = 0;
 407
 408         lock_kernel();
 409         minor = iminor(inode);
 410         if (minor != 0) {
 411                 err = -ENODEV;
 412                 goto out;
 413         }
 414
 415         if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED) {
 416                 err = -EBUSY;
 417                 goto out;
 418         }
 419
 420         memset(&sbp, 0, sizeof(struct sbprof_tb));
 421         sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
 422         if (!sbp.sbprof_tbbuf) {
 423                 err = -ENOMEM;
 424                 goto out;
 425         }
 426         memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
 427         init_waitqueue_head(&sbp.tb_sync);
 428         init_waitqueue_head(&sbp.tb_read);
 429         mutex_init(&sbp.lock);
 430
 431         sbp.open = SB_OPEN;
 432
 433   out:
 434         unlock_kernel();
 435         return err;
 436 }
 437
 438 static int sbprof_tb_release(struct inode *inode, struct file *filp)
 439 {
 440         int minor;
 441
 442         minor = iminor(inode);
 443         if (minor != 0 || !sbp.open)
 444                 return -ENODEV;
 445
 446         mutex_lock(&sbp.lock);
 447
 448         if (sbp.tb_armed || sbp.tb_enable)
 449                 sbprof_zbprof_stop();
 450
 451         vfree(sbp.sbprof_tbbuf);
 452         sbp.open = 0;
 453
 454         mutex_unlock(&sbp.lock);
 455
 456         return 0;
 457 }
 458
 459 static ssize_t sbprof_tb_read(struct file *filp, char *buf,
 460                               size_t size, loff_t *offp)
 461 {
 462         int cur_sample, sample_off, cur_count, sample_left;
 463         char *src;
 464         int   count   =  0;
 465         char *dest    =  buf;
 466         long  cur_off = *offp;
 467
 468         if (!access_ok(VERIFY_WRITE, buf, size))
 469                 return -EFAULT;
 470
 471         mutex_lock(&sbp.lock);
 472
 473         count = 0;
 474         cur_sample = cur_off / TB_SAMPLE_SIZE;
 475         sample_off = cur_off % TB_SAMPLE_SIZE;
 476         sample_left = TB_SAMPLE_SIZE - sample_off;
 477
 478         while (size && (cur_sample < sbp.next_tb_sample)) {
 479                 int err;
 480
 481                 cur_count = size < sample_left ? size : sample_left;
 482                 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
 483                 err = __copy_to_user(dest, src, cur_count);
 484                 if (err) {
 485                         *offp = cur_off + cur_count - err;
 486                         mutex_unlock(&sbp.lock);
 487                         return err;
 488                 }
 489                 pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
 490                          cur_sample, cur_count);
 491                 size -= cur_count;
 492                 sample_left -= cur_count;
 493                 if (!sample_left) {
 494                         cur_sample++;
 495                         sample_off = 0;
 496                         sample_left = TB_SAMPLE_SIZE;
 497                 } else {
 498                         sample_off += cur_count;
 499                 }
 500                 cur_off += cur_count;
 501                 dest += cur_count;
 502                 count += cur_count;
 503         }
 504         *offp = cur_off;
 505         mutex_unlock(&sbp.lock);
 506
 507         return count;
 508 }
 509
 510 static long sbprof_tb_ioctl(struct file *filp,
 511                             unsigned int command,
 512                             unsigned long arg)
 513 {
 514         int err = 0;
 515
 516         switch (command) {
 517         case SBPROF_ZBSTART:
 518                 mutex_lock(&sbp.lock);
 519                 err = sbprof_zbprof_start(filp);
 520                 mutex_unlock(&sbp.lock);
 521                 break;
 522
 523         case SBPROF_ZBSTOP:
 524                 mutex_lock(&sbp.lock);
 525                 err = sbprof_zbprof_stop();
 526                 mutex_unlock(&sbp.lock);
 527                 break;
 528
 529         case SBPROF_ZBWAITFULL: {
 530                 err = wait_event_interruptible(sbp.tb_read, TB_FULL);
 531                 if (err)
 532                         break;
 533
 534                 err = put_user(TB_FULL, (int *) arg);
 535                 break;
 536         }
 537
 538         default:
 539                 err = -EINVAL;
 540                 break;
 541         }
 542
 543         return err;
 544 }
 545
 546 static const struct file_operations sbprof_tb_fops = {
 547         .owner          = THIS_MODULE,
 548         .open           = sbprof_tb_open,
 549         .release        = sbprof_tb_release,
 550         .read           = sbprof_tb_read,
 551         .unlocked_ioctl = sbprof_tb_ioctl,
 552         .compat_ioctl   = sbprof_tb_ioctl,
 553         .mmap           = NULL,
 554 };
 555
 556 static struct class *tb_class;
 557 static struct device *tb_dev;
 558
 559 static int __init sbprof_tb_init(void)
 560 {
 561         struct device *dev;
 562         struct class *tbc;
 563         int err;
 564
 565         if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
 566                 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
 567                        SBPROF_TB_MAJOR);
 568                 return -EIO;
 569         }
 570
 571         tbc = class_create(THIS_MODULE, "sb_tracebuffer");
 572         if (IS_ERR(tbc)) {
 573                 err = PTR_ERR(tbc);
 574                 goto out_chrdev;
 575         }
 576
 577         tb_class = tbc;
 578
 579         dev = device_create_drvdata(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0),
 580                                     NULL, "tb");
 581         if (IS_ERR(dev)) {
 582                 err = PTR_ERR(dev);
 583                 goto out_class;
 584         }
 585         tb_dev = dev;
 586
 587         sbp.open = 0;
 588         tb_period = zbbus_mhz * 10000LL;
 589         pr_info(DEVNAME ": initialized - tb_period = %lld\n",
 590                 (long long) tb_period);
 591         return 0;
 592
 593 out_class:
 594         class_destroy(tb_class);
 595 out_chrdev:
 596         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 597
 598         return err;
 599 }
 600
 601 static void __exit sbprof_tb_cleanup(void)
 602 {
 603         device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
 604         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 605         class_destroy(tb_class);
 606 }
 607
 608 module_init(sbprof_tb_init);
 609 module_exit(sbprof_tb_cleanup);
 610
 611 MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
 612 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
 613 MODULE_LICENSE("GPL");