arch/mips/oprofile/op_model_loongson2.c

   1 /*
   2  * Loongson2 performance counter driver for oprofile
   3  *
   4  * Copyright (C) 2009 Lemote Inc.
   5  * Author: Yanhua <yanh@lemote.com>
   6  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/oprofile.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <loongson.h>                   /* LOONGSON2_PERFCNT_IRQ */
  17 #include "op_impl.h"
  18
  19 #define LOONGSON2_CPU_TYPE      "mips/loongson2"
  20
  21 #define LOONGSON2_PERFCNT_OVERFLOW              (1ULL   << 31)
  22
  23 #define LOONGSON2_PERFCTRL_EXL                  (1UL    <<  0)
  24 #define LOONGSON2_PERFCTRL_KERNEL               (1UL    <<  1)
  25 #define LOONGSON2_PERFCTRL_SUPERVISOR           (1UL    <<  2)
  26 #define LOONGSON2_PERFCTRL_USER                 (1UL    <<  3)
  27 #define LOONGSON2_PERFCTRL_ENABLE               (1UL    <<  4)
  28 #define LOONGSON2_PERFCTRL_EVENT(idx, event) \
  29         (((event) & 0x0f) << ((idx) ? 9 : 5))
  30
  31 #define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
  32 #define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
  33 #define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
  34 #define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
  35
  36 static struct loongson2_register_config {
  37         unsigned int ctrl;
  38         unsigned long long reset_counter1;
  39         unsigned long long reset_counter2;
  40         int cnt1_enabled, cnt2_enabled;
  41 } reg;
  42
  43 static char *oprofid = "LoongsonPerf";
  44 static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
  45
  46 static void loongson2_reg_setup(struct op_counter_config *cfg)
  47 {
  48         unsigned int ctrl = 0;
  49
  50         reg.reset_counter1 = 0;
  51         reg.reset_counter2 = 0;
  52
  53         /*
  54          * Compute the performance counter ctrl word.
  55          * For now, count kernel and user mode.
  56          */
  57         if (cfg[0].enabled) {
  58                 ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event);
  59                 reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
  60         }
  61
  62         if (cfg[1].enabled) {
  63                 ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event);
  64                 reg.reset_counter2 = 0x80000000ULL - cfg[1].count;
  65         }
  66
  67         if (cfg[0].enabled || cfg[1].enabled) {
  68                 ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE;
  69                 if (cfg[0].kernel || cfg[1].kernel)
  70                         ctrl |= LOONGSON2_PERFCTRL_KERNEL;
  71                 if (cfg[0].user || cfg[1].user)
  72                         ctrl |= LOONGSON2_PERFCTRL_USER;
  73         }
  74
  75         reg.ctrl = ctrl;
  76
  77         reg.cnt1_enabled = cfg[0].enabled;
  78         reg.cnt2_enabled = cfg[1].enabled;
  79 }
  80
  81 static void loongson2_cpu_setup(void *args)
  82 {
  83         write_c0_perfcnt((reg.reset_counter2 << 32) | reg.reset_counter1);
  84 }
  85
  86 static void loongson2_cpu_start(void *args)
  87 {
  88         /* Start all counters on current CPU */
  89         if (reg.cnt1_enabled || reg.cnt2_enabled)
  90                 write_c0_perfctrl(reg.ctrl);
  91 }
  92
  93 static void loongson2_cpu_stop(void *args)
  94 {
  95         /* Stop all counters on current CPU */
  96         write_c0_perfctrl(0);
  97         memset(&reg, 0, sizeof(reg));
  98 }
  99
 100 static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
 101 {
 102         uint64_t counter, counter1, counter2;
 103         struct pt_regs *regs = get_irq_regs();
 104         int enabled;
 105
 106         /* Check whether the irq belongs to me */
 107         enabled = read_c0_perfctrl() & LOONGSON2_PERFCTRL_ENABLE;
 108         if (!enabled)
 109                 return IRQ_NONE;
 110         enabled = reg.cnt1_enabled | reg.cnt2_enabled;
 111         if (!enabled)
 112                 return IRQ_NONE;
 113
 114         counter = read_c0_perfcnt();
 115         counter1 = counter & 0xffffffff;
 116         counter2 = counter >> 32;
 117
 118         if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
 119                 if (reg.cnt1_enabled)
 120                         oprofile_add_sample(regs, 0);
 121                 counter1 = reg.reset_counter1;
 122         }
 123         if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
 124                 if (reg.cnt2_enabled)
 125                         oprofile_add_sample(regs, 1);
 126                 counter2 = reg.reset_counter2;
 127         }
 128
 129         write_c0_perfcnt((counter2 << 32) | counter1);
 130
 131         return IRQ_HANDLED;
 132 }
 133
 134 static int __init loongson2_init(void)
 135 {
 136         return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
 137                            IRQF_SHARED, "Perfcounter", oprofid);
 138 }
 139
 140 static void loongson2_exit(void)
 141 {
 142         write_c0_perfctrl(0);
 143         free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
 144 }
 145
 146 struct op_mips_model op_model_loongson2_ops = {
 147         .reg_setup = loongson2_reg_setup,
 148         .cpu_setup = loongson2_cpu_setup,
 149         .init = loongson2_init,
 150         .exit = loongson2_exit,
 151         .cpu_start = loongson2_cpu_start,
 152         .cpu_stop = loongson2_cpu_stop,
 153         .cpu_type = LOONGSON2_CPU_TYPE,
 154         .num_counters = 2
 155 };