arch/mips/mm/tlb-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
   8  * Carsten Langgaard, carstenl@mips.com
   9  * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/sched.h>
  13 #include <linux/mm.h>
  14
  15 #include <asm/cpu.h>
  16 #include <asm/bootinfo.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/system.h>
  20
  21 extern void build_tlb_refill_handler(void);
  22
  23 /*
  24  * Make sure all entries differ.  If they're not different
  25  * MIPS32 will take revenge ...
  26  */
  27 #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
  28
  29 /* Atomicity and interruptability */
  30 #ifdef CONFIG_MIPS_MT_SMTC
  31
  32 #include <asm/smtc.h>
  33 #include <asm/mipsmtregs.h>
  34
  35 #define ENTER_CRITICAL(flags) \
  36         { \
  37         unsigned int mvpflags; \
  38         local_irq_save(flags);\
  39         mvpflags = dvpe()
  40 #define EXIT_CRITICAL(flags) \
  41         evpe(mvpflags); \
  42         local_irq_restore(flags); \
  43         }
  44 #else
  45
  46 #define ENTER_CRITICAL(flags) local_irq_save(flags)
  47 #define EXIT_CRITICAL(flags) local_irq_restore(flags)
  48
  49 #endif /* CONFIG_MIPS_MT_SMTC */
  50
  51 void local_flush_tlb_all(void)
  52 {
  53         unsigned long flags;
  54         unsigned long old_ctx;
  55         int entry;
  56
  57         ENTER_CRITICAL(flags);
  58         /* Save old context and create impossible VPN2 value */
  59         old_ctx = read_c0_entryhi();
  60         write_c0_entrylo0(0);
  61         write_c0_entrylo1(0);
  62
  63         entry = read_c0_wired();
  64
  65         /* Blast 'em all away. */
  66         while (entry < current_cpu_data.tlbsize) {
  67                 /* Make sure all entries differ. */
  68                 write_c0_entryhi(UNIQUE_ENTRYHI(entry));
  69                 write_c0_index(entry);
  70                 mtc0_tlbw_hazard();
  71                 tlb_write_indexed();
  72                 entry++;
  73         }
  74         tlbw_use_hazard();
  75         write_c0_entryhi(old_ctx);
  76         EXIT_CRITICAL(flags);
  77 }
  78
  79 /* All entries common to a mm share an asid.  To effectively flush
  80    these entries, we just bump the asid. */
  81 void local_flush_tlb_mm(struct mm_struct *mm)
  82 {
  83         int cpu;
  84
  85         preempt_disable();
  86
  87         cpu = smp_processor_id();
  88
  89         if (cpu_context(cpu, mm) != 0) {
  90                 drop_mmu_context(mm, cpu);
  91         }
  92
  93         preempt_enable();
  94 }
  95
  96 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
  97         unsigned long end)
  98 {
  99         struct mm_struct *mm = vma->vm_mm;
 100         int cpu = smp_processor_id();
 101
 102         if (cpu_context(cpu, mm) != 0) {
 103                 unsigned long flags;
 104                 int size;
 105
 106                 ENTER_CRITICAL(flags);
 107                 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 108                 size = (size + 1) >> 1;
 109                 local_irq_save(flags);
 110                 if (size <= current_cpu_data.tlbsize/2) {
 111                         int oldpid = read_c0_entryhi();
 112                         int newpid = cpu_asid(cpu, mm);
 113
 114                         start &= (PAGE_MASK << 1);
 115                         end += ((PAGE_SIZE << 1) - 1);
 116                         end &= (PAGE_MASK << 1);
 117                         while (start < end) {
 118                                 int idx;
 119
 120                                 write_c0_entryhi(start | newpid);
 121                                 start += (PAGE_SIZE << 1);
 122                                 mtc0_tlbw_hazard();
 123                                 tlb_probe();
 124                                 tlb_probe_hazard();
 125                                 idx = read_c0_index();
 126                                 write_c0_entrylo0(0);
 127                                 write_c0_entrylo1(0);
 128                                 if (idx < 0)
 129                                         continue;
 130                                 /* Make sure all entries differ. */
 131                                 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
 132                                 mtc0_tlbw_hazard();
 133                                 tlb_write_indexed();
 134                         }
 135                         tlbw_use_hazard();
 136                         write_c0_entryhi(oldpid);
 137                 } else {
 138                         drop_mmu_context(mm, cpu);
 139                 }
 140                 EXIT_CRITICAL(flags);
 141         }
 142 }
 143
 144 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
 145 {
 146         unsigned long flags;
 147         int size;
 148
 149         ENTER_CRITICAL(flags);
 150         size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
 151         size = (size + 1) >> 1;
 152         if (size <= current_cpu_data.tlbsize / 2) {
 153                 int pid = read_c0_entryhi();
 154
 155                 start &= (PAGE_MASK << 1);
 156                 end += ((PAGE_SIZE << 1) - 1);
 157                 end &= (PAGE_MASK << 1);
 158
 159                 while (start < end) {
 160                         int idx;
 161
 162                         write_c0_entryhi(start);
 163                         start += (PAGE_SIZE << 1);
 164                         mtc0_tlbw_hazard();
 165                         tlb_probe();
 166                         tlb_probe_hazard();
 167                         idx = read_c0_index();
 168                         write_c0_entrylo0(0);
 169                         write_c0_entrylo1(0);
 170                         if (idx < 0)
 171                                 continue;
 172                         /* Make sure all entries differ. */
 173                         write_c0_entryhi(UNIQUE_ENTRYHI(idx));
 174                         mtc0_tlbw_hazard();
 175                         tlb_write_indexed();
 176                 }
 177                 tlbw_use_hazard();
 178                 write_c0_entryhi(pid);
 179         } else {
 180                 local_flush_tlb_all();
 181         }
 182         EXIT_CRITICAL(flags);
 183 }
 184
 185 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 186 {
 187         int cpu = smp_processor_id();
 188
 189         if (cpu_context(cpu, vma->vm_mm) != 0) {
 190                 unsigned long flags;
 191                 int oldpid, newpid, idx;
 192
 193                 newpid = cpu_asid(cpu, vma->vm_mm);
 194                 page &= (PAGE_MASK << 1);
 195                 ENTER_CRITICAL(flags);
 196                 oldpid = read_c0_entryhi();
 197                 write_c0_entryhi(page | newpid);
 198                 mtc0_tlbw_hazard();
 199                 tlb_probe();
 200                 tlb_probe_hazard();
 201                 idx = read_c0_index();
 202                 write_c0_entrylo0(0);
 203                 write_c0_entrylo1(0);
 204                 if (idx < 0)
 205                         goto finish;
 206                 /* Make sure all entries differ. */
 207                 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
 208                 mtc0_tlbw_hazard();
 209                 tlb_write_indexed();
 210                 tlbw_use_hazard();
 211
 212         finish:
 213                 write_c0_entryhi(oldpid);
 214                 EXIT_CRITICAL(flags);
 215         }
 216 }
 217
 218 /*
 219  * This one is only used for pages with the global bit set so we don't care
 220  * much about the ASID.
 221  */
 222 void local_flush_tlb_one(unsigned long page)
 223 {
 224         unsigned long flags;
 225         int oldpid, idx;
 226
 227         ENTER_CRITICAL(flags);
 228         oldpid = read_c0_entryhi();
 229         page &= (PAGE_MASK << 1);
 230         write_c0_entryhi(page);
 231         mtc0_tlbw_hazard();
 232         tlb_probe();
 233         tlb_probe_hazard();
 234         idx = read_c0_index();
 235         write_c0_entrylo0(0);
 236         write_c0_entrylo1(0);
 237         if (idx >= 0) {
 238                 /* Make sure all entries differ. */
 239                 write_c0_entryhi(UNIQUE_ENTRYHI(idx));
 240                 mtc0_tlbw_hazard();
 241                 tlb_write_indexed();
 242                 tlbw_use_hazard();
 243         }
 244         write_c0_entryhi(oldpid);
 245
 246         EXIT_CRITICAL(flags);
 247 }
 248
 249 /*
 250  * We will need multiple versions of update_mmu_cache(), one that just
 251  * updates the TLB with the new pte(s), and another which also checks
 252  * for the R4k "end of page" hardware bug and does the needy.
 253  */
 254 void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 255 {
 256         unsigned long flags;
 257         pgd_t *pgdp;
 258         pud_t *pudp;
 259         pmd_t *pmdp;
 260         pte_t *ptep;
 261         int idx, pid;
 262
 263         /*
 264          * Handle debugger faulting in for debugee.
 265          */
 266         if (current->active_mm != vma->vm_mm)
 267                 return;
 268
 269         ENTER_CRITICAL(flags);
 270
 271         pid = read_c0_entryhi() & ASID_MASK;
 272         address &= (PAGE_MASK << 1);
 273         write_c0_entryhi(address | pid);
 274         pgdp = pgd_offset(vma->vm_mm, address);
 275         mtc0_tlbw_hazard();
 276         tlb_probe();
 277         tlb_probe_hazard();
 278         pudp = pud_offset(pgdp, address);
 279         pmdp = pmd_offset(pudp, address);
 280         idx = read_c0_index();
 281         ptep = pte_offset_map(pmdp, address);
 282
 283 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
 284         write_c0_entrylo0(ptep->pte_high);
 285         ptep++;
 286         write_c0_entrylo1(ptep->pte_high);
 287 #else
 288         write_c0_entrylo0(pte_val(*ptep++) >> 6);
 289         write_c0_entrylo1(pte_val(*ptep) >> 6);
 290 #endif
 291         mtc0_tlbw_hazard();
 292         if (idx < 0)
 293                 tlb_write_random();
 294         else
 295                 tlb_write_indexed();
 296         tlbw_use_hazard();
 297         EXIT_CRITICAL(flags);
 298 }
 299
 300 #if 0
 301 static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma,
 302                                        unsigned long address, pte_t pte)
 303 {
 304         unsigned long flags;
 305         unsigned int asid;
 306         pgd_t *pgdp;
 307         pmd_t *pmdp;
 308         pte_t *ptep;
 309         int idx;
 310
 311         ENTER_CRITICAL(flags);
 312         address &= (PAGE_MASK << 1);
 313         asid = read_c0_entryhi() & ASID_MASK;
 314         write_c0_entryhi(address | asid);
 315         pgdp = pgd_offset(vma->vm_mm, address);
 316         mtc0_tlbw_hazard();
 317         tlb_probe();
 318         tlb_probe_hazard();
 319         pmdp = pmd_offset(pgdp, address);
 320         idx = read_c0_index();
 321         ptep = pte_offset_map(pmdp, address);
 322         write_c0_entrylo0(pte_val(*ptep++) >> 6);
 323         write_c0_entrylo1(pte_val(*ptep) >> 6);
 324         mtc0_tlbw_hazard();
 325         if (idx < 0)
 326                 tlb_write_random();
 327         else
 328                 tlb_write_indexed();
 329         tlbw_use_hazard();
 330         EXIT_CRITICAL(flags);
 331 }
 332 #endif
 333
 334 void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
 335         unsigned long entryhi, unsigned long pagemask)
 336 {
 337         unsigned long flags;
 338         unsigned long wired;
 339         unsigned long old_pagemask;
 340         unsigned long old_ctx;
 341
 342         ENTER_CRITICAL(flags);
 343         /* Save old context and create impossible VPN2 value */
 344         old_ctx = read_c0_entryhi();
 345         old_pagemask = read_c0_pagemask();
 346         wired = read_c0_wired();
 347         write_c0_wired(wired + 1);
 348         write_c0_index(wired);
 349         tlbw_use_hazard();      /* What is the hazard here? */
 350         write_c0_pagemask(pagemask);
 351         write_c0_entryhi(entryhi);
 352         write_c0_entrylo0(entrylo0);
 353         write_c0_entrylo1(entrylo1);
 354         mtc0_tlbw_hazard();
 355         tlb_write_indexed();
 356         tlbw_use_hazard();
 357
 358         write_c0_entryhi(old_ctx);
 359         tlbw_use_hazard();      /* What is the hazard here? */
 360         write_c0_pagemask(old_pagemask);
 361         local_flush_tlb_all();
 362         EXIT_CRITICAL(flags);
 363 }
 364
 365 /*
 366  * Used for loading TLB entries before trap_init() has started, when we
 367  * don't actually want to add a wired entry which remains throughout the
 368  * lifetime of the system
 369  */
 370
 371 static int temp_tlb_entry __initdata;
 372
 373 __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
 374                                unsigned long entryhi, unsigned long pagemask)
 375 {
 376         int ret = 0;
 377         unsigned long flags;
 378         unsigned long wired;
 379         unsigned long old_pagemask;
 380         unsigned long old_ctx;
 381
 382         ENTER_CRITICAL(flags);
 383         /* Save old context and create impossible VPN2 value */
 384         old_ctx = read_c0_entryhi();
 385         old_pagemask = read_c0_pagemask();
 386         wired = read_c0_wired();
 387         if (--temp_tlb_entry < wired) {
 388                 printk(KERN_WARNING
 389                        "No TLB space left for add_temporary_entry\n");
 390                 ret = -ENOSPC;
 391                 goto out;
 392         }
 393
 394         write_c0_index(temp_tlb_entry);
 395         write_c0_pagemask(pagemask);
 396         write_c0_entryhi(entryhi);
 397         write_c0_entrylo0(entrylo0);
 398         write_c0_entrylo1(entrylo1);
 399         mtc0_tlbw_hazard();
 400         tlb_write_indexed();
 401         tlbw_use_hazard();
 402
 403         write_c0_entryhi(old_ctx);
 404         write_c0_pagemask(old_pagemask);
 405 out:
 406         EXIT_CRITICAL(flags);
 407         return ret;
 408 }
 409
 410 static void __init probe_tlb(unsigned long config)
 411 {
 412         struct cpuinfo_mips *c = &current_cpu_data;
 413         unsigned int reg;
 414
 415         /*
 416          * If this isn't a MIPS32 / MIPS64 compliant CPU.  Config 1 register
 417          * is not supported, we assume R4k style.  Cpu probing already figured
 418          * out the number of tlb entries.
 419          */
 420         if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
 421                 return;
 422 #ifdef CONFIG_MIPS_MT_SMTC
 423         /*
 424          * If TLB is shared in SMTC system, total size already
 425          * has been calculated and written into cpu_data tlbsize
 426          */
 427         if((smtc_status & SMTC_TLB_SHARED) == SMTC_TLB_SHARED)
 428                 return;
 429 #endif /* CONFIG_MIPS_MT_SMTC */
 430
 431         reg = read_c0_config1();
 432         if (!((config >> 7) & 3))
 433                 panic("No TLB present");
 434
 435         c->tlbsize = ((reg >> 25) & 0x3f) + 1;
 436 }
 437
 438 static int __initdata ntlb = 0;
 439 static int __init set_ntlb(char *str)
 440 {
 441         get_option(&str, &ntlb);
 442         return 1;
 443 }
 444
 445 __setup("ntlb=", set_ntlb);
 446
 447 void __init tlb_init(void)
 448 {
 449         unsigned int config = read_c0_config();
 450
 451         /*
 452          * You should never change this register:
 453          *   - On R4600 1.7 the tlbp never hits for pages smaller than
 454          *     the value in the c0_pagemask register.
 455          *   - The entire mm handling assumes the c0_pagemask register to
 456          *     be set for 4kb pages.
 457          */
 458         probe_tlb(config);
 459         write_c0_pagemask(PM_DEFAULT_MASK);
 460         write_c0_wired(0);
 461         write_c0_framemask(0);
 462         temp_tlb_entry = current_cpu_data.tlbsize - 1;
 463
 464         /* From this point on the ARC firmware is dead.  */
 465         local_flush_tlb_all();
 466
 467         /* Did I tell you that ARC SUCKS?  */
 468
 469         if (ntlb) {
 470                 if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
 471                         int wired = current_cpu_data.tlbsize - ntlb;
 472                         write_c0_wired(wired);
 473                         write_c0_index(wired-1);
 474                         printk ("Restricting TLB to %d entries\n", ntlb);
 475                 } else
 476                         printk("Ignoring invalid argument ntlb=%d\n", ntlb);
 477         }
 478
 479         build_tlb_refill_handler();
 480 }