arch/mips/kernel/irq-msc01.c

   1 /*
   2  * This program is free software; you can redistribute  it and/or modify it
   3  * under  the terms of  the GNU General  Public License as published by the
   4  * Free Software Foundation;  either version 2 of the  License, or (at your
   5  * option) any later version.
   6  *
   7  * Copyright (c) 2004 MIPS Inc
   8  * Author: chris@mips.com
   9  *
  10  * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
  11  */
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/sched.h>
  15 #include <linux/kernel_stat.h>
  16 #include <asm/io.h>
  17 #include <asm/irq.h>
  18 #include <asm/msc01_ic.h>
  19 #include <asm/traps.h>
  20
  21 static unsigned long _icctrl_msc;
  22 #define MSC01_IC_REG_BASE       _icctrl_msc
  23
  24 #define MSCIC_WRITE(reg, data)  do { *(volatile u32 *)(reg) = data; } while (0)
  25 #define MSCIC_READ(reg, data)   do { data = *(volatile u32 *)(reg); } while (0)
  26
  27 static unsigned int irq_base;
  28
  29 /* mask off an interrupt */
  30 static inline void mask_msc_irq(struct irq_data *d)
  31 {
  32         unsigned int irq = d->irq;
  33
  34         if (irq < (irq_base + 32))
  35                 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
  36         else
  37                 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
  38 }
  39
  40 /* unmask an interrupt */
  41 static inline void unmask_msc_irq(struct irq_data *d)
  42 {
  43         unsigned int irq = d->irq;
  44
  45         if (irq < (irq_base + 32))
  46                 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
  47         else
  48                 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
  49 }
  50
  51 /*
  52  * Masks and ACKs an IRQ
  53  */
  54 static void level_mask_and_ack_msc_irq(struct irq_data *d)
  55 {
  56         unsigned int irq = d->irq;
  57
  58         mask_msc_irq(d);
  59         if (!cpu_has_veic)
  60                 MSCIC_WRITE(MSC01_IC_EOI, 0);
  61         /* This actually needs to be a call into platform code */
  62         smtc_im_ack_irq(irq);
  63 }
  64
  65 /*
  66  * Masks and ACKs an IRQ
  67  */
  68 static void edge_mask_and_ack_msc_irq(struct irq_data *d)
  69 {
  70         unsigned int irq = d->irq;
  71
  72         mask_msc_irq(d);
  73         if (!cpu_has_veic)
  74                 MSCIC_WRITE(MSC01_IC_EOI, 0);
  75         else {
  76                 u32 r;
  77                 MSCIC_READ(MSC01_IC_SUP+irq*8, r);
  78                 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
  79                 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
  80         }
  81         smtc_im_ack_irq(irq);
  82 }
  83
  84 /*
  85  * Interrupt handler for interrupts coming from SOC-it.
  86  */
  87 void ll_msc_irq(void)
  88 {
  89         unsigned int irq;
  90
  91         /* read the interrupt vector register */
  92         MSCIC_READ(MSC01_IC_VEC, irq);
  93         if (irq < 64)
  94                 do_IRQ(irq + irq_base);
  95         else {
  96                 /* Ignore spurious interrupt */
  97         }
  98 }
  99
 100 static void msc_bind_eic_interrupt(int irq, int set)
 101 {
 102         MSCIC_WRITE(MSC01_IC_RAMW,
 103                     (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
 104 }
 105
 106 static struct irq_chip msc_levelirq_type = {
 107         .name = "SOC-it-Level",
 108         .irq_ack = level_mask_and_ack_msc_irq,
 109         .irq_mask = mask_msc_irq,
 110         .irq_mask_ack = level_mask_and_ack_msc_irq,
 111         .irq_unmask = unmask_msc_irq,
 112         .irq_eoi = unmask_msc_irq,
 113 };
 114
 115 static struct irq_chip msc_edgeirq_type = {
 116         .name = "SOC-it-Edge",
 117         .irq_ack = edge_mask_and_ack_msc_irq,
 118         .irq_mask = mask_msc_irq,
 119         .irq_mask_ack = edge_mask_and_ack_msc_irq,
 120         .irq_unmask = unmask_msc_irq,
 121         .irq_eoi = unmask_msc_irq,
 122 };
 123
 124
 125 void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
 126 {
 127         _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
 128
 129         /* Reset interrupt controller - initialises all registers to 0 */
 130         MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
 131
 132         board_bind_eic_interrupt = &msc_bind_eic_interrupt;
 133
 134         for (; nirq >= 0; nirq--, imp++) {
 135                 int n = imp->im_irq;
 136
 137                 switch (imp->im_type) {
 138                 case MSC01_IRQ_EDGE:
 139                         irq_set_chip_and_handler_name(irqbase + n,
 140                                                       &msc_edgeirq_type,
 141                                                       handle_edge_irq,
 142                                                       "edge");
 143                         if (cpu_has_veic)
 144                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
 145                         else
 146                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
 147                         break;
 148                 case MSC01_IRQ_LEVEL:
 149                         irq_set_chip_and_handler_name(irqbase + n,
 150                                                       &msc_levelirq_type,
 151                                                       handle_level_irq,
 152                                                       "level");
 153                         if (cpu_has_veic)
 154                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
 155                         else
 156                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
 157                 }
 158         }
 159
 160         irq_base = irqbase;
 161
 162         MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);     /* Enable interrupt generation */
 163
 164 }