arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/module.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/system.h>
  26 #include <asm/watch.h>
  27 #include <asm/spram.h>
  28 /*
  29  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  30  * the implementation of the "wait" feature differs between CPU families. This
  31  * points to the function that implements CPU specific wait.
  32  * The wait instruction stops the pipeline and reduces the power consumption of
  33  * the CPU very much.
  34  */
  35 void (*cpu_wait)(void);
  36 EXPORT_SYMBOL(cpu_wait);
  37
  38 static void r3081_wait(void)
  39 {
  40         unsigned long cfg = read_c0_conf();
  41         write_c0_conf(cfg | R30XX_CONF_HALT);
  42 }
  43
  44 static void r39xx_wait(void)
  45 {
  46         local_irq_disable();
  47         if (!need_resched())
  48                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  49         local_irq_enable();
  50 }
  51
  52 extern void r4k_wait(void);
  53
  54 /*
  55  * This variant is preferable as it allows testing need_resched and going to
  56  * sleep depending on the outcome atomically.  Unfortunately the "It is
  57  * implementation-dependent whether the pipeline restarts when a non-enabled
  58  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  59  * using this version a gamble.
  60  */
  61 void r4k_wait_irqoff(void)
  62 {
  63         local_irq_disable();
  64         if (!need_resched())
  65                 __asm__("       .set    push            \n"
  66                         "       .set    mips3           \n"
  67                         "       wait                    \n"
  68                         "       .set    pop             \n");
  69         local_irq_enable();
  70         __asm__("       .globl __pastwait       \n"
  71                 "__pastwait:                    \n");
  72         return;
  73 }
  74
  75 /*
  76  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  77  * have any pending stores when the WAIT instruction is executed.
  78  */
  79 static void rm7k_wait_irqoff(void)
  80 {
  81         local_irq_disable();
  82         if (!need_resched())
  83                 __asm__(
  84                 "       .set    push                                    \n"
  85                 "       .set    mips3                                   \n"
  86                 "       .set    noat                                    \n"
  87                 "       mfc0    $1, $12                                 \n"
  88                 "       sync                                            \n"
  89                 "       mtc0    $1, $12         # stalls until W stage  \n"
  90                 "       wait                                            \n"
  91                 "       mtc0    $1, $12         # stalls until W stage  \n"
  92                 "       .set    pop                                     \n");
  93         local_irq_enable();
  94 }
  95
  96 /*
  97  * The Au1xxx wait is available only if using 32khz counter or
  98  * external timer source, but specifically not CP0 Counter.
  99  * alchemy/common/time.c may override cpu_wait!
 100  */
 101 static void au1k_wait(void)
 102 {
 103         __asm__("       .set    mips3                   \n"
 104                 "       cache   0x14, 0(%0)             \n"
 105                 "       cache   0x14, 32(%0)            \n"
 106                 "       sync                            \n"
 107                 "       nop                             \n"
 108                 "       wait                            \n"
 109                 "       nop                             \n"
 110                 "       nop                             \n"
 111                 "       nop                             \n"
 112                 "       nop                             \n"
 113                 "       .set    mips0                   \n"
 114                 : : "r" (au1k_wait));
 115 }
 116
 117 static int __initdata nowait;
 118
 119 static int __init wait_disable(char *s)
 120 {
 121         nowait = 1;
 122
 123         return 1;
 124 }
 125
 126 __setup("nowait", wait_disable);
 127
 128 static int __cpuinitdata mips_fpu_disabled;
 129
 130 static int __init fpu_disable(char *s)
 131 {
 132         cpu_data[0].options &= ~MIPS_CPU_FPU;
 133         mips_fpu_disabled = 1;
 134
 135         return 1;
 136 }
 137
 138 __setup("nofpu", fpu_disable);
 139
 140 int __cpuinitdata mips_dsp_disabled;
 141
 142 static int __init dsp_disable(char *s)
 143 {
 144         cpu_data[0].ases &= ~MIPS_ASE_DSP;
 145         mips_dsp_disabled = 1;
 146
 147         return 1;
 148 }
 149
 150 __setup("nodsp", dsp_disable);
 151
 152 void __init check_wait(void)
 153 {
 154         struct cpuinfo_mips *c = &current_cpu_data;
 155
 156         if (nowait) {
 157                 printk("Wait instruction disabled.\n");
 158                 return;
 159         }
 160
 161         switch (c->cputype) {
 162         case CPU_R3081:
 163         case CPU_R3081E:
 164                 cpu_wait = r3081_wait;
 165                 break;
 166         case CPU_TX3927:
 167                 cpu_wait = r39xx_wait;
 168                 break;
 169         case CPU_R4200:
 170 /*      case CPU_R4300: */
 171         case CPU_R4600:
 172         case CPU_R4640:
 173         case CPU_R4650:
 174         case CPU_R4700:
 175         case CPU_R5000:
 176         case CPU_R5500:
 177         case CPU_NEVADA:
 178         case CPU_4KC:
 179         case CPU_4KEC:
 180         case CPU_4KSC:
 181         case CPU_5KC:
 182         case CPU_25KF:
 183         case CPU_PR4450:
 184         case CPU_BCM3302:
 185         case CPU_BCM6338:
 186         case CPU_BCM6348:
 187         case CPU_BCM6358:
 188         case CPU_CAVIUM_OCTEON:
 189         case CPU_CAVIUM_OCTEON_PLUS:
 190         case CPU_JZRISC:
 191                 cpu_wait = r4k_wait;
 192                 break;
 193
 194         case CPU_RM7000:
 195                 cpu_wait = rm7k_wait_irqoff;
 196                 break;
 197
 198         case CPU_24K:
 199         case CPU_34K:
 200         case CPU_1004K:
 201                 cpu_wait = r4k_wait;
 202                 if (read_c0_config7() & MIPS_CONF7_WII)
 203                         cpu_wait = r4k_wait_irqoff;
 204                 break;
 205
 206         case CPU_74K:
 207                 cpu_wait = r4k_wait;
 208                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 209                         cpu_wait = r4k_wait_irqoff;
 210                 break;
 211
 212         case CPU_TX49XX:
 213                 cpu_wait = r4k_wait_irqoff;
 214                 break;
 215         case CPU_ALCHEMY:
 216                 cpu_wait = au1k_wait;
 217                 break;
 218         case CPU_20KC:
 219                 /*
 220                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 221                  * WAIT on Rev2.0 and Rev3.0 has E16.
 222                  * Rev3.1 WAIT is nop, why bother
 223                  */
 224                 if ((c->processor_id & 0xff) <= 0x64)
 225                         break;
 226
 227                 /*
 228                  * Another rev is incremeting c0_count at a reduced clock
 229                  * rate while in WAIT mode.  So we basically have the choice
 230                  * between using the cp0 timer as clocksource or avoiding
 231                  * the WAIT instruction.  Until more details are known,
 232                  * disable the use of WAIT for 20Kc entirely.
 233                    cpu_wait = r4k_wait;
 234                  */
 235                 break;
 236         case CPU_RM9000:
 237                 if ((c->processor_id & 0x00ff) >= 0x40)
 238                         cpu_wait = r4k_wait;
 239                 break;
 240         default:
 241                 break;
 242         }
 243 }
 244
 245 static inline void check_errata(void)
 246 {
 247         struct cpuinfo_mips *c = &current_cpu_data;
 248
 249         switch (c->cputype) {
 250         case CPU_34K:
 251                 /*
 252                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 253                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 254                  * making use of VPE1 will be responsable for that VPE.
 255                  */
 256                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 257                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 258                 break;
 259         default:
 260                 break;
 261         }
 262 }
 263
 264 void __init check_bugs32(void)
 265 {
 266         check_errata();
 267 }
 268
 269 /*
 270  * Probe whether cpu has config register by trying to play with
 271  * alternate cache bit and see whether it matters.
 272  * It's used by cpu_probe to distinguish between R3000A and R3081.
 273  */
 274 static inline int cpu_has_confreg(void)
 275 {
 276 #ifdef CONFIG_CPU_R3000
 277         extern unsigned long r3k_cache_size(unsigned long);
 278         unsigned long size1, size2;
 279         unsigned long cfg = read_c0_conf();
 280
 281         size1 = r3k_cache_size(ST0_ISC);
 282         write_c0_conf(cfg ^ R30XX_CONF_AC);
 283         size2 = r3k_cache_size(ST0_ISC);
 284         write_c0_conf(cfg);
 285         return size1 != size2;
 286 #else
 287         return 0;
 288 #endif
 289 }
 290
 291 /*
 292  * Get the FPU Implementation/Revision.
 293  */
 294 static inline unsigned long cpu_get_fpu_id(void)
 295 {
 296         unsigned long tmp, fpu_id;
 297
 298         tmp = read_c0_status();
 299         __enable_fpu();
 300         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 301         write_c0_status(tmp);
 302         return fpu_id;
 303 }
 304
 305 /*
 306  * Check the CPU has an FPU the official way.
 307  */
 308 static inline int __cpu_has_fpu(void)
 309 {
 310         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 311 }
 312
 313 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 314 {
 315 #ifdef __NEED_VMBITS_PROBE
 316         write_c0_entryhi(0x3fffffffffffe000ULL);
 317         back_to_back_c0_hazard();
 318         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 319 #endif
 320 }
 321
 322 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 323                 | MIPS_CPU_COUNTER)
 324
 325 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 326 {
 327         switch (c->processor_id & 0xff00) {
 328         case PRID_IMP_R2000:
 329                 c->cputype = CPU_R2000;
 330                 __cpu_name[cpu] = "R2000";
 331                 c->isa_level = MIPS_CPU_ISA_I;
 332                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 333                              MIPS_CPU_NOFPUEX;
 334                 if (__cpu_has_fpu())
 335                         c->options |= MIPS_CPU_FPU;
 336                 c->tlbsize = 64;
 337                 break;
 338         case PRID_IMP_R3000:
 339                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 340                         if (cpu_has_confreg()) {
 341                                 c->cputype = CPU_R3081E;
 342                                 __cpu_name[cpu] = "R3081";
 343                         } else {
 344                                 c->cputype = CPU_R3000A;
 345                                 __cpu_name[cpu] = "R3000A";
 346                         }
 347                         break;
 348                 } else {
 349                         c->cputype = CPU_R3000;
 350                         __cpu_name[cpu] = "R3000";
 351                 }
 352                 c->isa_level = MIPS_CPU_ISA_I;
 353                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 354                              MIPS_CPU_NOFPUEX;
 355                 if (__cpu_has_fpu())
 356                         c->options |= MIPS_CPU_FPU;
 357                 c->tlbsize = 64;
 358                 break;
 359         case PRID_IMP_R4000:
 360                 if (read_c0_config() & CONF_SC) {
 361                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 362                                 c->cputype = CPU_R4400PC;
 363                                 __cpu_name[cpu] = "R4400PC";
 364                         } else {
 365                                 c->cputype = CPU_R4000PC;
 366                                 __cpu_name[cpu] = "R4000PC";
 367                         }
 368                 } else {
 369                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 370                                 c->cputype = CPU_R4400SC;
 371                                 __cpu_name[cpu] = "R4400SC";
 372                         } else {
 373                                 c->cputype = CPU_R4000SC;
 374                                 __cpu_name[cpu] = "R4000SC";
 375                         }
 376                 }
 377
 378                 c->isa_level = MIPS_CPU_ISA_III;
 379                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 380                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 381                              MIPS_CPU_LLSC;
 382                 c->tlbsize = 48;
 383                 break;
 384         case PRID_IMP_VR41XX:
 385                 switch (c->processor_id & 0xf0) {
 386                 case PRID_REV_VR4111:
 387                         c->cputype = CPU_VR4111;
 388                         __cpu_name[cpu] = "NEC VR4111";
 389                         break;
 390                 case PRID_REV_VR4121:
 391                         c->cputype = CPU_VR4121;
 392                         __cpu_name[cpu] = "NEC VR4121";
 393                         break;
 394                 case PRID_REV_VR4122:
 395                         if ((c->processor_id & 0xf) < 0x3) {
 396                                 c->cputype = CPU_VR4122;
 397                                 __cpu_name[cpu] = "NEC VR4122";
 398                         } else {
 399                                 c->cputype = CPU_VR4181A;
 400                                 __cpu_name[cpu] = "NEC VR4181A";
 401                         }
 402                         break;
 403                 case PRID_REV_VR4130:
 404                         if ((c->processor_id & 0xf) < 0x4) {
 405                                 c->cputype = CPU_VR4131;
 406                                 __cpu_name[cpu] = "NEC VR4131";
 407                         } else {
 408                                 c->cputype = CPU_VR4133;
 409                                 __cpu_name[cpu] = "NEC VR4133";
 410                         }
 411                         break;
 412                 default:
 413                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 414                         c->cputype = CPU_VR41XX;
 415                         __cpu_name[cpu] = "NEC Vr41xx";
 416                         break;
 417                 }
 418                 c->isa_level = MIPS_CPU_ISA_III;
 419                 c->options = R4K_OPTS;
 420                 c->tlbsize = 32;
 421                 break;
 422         case PRID_IMP_R4300:
 423                 c->cputype = CPU_R4300;
 424                 __cpu_name[cpu] = "R4300";
 425                 c->isa_level = MIPS_CPU_ISA_III;
 426                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 427                              MIPS_CPU_LLSC;
 428                 c->tlbsize = 32;
 429                 break;
 430         case PRID_IMP_R4600:
 431                 c->cputype = CPU_R4600;
 432                 __cpu_name[cpu] = "R4600";
 433                 c->isa_level = MIPS_CPU_ISA_III;
 434                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 435                              MIPS_CPU_LLSC;
 436                 c->tlbsize = 48;
 437                 break;
 438         #if 0
 439         case PRID_IMP_R4650:
 440                 /*
 441                  * This processor doesn't have an MMU, so it's not
 442                  * "real easy" to run Linux on it. It is left purely
 443                  * for documentation.  Commented out because it shares
 444                  * it's c0_prid id number with the TX3900.
 445                  */
 446                 c->cputype = CPU_R4650;
 447                 __cpu_name[cpu] = "R4650";
 448                 c->isa_level = MIPS_CPU_ISA_III;
 449                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 450                 c->tlbsize = 48;
 451                 break;
 452         #endif
 453         case PRID_IMP_TX39:
 454                 c->isa_level = MIPS_CPU_ISA_I;
 455                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 456
 457                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 458                         c->cputype = CPU_TX3927;
 459                         __cpu_name[cpu] = "TX3927";
 460                         c->tlbsize = 64;
 461                 } else {
 462                         switch (c->processor_id & 0xff) {
 463                         case PRID_REV_TX3912:
 464                                 c->cputype = CPU_TX3912;
 465                                 __cpu_name[cpu] = "TX3912";
 466                                 c->tlbsize = 32;
 467                                 break;
 468                         case PRID_REV_TX3922:
 469                                 c->cputype = CPU_TX3922;
 470                                 __cpu_name[cpu] = "TX3922";
 471                                 c->tlbsize = 64;
 472                                 break;
 473                         }
 474                 }
 475                 break;
 476         case PRID_IMP_R4700:
 477                 c->cputype = CPU_R4700;
 478                 __cpu_name[cpu] = "R4700";
 479                 c->isa_level = MIPS_CPU_ISA_III;
 480                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 481                              MIPS_CPU_LLSC;
 482                 c->tlbsize = 48;
 483                 break;
 484         case PRID_IMP_TX49:
 485                 c->cputype = CPU_TX49XX;
 486                 __cpu_name[cpu] = "R49XX";
 487                 c->isa_level = MIPS_CPU_ISA_III;
 488                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 489                 if (!(c->processor_id & 0x08))
 490                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 491                 c->tlbsize = 48;
 492                 break;
 493         case PRID_IMP_R5000:
 494                 c->cputype = CPU_R5000;
 495                 __cpu_name[cpu] = "R5000";
 496                 c->isa_level = MIPS_CPU_ISA_IV;
 497                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 498                              MIPS_CPU_LLSC;
 499                 c->tlbsize = 48;
 500                 break;
 501         case PRID_IMP_R5432:
 502                 c->cputype = CPU_R5432;
 503                 __cpu_name[cpu] = "R5432";
 504                 c->isa_level = MIPS_CPU_ISA_IV;
 505                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 506                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 507                 c->tlbsize = 48;
 508                 break;
 509         case PRID_IMP_R5500:
 510                 c->cputype = CPU_R5500;
 511                 __cpu_name[cpu] = "R5500";
 512                 c->isa_level = MIPS_CPU_ISA_IV;
 513                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 514                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 515                 c->tlbsize = 48;
 516                 break;
 517         case PRID_IMP_NEVADA:
 518                 c->cputype = CPU_NEVADA;
 519                 __cpu_name[cpu] = "Nevada";
 520                 c->isa_level = MIPS_CPU_ISA_IV;
 521                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 522                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 523                 c->tlbsize = 48;
 524                 break;
 525         case PRID_IMP_R6000:
 526                 c->cputype = CPU_R6000;
 527                 __cpu_name[cpu] = "R6000";
 528                 c->isa_level = MIPS_CPU_ISA_II;
 529                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 530                              MIPS_CPU_LLSC;
 531                 c->tlbsize = 32;
 532                 break;
 533         case PRID_IMP_R6000A:
 534                 c->cputype = CPU_R6000A;
 535                 __cpu_name[cpu] = "R6000A";
 536                 c->isa_level = MIPS_CPU_ISA_II;
 537                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 538                              MIPS_CPU_LLSC;
 539                 c->tlbsize = 32;
 540                 break;
 541         case PRID_IMP_RM7000:
 542                 c->cputype = CPU_RM7000;
 543                 __cpu_name[cpu] = "RM7000";
 544                 c->isa_level = MIPS_CPU_ISA_IV;
 545                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 546                              MIPS_CPU_LLSC;
 547                 /*
 548                  * Undocumented RM7000:  Bit 29 in the info register of
 549                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 550                  * entries.
 551                  *
 552                  * 29      1 =>    64 entry JTLB
 553                  *         0 =>    48 entry JTLB
 554                  */
 555                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 556                 break;
 557         case PRID_IMP_RM9000:
 558                 c->cputype = CPU_RM9000;
 559                 __cpu_name[cpu] = "RM9000";
 560                 c->isa_level = MIPS_CPU_ISA_IV;
 561                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 562                              MIPS_CPU_LLSC;
 563                 /*
 564                  * Bit 29 in the info register of the RM9000
 565                  * indicates if the TLB has 48 or 64 entries.
 566                  *
 567                  * 29      1 =>    64 entry JTLB
 568                  *         0 =>    48 entry JTLB
 569                  */
 570                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 571                 break;
 572         case PRID_IMP_R8000:
 573                 c->cputype = CPU_R8000;
 574                 __cpu_name[cpu] = "RM8000";
 575                 c->isa_level = MIPS_CPU_ISA_IV;
 576                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 577                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 578                              MIPS_CPU_LLSC;
 579                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 580                 break;
 581         case PRID_IMP_R10000:
 582                 c->cputype = CPU_R10000;
 583                 __cpu_name[cpu] = "R10000";
 584                 c->isa_level = MIPS_CPU_ISA_IV;
 585                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 586                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 587                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 588                              MIPS_CPU_LLSC;
 589                 c->tlbsize = 64;
 590                 break;
 591         case PRID_IMP_R12000:
 592                 c->cputype = CPU_R12000;
 593                 __cpu_name[cpu] = "R12000";
 594                 c->isa_level = MIPS_CPU_ISA_IV;
 595                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 596                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 597                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 598                              MIPS_CPU_LLSC;
 599                 c->tlbsize = 64;
 600                 break;
 601         case PRID_IMP_R14000:
 602                 c->cputype = CPU_R14000;
 603                 __cpu_name[cpu] = "R14000";
 604                 c->isa_level = MIPS_CPU_ISA_IV;
 605                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 606                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 607                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 608                              MIPS_CPU_LLSC;
 609                 c->tlbsize = 64;
 610                 break;
 611         case PRID_IMP_LOONGSON2:
 612                 c->cputype = CPU_LOONGSON2;
 613                 __cpu_name[cpu] = "ICT Loongson-2";
 614                 c->isa_level = MIPS_CPU_ISA_III;
 615                 c->options = R4K_OPTS |
 616                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 617                              MIPS_CPU_32FPR;
 618                 c->tlbsize = 64;
 619                 break;
 620         }
 621 }
 622
 623 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 624         "Unsupported ISA type, c0.config0: %d.";
 625
 626 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 627 {
 628         unsigned int config0;
 629         int isa;
 630
 631         config0 = read_c0_config();
 632
 633         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 634                 c->options |= MIPS_CPU_TLB;
 635         isa = (config0 & MIPS_CONF_AT) >> 13;
 636         switch (isa) {
 637         case 0:
 638                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 639                 case 0:
 640                         c->isa_level = MIPS_CPU_ISA_M32R1;
 641                         break;
 642                 case 1:
 643                         c->isa_level = MIPS_CPU_ISA_M32R2;
 644                         break;
 645                 default:
 646                         goto unknown;
 647                 }
 648                 break;
 649         case 2:
 650                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 651                 case 0:
 652                         c->isa_level = MIPS_CPU_ISA_M64R1;
 653                         break;
 654                 case 1:
 655                         c->isa_level = MIPS_CPU_ISA_M64R2;
 656                         break;
 657                 default:
 658                         goto unknown;
 659                 }
 660                 break;
 661         default:
 662                 goto unknown;
 663         }
 664
 665         return config0 & MIPS_CONF_M;
 666
 667 unknown:
 668         panic(unknown_isa, config0);
 669 }
 670
 671 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 672 {
 673         unsigned int config1;
 674
 675         config1 = read_c0_config1();
 676
 677         if (config1 & MIPS_CONF1_MD)
 678                 c->ases |= MIPS_ASE_MDMX;
 679         if (config1 & MIPS_CONF1_WR)
 680                 c->options |= MIPS_CPU_WATCH;
 681         if (config1 & MIPS_CONF1_CA)
 682                 c->ases |= MIPS_ASE_MIPS16;
 683         if (config1 & MIPS_CONF1_EP)
 684                 c->options |= MIPS_CPU_EJTAG;
 685         if (config1 & MIPS_CONF1_FP) {
 686                 c->options |= MIPS_CPU_FPU;
 687                 c->options |= MIPS_CPU_32FPR;
 688         }
 689         if (cpu_has_tlb)
 690                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 691
 692         return config1 & MIPS_CONF_M;
 693 }
 694
 695 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 696 {
 697         unsigned int config2;
 698
 699         config2 = read_c0_config2();
 700
 701         if (config2 & MIPS_CONF2_SL)
 702                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 703
 704         return config2 & MIPS_CONF_M;
 705 }
 706
 707 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 708 {
 709         unsigned int config3;
 710
 711         config3 = read_c0_config3();
 712
 713         if (config3 & MIPS_CONF3_SM)
 714                 c->ases |= MIPS_ASE_SMARTMIPS;
 715         if (config3 & MIPS_CONF3_DSP)
 716                 c->ases |= MIPS_ASE_DSP;
 717         if (config3 & MIPS_CONF3_VINT)
 718                 c->options |= MIPS_CPU_VINT;
 719         if (config3 & MIPS_CONF3_VEIC)
 720                 c->options |= MIPS_CPU_VEIC;
 721         if (config3 & MIPS_CONF3_MT)
 722                 c->ases |= MIPS_ASE_MIPSMT;
 723         if (config3 & MIPS_CONF3_ULRI)
 724                 c->options |= MIPS_CPU_ULRI;
 725
 726         return config3 & MIPS_CONF_M;
 727 }
 728
 729 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 730 {
 731         unsigned int config4;
 732
 733         config4 = read_c0_config4();
 734
 735         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 736             && cpu_has_tlb)
 737                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 738
 739         return config4 & MIPS_CONF_M;
 740 }
 741
 742 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 743 {
 744         int ok;
 745
 746         /* MIPS32 or MIPS64 compliant CPU.  */
 747         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 748                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 749
 750         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 751
 752         ok = decode_config0(c);                 /* Read Config registers.  */
 753         BUG_ON(!ok);                            /* Arch spec violation!  */
 754         if (ok)
 755                 ok = decode_config1(c);
 756         if (ok)
 757                 ok = decode_config2(c);
 758         if (ok)
 759                 ok = decode_config3(c);
 760         if (ok)
 761                 ok = decode_config4(c);
 762
 763         mips_probe_watch_registers(c);
 764
 765         if (cpu_has_mips_r2)
 766                 c->core = read_c0_ebase() & 0x3ff;
 767 }
 768
 769 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 770 {
 771         decode_configs(c);
 772         switch (c->processor_id & 0xff00) {
 773         case PRID_IMP_4KC:
 774                 c->cputype = CPU_4KC;
 775                 __cpu_name[cpu] = "MIPS 4Kc";
 776                 break;
 777         case PRID_IMP_4KEC:
 778         case PRID_IMP_4KECR2:
 779                 c->cputype = CPU_4KEC;
 780                 __cpu_name[cpu] = "MIPS 4KEc";
 781                 break;
 782         case PRID_IMP_4KSC:
 783         case PRID_IMP_4KSD:
 784                 c->cputype = CPU_4KSC;
 785                 __cpu_name[cpu] = "MIPS 4KSc";
 786                 break;
 787         case PRID_IMP_5KC:
 788                 c->cputype = CPU_5KC;
 789                 __cpu_name[cpu] = "MIPS 5Kc";
 790                 break;
 791         case PRID_IMP_20KC:
 792                 c->cputype = CPU_20KC;
 793                 __cpu_name[cpu] = "MIPS 20Kc";
 794                 break;
 795         case PRID_IMP_24K:
 796         case PRID_IMP_24KE:
 797                 c->cputype = CPU_24K;
 798                 __cpu_name[cpu] = "MIPS 24Kc";
 799                 break;
 800         case PRID_IMP_25KF:
 801                 c->cputype = CPU_25KF;
 802                 __cpu_name[cpu] = "MIPS 25Kc";
 803                 break;
 804         case PRID_IMP_34K:
 805                 c->cputype = CPU_34K;
 806                 __cpu_name[cpu] = "MIPS 34Kc";
 807                 break;
 808         case PRID_IMP_74K:
 809                 c->cputype = CPU_74K;
 810                 __cpu_name[cpu] = "MIPS 74Kc";
 811                 break;
 812         case PRID_IMP_1004K:
 813                 c->cputype = CPU_1004K;
 814                 __cpu_name[cpu] = "MIPS 1004Kc";
 815                 break;
 816         }
 817
 818         spram_config();
 819 }
 820
 821 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 822 {
 823         decode_configs(c);
 824         switch (c->processor_id & 0xff00) {
 825         case PRID_IMP_AU1_REV1:
 826         case PRID_IMP_AU1_REV2:
 827                 c->cputype = CPU_ALCHEMY;
 828                 switch ((c->processor_id >> 24) & 0xff) {
 829                 case 0:
 830                         __cpu_name[cpu] = "Au1000";
 831                         break;
 832                 case 1:
 833                         __cpu_name[cpu] = "Au1500";
 834                         break;
 835                 case 2:
 836                         __cpu_name[cpu] = "Au1100";
 837                         break;
 838                 case 3:
 839                         __cpu_name[cpu] = "Au1550";
 840                         break;
 841                 case 4:
 842                         __cpu_name[cpu] = "Au1200";
 843                         if ((c->processor_id & 0xff) == 2)
 844                                 __cpu_name[cpu] = "Au1250";
 845                         break;
 846                 case 5:
 847                         __cpu_name[cpu] = "Au1210";
 848                         break;
 849                 default:
 850                         __cpu_name[cpu] = "Au1xxx";
 851                         break;
 852                 }
 853                 break;
 854         }
 855 }
 856
 857 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 858 {
 859         decode_configs(c);
 860
 861         switch (c->processor_id & 0xff00) {
 862         case PRID_IMP_SB1:
 863                 c->cputype = CPU_SB1;
 864                 __cpu_name[cpu] = "SiByte SB1";
 865                 /* FPU in pass1 is known to have issues. */
 866                 if ((c->processor_id & 0xff) < 0x02)
 867                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 868                 break;
 869         case PRID_IMP_SB1A:
 870                 c->cputype = CPU_SB1A;
 871                 __cpu_name[cpu] = "SiByte SB1A";
 872                 break;
 873         }
 874 }
 875
 876 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 877 {
 878         decode_configs(c);
 879         switch (c->processor_id & 0xff00) {
 880         case PRID_IMP_SR71000:
 881                 c->cputype = CPU_SR71000;
 882                 __cpu_name[cpu] = "Sandcraft SR71000";
 883                 c->scache.ways = 8;
 884                 c->tlbsize = 64;
 885                 break;
 886         }
 887 }
 888
 889 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 890 {
 891         decode_configs(c);
 892         switch (c->processor_id & 0xff00) {
 893         case PRID_IMP_PR4450:
 894                 c->cputype = CPU_PR4450;
 895                 __cpu_name[cpu] = "Philips PR4450";
 896                 c->isa_level = MIPS_CPU_ISA_M32R1;
 897                 break;
 898         }
 899 }
 900
 901 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 902 {
 903         decode_configs(c);
 904         switch (c->processor_id & 0xff00) {
 905         case PRID_IMP_BCM3302:
 906          /* same as PRID_IMP_BCM6338 */
 907                 c->cputype = CPU_BCM3302;
 908                 __cpu_name[cpu] = "Broadcom BCM3302";
 909                 break;
 910         case PRID_IMP_BCM4710:
 911                 c->cputype = CPU_BCM4710;
 912                 __cpu_name[cpu] = "Broadcom BCM4710";
 913                 break;
 914         case PRID_IMP_BCM6345:
 915                 c->cputype = CPU_BCM6345;
 916                 __cpu_name[cpu] = "Broadcom BCM6345";
 917                 break;
 918         case PRID_IMP_BCM6348:
 919                 c->cputype = CPU_BCM6348;
 920                 __cpu_name[cpu] = "Broadcom BCM6348";
 921                 break;
 922         case PRID_IMP_BCM4350:
 923                 switch (c->processor_id & 0xf0) {
 924                 case PRID_REV_BCM6358:
 925                         c->cputype = CPU_BCM6358;
 926                         __cpu_name[cpu] = "Broadcom BCM6358";
 927                         break;
 928                 default:
 929                         c->cputype = CPU_UNKNOWN;
 930                         break;
 931                 }
 932                 break;
 933         }
 934 }
 935
 936 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 937 {
 938         decode_configs(c);
 939         switch (c->processor_id & 0xff00) {
 940         case PRID_IMP_CAVIUM_CN38XX:
 941         case PRID_IMP_CAVIUM_CN31XX:
 942         case PRID_IMP_CAVIUM_CN30XX:
 943                 c->cputype = CPU_CAVIUM_OCTEON;
 944                 __cpu_name[cpu] = "Cavium Octeon";
 945                 goto platform;
 946         case PRID_IMP_CAVIUM_CN58XX:
 947         case PRID_IMP_CAVIUM_CN56XX:
 948         case PRID_IMP_CAVIUM_CN50XX:
 949         case PRID_IMP_CAVIUM_CN52XX:
 950                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 951                 __cpu_name[cpu] = "Cavium Octeon+";
 952 platform:
 953                 if (cpu == 0)
 954                         __elf_platform = "octeon";
 955                 break;
 956         default:
 957                 printk(KERN_INFO "Unknown Octeon chip!\n");
 958                 c->cputype = CPU_UNKNOWN;
 959                 break;
 960         }
 961 }
 962
 963 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 964 {
 965         decode_configs(c);
 966         /* JZRISC does not implement the CP0 counter. */
 967         c->options &= ~MIPS_CPU_COUNTER;
 968         switch (c->processor_id & 0xff00) {
 969         case PRID_IMP_JZRISC:
 970                 c->cputype = CPU_JZRISC;
 971                 __cpu_name[cpu] = "Ingenic JZRISC";
 972                 break;
 973         default:
 974                 panic("Unknown Ingenic Processor ID!");
 975                 break;
 976         }
 977 }
 978
 979 const char *__cpu_name[NR_CPUS];
 980 const char *__elf_platform;
 981
 982 __cpuinit void cpu_probe(void)
 983 {
 984         struct cpuinfo_mips *c = &current_cpu_data;
 985         unsigned int cpu = smp_processor_id();
 986
 987         c->processor_id = PRID_IMP_UNKNOWN;
 988         c->fpu_id       = FPIR_IMP_NONE;
 989         c->cputype      = CPU_UNKNOWN;
 990
 991         c->processor_id = read_c0_prid();
 992         switch (c->processor_id & 0xff0000) {
 993         case PRID_COMP_LEGACY:
 994                 cpu_probe_legacy(c, cpu);
 995                 break;
 996         case PRID_COMP_MIPS:
 997                 cpu_probe_mips(c, cpu);
 998                 break;
 999         case PRID_COMP_ALCHEMY:
1000                 cpu_probe_alchemy(c, cpu);
1001                 break;
1002         case PRID_COMP_SIBYTE:
1003                 cpu_probe_sibyte(c, cpu);
1004                 break;
1005         case PRID_COMP_BROADCOM:
1006                 cpu_probe_broadcom(c, cpu);
1007                 break;
1008         case PRID_COMP_SANDCRAFT:
1009                 cpu_probe_sandcraft(c, cpu);
1010                 break;
1011         case PRID_COMP_NXP:
1012                 cpu_probe_nxp(c, cpu);
1013                 break;
1014         case PRID_COMP_CAVIUM:
1015                 cpu_probe_cavium(c, cpu);
1016                 break;
1017         case PRID_COMP_INGENIC:
1018                 cpu_probe_ingenic(c, cpu);
1019                 break;
1020         }
1021
1022         BUG_ON(!__cpu_name[cpu]);
1023         BUG_ON(c->cputype == CPU_UNKNOWN);
1024
1025         /*
1026          * Platform code can force the cpu type to optimize code
1027          * generation. In that case be sure the cpu type is correctly
1028          * manually setup otherwise it could trigger some nasty bugs.
1029          */
1030         BUG_ON(current_cpu_type() != c->cputype);
1031
1032         if (mips_fpu_disabled)
1033                 c->options &= ~MIPS_CPU_FPU;
1034
1035         if (mips_dsp_disabled)
1036                 c->ases &= ~MIPS_ASE_DSP;
1037
1038         if (c->options & MIPS_CPU_FPU) {
1039                 c->fpu_id = cpu_get_fpu_id();
1040
1041                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1042                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1043                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1044                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1045                         if (c->fpu_id & MIPS_FPIR_3D)
1046                                 c->ases |= MIPS_ASE_MIPS3D;
1047                 }
1048         }
1049
1050         if (cpu_has_mips_r2)
1051                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1052         else
1053                 c->srsets = 1;
1054
1055         cpu_probe_vmbits(c);
1056 }
1057
1058 __cpuinit void cpu_report(void)
1059 {
1060         struct cpuinfo_mips *c = &current_cpu_data;
1061
1062         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1063                c->processor_id, cpu_name_string());
1064         if (c->options & MIPS_CPU_FPU)
1065                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1066 }