arch/mips/include/asm/octeon/cvmx-uctlx-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2010 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_UCTLX_TYPEDEFS_H__
  29 #define __CVMX_UCTLX_TYPEDEFS_H__
  30
  31 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
  32 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
  33 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
  34 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
  35 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
  36 #define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
  37 #define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
  38 #define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
  39 #define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
  40 #define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
  41 #define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
  42 #define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
  43 #define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
  44
  45 union cvmx_uctlx_bist_status {
  46         uint64_t u64;
  47         struct cvmx_uctlx_bist_status_s {
  48                 uint64_t reserved_6_63:58;
  49                 uint64_t data_bis:1;
  50                 uint64_t desc_bis:1;
  51                 uint64_t erbm_bis:1;
  52                 uint64_t orbm_bis:1;
  53                 uint64_t wrbm_bis:1;
  54                 uint64_t ppaf_bis:1;
  55         } s;
  56         struct cvmx_uctlx_bist_status_s       cn63xx;
  57         struct cvmx_uctlx_bist_status_s       cn63xxp1;
  58 };
  59
  60 union cvmx_uctlx_clk_rst_ctl {
  61         uint64_t u64;
  62         struct cvmx_uctlx_clk_rst_ctl_s {
  63                 uint64_t reserved_25_63:39;
  64                 uint64_t clear_bist:1;
  65                 uint64_t start_bist:1;
  66                 uint64_t ehci_sm:1;
  67                 uint64_t ohci_clkcktrst:1;
  68                 uint64_t ohci_sm:1;
  69                 uint64_t ohci_susp_lgcy:1;
  70                 uint64_t app_start_clk:1;
  71                 uint64_t o_clkdiv_rst:1;
  72                 uint64_t h_clkdiv_byp:1;
  73                 uint64_t h_clkdiv_rst:1;
  74                 uint64_t h_clkdiv_en:1;
  75                 uint64_t o_clkdiv_en:1;
  76                 uint64_t h_div:4;
  77                 uint64_t p_refclk_sel:2;
  78                 uint64_t p_refclk_div:2;
  79                 uint64_t reserved_4_4:1;
  80                 uint64_t p_com_on:1;
  81                 uint64_t p_por:1;
  82                 uint64_t p_prst:1;
  83                 uint64_t hrst:1;
  84         } s;
  85         struct cvmx_uctlx_clk_rst_ctl_s       cn63xx;
  86         struct cvmx_uctlx_clk_rst_ctl_s       cn63xxp1;
  87 };
  88
  89 union cvmx_uctlx_ehci_ctl {
  90         uint64_t u64;
  91         struct cvmx_uctlx_ehci_ctl_s {
  92                 uint64_t reserved_20_63:44;
  93                 uint64_t desc_rbm:1;
  94                 uint64_t reg_nb:1;
  95                 uint64_t l2c_dc:1;
  96                 uint64_t l2c_bc:1;
  97                 uint64_t l2c_0pag:1;
  98                 uint64_t l2c_stt:1;
  99                 uint64_t l2c_buff_emod:2;
 100                 uint64_t l2c_desc_emod:2;
 101                 uint64_t inv_reg_a2:1;
 102                 uint64_t ehci_64b_addr_en:1;
 103                 uint64_t l2c_addr_msb:8;
 104         } s;
 105         struct cvmx_uctlx_ehci_ctl_s          cn63xx;
 106         struct cvmx_uctlx_ehci_ctl_s          cn63xxp1;
 107 };
 108
 109 union cvmx_uctlx_ehci_fla {
 110         uint64_t u64;
 111         struct cvmx_uctlx_ehci_fla_s {
 112                 uint64_t reserved_6_63:58;
 113                 uint64_t fla:6;
 114         } s;
 115         struct cvmx_uctlx_ehci_fla_s          cn63xx;
 116         struct cvmx_uctlx_ehci_fla_s          cn63xxp1;
 117 };
 118
 119 union cvmx_uctlx_erto_ctl {
 120         uint64_t u64;
 121         struct cvmx_uctlx_erto_ctl_s {
 122                 uint64_t reserved_32_63:32;
 123                 uint64_t to_val:27;
 124                 uint64_t reserved_0_4:5;
 125         } s;
 126         struct cvmx_uctlx_erto_ctl_s          cn63xx;
 127         struct cvmx_uctlx_erto_ctl_s          cn63xxp1;
 128 };
 129
 130 union cvmx_uctlx_if_ena {
 131         uint64_t u64;
 132         struct cvmx_uctlx_if_ena_s {
 133                 uint64_t reserved_1_63:63;
 134                 uint64_t en:1;
 135         } s;
 136         struct cvmx_uctlx_if_ena_s            cn63xx;
 137         struct cvmx_uctlx_if_ena_s            cn63xxp1;
 138 };
 139
 140 union cvmx_uctlx_int_ena {
 141         uint64_t u64;
 142         struct cvmx_uctlx_int_ena_s {
 143                 uint64_t reserved_8_63:56;
 144                 uint64_t ec_ovf_e:1;
 145                 uint64_t oc_ovf_e:1;
 146                 uint64_t wb_pop_e:1;
 147                 uint64_t wb_psh_f:1;
 148                 uint64_t cf_psh_f:1;
 149                 uint64_t or_psh_f:1;
 150                 uint64_t er_psh_f:1;
 151                 uint64_t pp_psh_f:1;
 152         } s;
 153         struct cvmx_uctlx_int_ena_s           cn63xx;
 154         struct cvmx_uctlx_int_ena_s           cn63xxp1;
 155 };
 156
 157 union cvmx_uctlx_int_reg {
 158         uint64_t u64;
 159         struct cvmx_uctlx_int_reg_s {
 160                 uint64_t reserved_8_63:56;
 161                 uint64_t ec_ovf_e:1;
 162                 uint64_t oc_ovf_e:1;
 163                 uint64_t wb_pop_e:1;
 164                 uint64_t wb_psh_f:1;
 165                 uint64_t cf_psh_f:1;
 166                 uint64_t or_psh_f:1;
 167                 uint64_t er_psh_f:1;
 168                 uint64_t pp_psh_f:1;
 169         } s;
 170         struct cvmx_uctlx_int_reg_s           cn63xx;
 171         struct cvmx_uctlx_int_reg_s           cn63xxp1;
 172 };
 173
 174 union cvmx_uctlx_ohci_ctl {
 175         uint64_t u64;
 176         struct cvmx_uctlx_ohci_ctl_s {
 177                 uint64_t reserved_19_63:45;
 178                 uint64_t reg_nb:1;
 179                 uint64_t l2c_dc:1;
 180                 uint64_t l2c_bc:1;
 181                 uint64_t l2c_0pag:1;
 182                 uint64_t l2c_stt:1;
 183                 uint64_t l2c_buff_emod:2;
 184                 uint64_t l2c_desc_emod:2;
 185                 uint64_t inv_reg_a2:1;
 186                 uint64_t reserved_8_8:1;
 187                 uint64_t l2c_addr_msb:8;
 188         } s;
 189         struct cvmx_uctlx_ohci_ctl_s          cn63xx;
 190         struct cvmx_uctlx_ohci_ctl_s          cn63xxp1;
 191 };
 192
 193 union cvmx_uctlx_orto_ctl {
 194         uint64_t u64;
 195         struct cvmx_uctlx_orto_ctl_s {
 196                 uint64_t reserved_32_63:32;
 197                 uint64_t to_val:24;
 198                 uint64_t reserved_0_7:8;
 199         } s;
 200         struct cvmx_uctlx_orto_ctl_s          cn63xx;
 201         struct cvmx_uctlx_orto_ctl_s          cn63xxp1;
 202 };
 203
 204 union cvmx_uctlx_ppaf_wm {
 205         uint64_t u64;
 206         struct cvmx_uctlx_ppaf_wm_s {
 207                 uint64_t reserved_5_63:59;
 208                 uint64_t wm:5;
 209         } s;
 210         struct cvmx_uctlx_ppaf_wm_s           cn63xx;
 211         struct cvmx_uctlx_ppaf_wm_s           cn63xxp1;
 212 };
 213
 214 union cvmx_uctlx_uphy_ctl_status {
 215         uint64_t u64;
 216         struct cvmx_uctlx_uphy_ctl_status_s {
 217                 uint64_t reserved_10_63:54;
 218                 uint64_t bist_done:1;
 219                 uint64_t bist_err:1;
 220                 uint64_t hsbist:1;
 221                 uint64_t fsbist:1;
 222                 uint64_t lsbist:1;
 223                 uint64_t siddq:1;
 224                 uint64_t vtest_en:1;
 225                 uint64_t uphy_bist:1;
 226                 uint64_t bist_en:1;
 227                 uint64_t ate_reset:1;
 228         } s;
 229         struct cvmx_uctlx_uphy_ctl_status_s   cn63xx;
 230         struct cvmx_uctlx_uphy_ctl_status_s   cn63xxp1;
 231 };
 232
 233 union cvmx_uctlx_uphy_portx_ctl_status {
 234         uint64_t u64;
 235         struct cvmx_uctlx_uphy_portx_ctl_status_s {
 236                 uint64_t reserved_43_63:21;
 237                 uint64_t tdata_out:4;
 238                 uint64_t txbiststuffenh:1;
 239                 uint64_t txbiststuffen:1;
 240                 uint64_t dmpulldown:1;
 241                 uint64_t dppulldown:1;
 242                 uint64_t vbusvldext:1;
 243                 uint64_t portreset:1;
 244                 uint64_t txhsvxtune:2;
 245                 uint64_t txvreftune:4;
 246                 uint64_t txrisetune:1;
 247                 uint64_t txpreemphasistune:1;
 248                 uint64_t txfslstune:4;
 249                 uint64_t sqrxtune:3;
 250                 uint64_t compdistune:3;
 251                 uint64_t loop_en:1;
 252                 uint64_t tclk:1;
 253                 uint64_t tdata_sel:1;
 254                 uint64_t taddr_in:4;
 255                 uint64_t tdata_in:8;
 256         } s;
 257         struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
 258         struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
 259 };
 260
 261 #endif