arch/mips/include/asm/octeon/cvmx-npi-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2010 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
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  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_NPI_DEFS_H__
  29 #define __CVMX_NPI_DEFS_H__
  30
  31 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
  32 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
  33 #define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
  34 #define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
  35 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
  36 #define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
  37 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
  38 #define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
  39 #define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
  40 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
  41 #define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
  42 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
  43 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
  44 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
  45 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
  46 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
  47 #define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
  48 #define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
  49 #define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
  50 #define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
  51 #define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
  52 #define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
  53 #define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
  54 #define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
  55 #define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
  56 #define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
  57 #define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
  58 #define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
  59 #define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
  60 #define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
  61 #define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
  62 #define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
  63 #define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
  64 #define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
  65 #define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
  66 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
  67 #define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
  68 #define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
  69 #define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
  70 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
  71 #define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
  72 #define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
  73 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
  74 #define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
  75 #define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
  76 #define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
  77 #define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
  78 #define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
  79 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
  80 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
  81 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
  82 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
  83 #define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
  84 #define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
  85 #define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
  86 #define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
  87 #define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
  88 #define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
  89 #define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
  90 #define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
  91 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
  92 #define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
  93 #define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
  94 #define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
  95 #define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
  96 #define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
  97 #define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
  98 #define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
  99 #define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
 100 #define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
 101 #define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
 102 #define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
 103 #define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
 104 #define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
 105 #define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
 106 #define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
 107 #define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
 108 #define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
 109 #define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
 110 #define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
 111 #define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
 112 #define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
 113 #define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
 114 #define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
 115 #define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
 116 #define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
 117 #define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
 118 #define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
 119 #define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
 120 #define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
 121 #define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
 122 #define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
 123 #define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
 124 #define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
 125 #define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
 126 #define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
 127 #define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
 128 #define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
 129 #define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
 130 #define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
 131 #define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
 132 #define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
 133 #define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
 134 #define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
 135 #define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
 136 #define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
 137 #define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
 138 #define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
 139 #define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
 140 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
 141 #define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
 142 #define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
 143 #define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
 144 #define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
 145 #define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
 146 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
 147 #define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
 148 #define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
 149 #define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
 150 #define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
 151
 152 union cvmx_npi_base_addr_inputx {
 153         uint64_t u64;
 154         struct cvmx_npi_base_addr_inputx_s {
 155                 uint64_t baddr:61;
 156                 uint64_t reserved_0_2:3;
 157         } s;
 158         struct cvmx_npi_base_addr_inputx_s cn30xx;
 159         struct cvmx_npi_base_addr_inputx_s cn31xx;
 160         struct cvmx_npi_base_addr_inputx_s cn38xx;
 161         struct cvmx_npi_base_addr_inputx_s cn38xxp2;
 162         struct cvmx_npi_base_addr_inputx_s cn50xx;
 163         struct cvmx_npi_base_addr_inputx_s cn58xx;
 164         struct cvmx_npi_base_addr_inputx_s cn58xxp1;
 165 };
 166
 167 union cvmx_npi_base_addr_outputx {
 168         uint64_t u64;
 169         struct cvmx_npi_base_addr_outputx_s {
 170                 uint64_t baddr:61;
 171                 uint64_t reserved_0_2:3;
 172         } s;
 173         struct cvmx_npi_base_addr_outputx_s cn30xx;
 174         struct cvmx_npi_base_addr_outputx_s cn31xx;
 175         struct cvmx_npi_base_addr_outputx_s cn38xx;
 176         struct cvmx_npi_base_addr_outputx_s cn38xxp2;
 177         struct cvmx_npi_base_addr_outputx_s cn50xx;
 178         struct cvmx_npi_base_addr_outputx_s cn58xx;
 179         struct cvmx_npi_base_addr_outputx_s cn58xxp1;
 180 };
 181
 182 union cvmx_npi_bist_status {
 183         uint64_t u64;
 184         struct cvmx_npi_bist_status_s {
 185                 uint64_t reserved_20_63:44;
 186                 uint64_t csr_bs:1;
 187                 uint64_t dif_bs:1;
 188                 uint64_t rdp_bs:1;
 189                 uint64_t pcnc_bs:1;
 190                 uint64_t pcn_bs:1;
 191                 uint64_t rdn_bs:1;
 192                 uint64_t pcac_bs:1;
 193                 uint64_t pcad_bs:1;
 194                 uint64_t rdnl_bs:1;
 195                 uint64_t pgf_bs:1;
 196                 uint64_t pig_bs:1;
 197                 uint64_t pof0_bs:1;
 198                 uint64_t pof1_bs:1;
 199                 uint64_t pof2_bs:1;
 200                 uint64_t pof3_bs:1;
 201                 uint64_t pos_bs:1;
 202                 uint64_t nus_bs:1;
 203                 uint64_t dob_bs:1;
 204                 uint64_t pdf_bs:1;
 205                 uint64_t dpi_bs:1;
 206         } s;
 207         struct cvmx_npi_bist_status_cn30xx {
 208                 uint64_t reserved_20_63:44;
 209                 uint64_t csr_bs:1;
 210                 uint64_t dif_bs:1;
 211                 uint64_t rdp_bs:1;
 212                 uint64_t pcnc_bs:1;
 213                 uint64_t pcn_bs:1;
 214                 uint64_t rdn_bs:1;
 215                 uint64_t pcac_bs:1;
 216                 uint64_t pcad_bs:1;
 217                 uint64_t rdnl_bs:1;
 218                 uint64_t pgf_bs:1;
 219                 uint64_t pig_bs:1;
 220                 uint64_t pof0_bs:1;
 221                 uint64_t reserved_5_7:3;
 222                 uint64_t pos_bs:1;
 223                 uint64_t nus_bs:1;
 224                 uint64_t dob_bs:1;
 225                 uint64_t pdf_bs:1;
 226                 uint64_t dpi_bs:1;
 227         } cn30xx;
 228         struct cvmx_npi_bist_status_s cn31xx;
 229         struct cvmx_npi_bist_status_s cn38xx;
 230         struct cvmx_npi_bist_status_s cn38xxp2;
 231         struct cvmx_npi_bist_status_cn50xx {
 232                 uint64_t reserved_20_63:44;
 233                 uint64_t csr_bs:1;
 234                 uint64_t dif_bs:1;
 235                 uint64_t rdp_bs:1;
 236                 uint64_t pcnc_bs:1;
 237                 uint64_t pcn_bs:1;
 238                 uint64_t rdn_bs:1;
 239                 uint64_t pcac_bs:1;
 240                 uint64_t pcad_bs:1;
 241                 uint64_t rdnl_bs:1;
 242                 uint64_t pgf_bs:1;
 243                 uint64_t pig_bs:1;
 244                 uint64_t pof0_bs:1;
 245                 uint64_t pof1_bs:1;
 246                 uint64_t reserved_5_6:2;
 247                 uint64_t pos_bs:1;
 248                 uint64_t nus_bs:1;
 249                 uint64_t dob_bs:1;
 250                 uint64_t pdf_bs:1;
 251                 uint64_t dpi_bs:1;
 252         } cn50xx;
 253         struct cvmx_npi_bist_status_s cn58xx;
 254         struct cvmx_npi_bist_status_s cn58xxp1;
 255 };
 256
 257 union cvmx_npi_buff_size_outputx {
 258         uint64_t u64;
 259         struct cvmx_npi_buff_size_outputx_s {
 260                 uint64_t reserved_23_63:41;
 261                 uint64_t isize:7;
 262                 uint64_t bsize:16;
 263         } s;
 264         struct cvmx_npi_buff_size_outputx_s cn30xx;
 265         struct cvmx_npi_buff_size_outputx_s cn31xx;
 266         struct cvmx_npi_buff_size_outputx_s cn38xx;
 267         struct cvmx_npi_buff_size_outputx_s cn38xxp2;
 268         struct cvmx_npi_buff_size_outputx_s cn50xx;
 269         struct cvmx_npi_buff_size_outputx_s cn58xx;
 270         struct cvmx_npi_buff_size_outputx_s cn58xxp1;
 271 };
 272
 273 union cvmx_npi_comp_ctl {
 274         uint64_t u64;
 275         struct cvmx_npi_comp_ctl_s {
 276                 uint64_t reserved_10_63:54;
 277                 uint64_t pctl:5;
 278                 uint64_t nctl:5;
 279         } s;
 280         struct cvmx_npi_comp_ctl_s cn50xx;
 281         struct cvmx_npi_comp_ctl_s cn58xx;
 282         struct cvmx_npi_comp_ctl_s cn58xxp1;
 283 };
 284
 285 union cvmx_npi_ctl_status {
 286         uint64_t u64;
 287         struct cvmx_npi_ctl_status_s {
 288                 uint64_t reserved_63_63:1;
 289                 uint64_t chip_rev:8;
 290                 uint64_t dis_pniw:1;
 291                 uint64_t out3_enb:1;
 292                 uint64_t out2_enb:1;
 293                 uint64_t out1_enb:1;
 294                 uint64_t out0_enb:1;
 295                 uint64_t ins3_enb:1;
 296                 uint64_t ins2_enb:1;
 297                 uint64_t ins1_enb:1;
 298                 uint64_t ins0_enb:1;
 299                 uint64_t ins3_64b:1;
 300                 uint64_t ins2_64b:1;
 301                 uint64_t ins1_64b:1;
 302                 uint64_t ins0_64b:1;
 303                 uint64_t pci_wdis:1;
 304                 uint64_t wait_com:1;
 305                 uint64_t reserved_37_39:3;
 306                 uint64_t max_word:5;
 307                 uint64_t reserved_10_31:22;
 308                 uint64_t timer:10;
 309         } s;
 310         struct cvmx_npi_ctl_status_cn30xx {
 311                 uint64_t reserved_63_63:1;
 312                 uint64_t chip_rev:8;
 313                 uint64_t dis_pniw:1;
 314                 uint64_t reserved_51_53:3;
 315                 uint64_t out0_enb:1;
 316                 uint64_t reserved_47_49:3;
 317                 uint64_t ins0_enb:1;
 318                 uint64_t reserved_43_45:3;
 319                 uint64_t ins0_64b:1;
 320                 uint64_t pci_wdis:1;
 321                 uint64_t wait_com:1;
 322                 uint64_t reserved_37_39:3;
 323                 uint64_t max_word:5;
 324                 uint64_t reserved_10_31:22;
 325                 uint64_t timer:10;
 326         } cn30xx;
 327         struct cvmx_npi_ctl_status_cn31xx {
 328                 uint64_t reserved_63_63:1;
 329                 uint64_t chip_rev:8;
 330                 uint64_t dis_pniw:1;
 331                 uint64_t reserved_52_53:2;
 332                 uint64_t out1_enb:1;
 333                 uint64_t out0_enb:1;
 334                 uint64_t reserved_48_49:2;
 335                 uint64_t ins1_enb:1;
 336                 uint64_t ins0_enb:1;
 337                 uint64_t reserved_44_45:2;
 338                 uint64_t ins1_64b:1;
 339                 uint64_t ins0_64b:1;
 340                 uint64_t pci_wdis:1;
 341                 uint64_t wait_com:1;
 342                 uint64_t reserved_37_39:3;
 343                 uint64_t max_word:5;
 344                 uint64_t reserved_10_31:22;
 345                 uint64_t timer:10;
 346         } cn31xx;
 347         struct cvmx_npi_ctl_status_s cn38xx;
 348         struct cvmx_npi_ctl_status_s cn38xxp2;
 349         struct cvmx_npi_ctl_status_cn31xx cn50xx;
 350         struct cvmx_npi_ctl_status_s cn58xx;
 351         struct cvmx_npi_ctl_status_s cn58xxp1;
 352 };
 353
 354 union cvmx_npi_dbg_select {
 355         uint64_t u64;
 356         struct cvmx_npi_dbg_select_s {
 357                 uint64_t reserved_16_63:48;
 358                 uint64_t dbg_sel:16;
 359         } s;
 360         struct cvmx_npi_dbg_select_s cn30xx;
 361         struct cvmx_npi_dbg_select_s cn31xx;
 362         struct cvmx_npi_dbg_select_s cn38xx;
 363         struct cvmx_npi_dbg_select_s cn38xxp2;
 364         struct cvmx_npi_dbg_select_s cn50xx;
 365         struct cvmx_npi_dbg_select_s cn58xx;
 366         struct cvmx_npi_dbg_select_s cn58xxp1;
 367 };
 368
 369 union cvmx_npi_dma_control {
 370         uint64_t u64;
 371         struct cvmx_npi_dma_control_s {
 372                 uint64_t reserved_36_63:28;
 373                 uint64_t b0_lend:1;
 374                 uint64_t dwb_denb:1;
 375                 uint64_t dwb_ichk:9;
 376                 uint64_t fpa_que:3;
 377                 uint64_t o_add1:1;
 378                 uint64_t o_ro:1;
 379                 uint64_t o_ns:1;
 380                 uint64_t o_es:2;
 381                 uint64_t o_mode:1;
 382                 uint64_t hp_enb:1;
 383                 uint64_t lp_enb:1;
 384                 uint64_t csize:14;
 385         } s;
 386         struct cvmx_npi_dma_control_s cn30xx;
 387         struct cvmx_npi_dma_control_s cn31xx;
 388         struct cvmx_npi_dma_control_s cn38xx;
 389         struct cvmx_npi_dma_control_s cn38xxp2;
 390         struct cvmx_npi_dma_control_s cn50xx;
 391         struct cvmx_npi_dma_control_s cn58xx;
 392         struct cvmx_npi_dma_control_s cn58xxp1;
 393 };
 394
 395 union cvmx_npi_dma_highp_counts {
 396         uint64_t u64;
 397         struct cvmx_npi_dma_highp_counts_s {
 398                 uint64_t reserved_39_63:25;
 399                 uint64_t fcnt:7;
 400                 uint64_t dbell:32;
 401         } s;
 402         struct cvmx_npi_dma_highp_counts_s cn30xx;
 403         struct cvmx_npi_dma_highp_counts_s cn31xx;
 404         struct cvmx_npi_dma_highp_counts_s cn38xx;
 405         struct cvmx_npi_dma_highp_counts_s cn38xxp2;
 406         struct cvmx_npi_dma_highp_counts_s cn50xx;
 407         struct cvmx_npi_dma_highp_counts_s cn58xx;
 408         struct cvmx_npi_dma_highp_counts_s cn58xxp1;
 409 };
 410
 411 union cvmx_npi_dma_highp_naddr {
 412         uint64_t u64;
 413         struct cvmx_npi_dma_highp_naddr_s {
 414                 uint64_t reserved_40_63:24;
 415                 uint64_t state:4;
 416                 uint64_t addr:36;
 417         } s;
 418         struct cvmx_npi_dma_highp_naddr_s cn30xx;
 419         struct cvmx_npi_dma_highp_naddr_s cn31xx;
 420         struct cvmx_npi_dma_highp_naddr_s cn38xx;
 421         struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
 422         struct cvmx_npi_dma_highp_naddr_s cn50xx;
 423         struct cvmx_npi_dma_highp_naddr_s cn58xx;
 424         struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
 425 };
 426
 427 union cvmx_npi_dma_lowp_counts {
 428         uint64_t u64;
 429         struct cvmx_npi_dma_lowp_counts_s {
 430                 uint64_t reserved_39_63:25;
 431                 uint64_t fcnt:7;
 432                 uint64_t dbell:32;
 433         } s;
 434         struct cvmx_npi_dma_lowp_counts_s cn30xx;
 435         struct cvmx_npi_dma_lowp_counts_s cn31xx;
 436         struct cvmx_npi_dma_lowp_counts_s cn38xx;
 437         struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
 438         struct cvmx_npi_dma_lowp_counts_s cn50xx;
 439         struct cvmx_npi_dma_lowp_counts_s cn58xx;
 440         struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
 441 };
 442
 443 union cvmx_npi_dma_lowp_naddr {
 444         uint64_t u64;
 445         struct cvmx_npi_dma_lowp_naddr_s {
 446                 uint64_t reserved_40_63:24;
 447                 uint64_t state:4;
 448                 uint64_t addr:36;
 449         } s;
 450         struct cvmx_npi_dma_lowp_naddr_s cn30xx;
 451         struct cvmx_npi_dma_lowp_naddr_s cn31xx;
 452         struct cvmx_npi_dma_lowp_naddr_s cn38xx;
 453         struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
 454         struct cvmx_npi_dma_lowp_naddr_s cn50xx;
 455         struct cvmx_npi_dma_lowp_naddr_s cn58xx;
 456         struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
 457 };
 458
 459 union cvmx_npi_highp_dbell {
 460         uint64_t u64;
 461         struct cvmx_npi_highp_dbell_s {
 462                 uint64_t reserved_16_63:48;
 463                 uint64_t dbell:16;
 464         } s;
 465         struct cvmx_npi_highp_dbell_s cn30xx;
 466         struct cvmx_npi_highp_dbell_s cn31xx;
 467         struct cvmx_npi_highp_dbell_s cn38xx;
 468         struct cvmx_npi_highp_dbell_s cn38xxp2;
 469         struct cvmx_npi_highp_dbell_s cn50xx;
 470         struct cvmx_npi_highp_dbell_s cn58xx;
 471         struct cvmx_npi_highp_dbell_s cn58xxp1;
 472 };
 473
 474 union cvmx_npi_highp_ibuff_saddr {
 475         uint64_t u64;
 476         struct cvmx_npi_highp_ibuff_saddr_s {
 477                 uint64_t reserved_36_63:28;
 478                 uint64_t saddr:36;
 479         } s;
 480         struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
 481         struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
 482         struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
 483         struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
 484         struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
 485         struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
 486         struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
 487 };
 488
 489 union cvmx_npi_input_control {
 490         uint64_t u64;
 491         struct cvmx_npi_input_control_s {
 492                 uint64_t reserved_23_63:41;
 493                 uint64_t pkt_rr:1;
 494                 uint64_t pbp_dhi:13;
 495                 uint64_t d_nsr:1;
 496                 uint64_t d_esr:2;
 497                 uint64_t d_ror:1;
 498                 uint64_t use_csr:1;
 499                 uint64_t nsr:1;
 500                 uint64_t esr:2;
 501                 uint64_t ror:1;
 502         } s;
 503         struct cvmx_npi_input_control_cn30xx {
 504                 uint64_t reserved_22_63:42;
 505                 uint64_t pbp_dhi:13;
 506                 uint64_t d_nsr:1;
 507                 uint64_t d_esr:2;
 508                 uint64_t d_ror:1;
 509                 uint64_t use_csr:1;
 510                 uint64_t nsr:1;
 511                 uint64_t esr:2;
 512                 uint64_t ror:1;
 513         } cn30xx;
 514         struct cvmx_npi_input_control_cn30xx cn31xx;
 515         struct cvmx_npi_input_control_s cn38xx;
 516         struct cvmx_npi_input_control_cn30xx cn38xxp2;
 517         struct cvmx_npi_input_control_s cn50xx;
 518         struct cvmx_npi_input_control_s cn58xx;
 519         struct cvmx_npi_input_control_s cn58xxp1;
 520 };
 521
 522 union cvmx_npi_int_enb {
 523         uint64_t u64;
 524         struct cvmx_npi_int_enb_s {
 525                 uint64_t reserved_62_63:2;
 526                 uint64_t q1_a_f:1;
 527                 uint64_t q1_s_e:1;
 528                 uint64_t pdf_p_f:1;
 529                 uint64_t pdf_p_e:1;
 530                 uint64_t pcf_p_f:1;
 531                 uint64_t pcf_p_e:1;
 532                 uint64_t rdx_s_e:1;
 533                 uint64_t rwx_s_e:1;
 534                 uint64_t pnc_a_f:1;
 535                 uint64_t pnc_s_e:1;
 536                 uint64_t com_a_f:1;
 537                 uint64_t com_s_e:1;
 538                 uint64_t q3_a_f:1;
 539                 uint64_t q3_s_e:1;
 540                 uint64_t q2_a_f:1;
 541                 uint64_t q2_s_e:1;
 542                 uint64_t pcr_a_f:1;
 543                 uint64_t pcr_s_e:1;
 544                 uint64_t fcr_a_f:1;
 545                 uint64_t fcr_s_e:1;
 546                 uint64_t iobdma:1;
 547                 uint64_t p_dperr:1;
 548                 uint64_t win_rto:1;
 549                 uint64_t i3_pperr:1;
 550                 uint64_t i2_pperr:1;
 551                 uint64_t i1_pperr:1;
 552                 uint64_t i0_pperr:1;
 553                 uint64_t p3_ptout:1;
 554                 uint64_t p2_ptout:1;
 555                 uint64_t p1_ptout:1;
 556                 uint64_t p0_ptout:1;
 557                 uint64_t p3_pperr:1;
 558                 uint64_t p2_pperr:1;
 559                 uint64_t p1_pperr:1;
 560                 uint64_t p0_pperr:1;
 561                 uint64_t g3_rtout:1;
 562                 uint64_t g2_rtout:1;
 563                 uint64_t g1_rtout:1;
 564                 uint64_t g0_rtout:1;
 565                 uint64_t p3_perr:1;
 566                 uint64_t p2_perr:1;
 567                 uint64_t p1_perr:1;
 568                 uint64_t p0_perr:1;
 569                 uint64_t p3_rtout:1;
 570                 uint64_t p2_rtout:1;
 571                 uint64_t p1_rtout:1;
 572                 uint64_t p0_rtout:1;
 573                 uint64_t i3_overf:1;
 574                 uint64_t i2_overf:1;
 575                 uint64_t i1_overf:1;
 576                 uint64_t i0_overf:1;
 577                 uint64_t i3_rtout:1;
 578                 uint64_t i2_rtout:1;
 579                 uint64_t i1_rtout:1;
 580                 uint64_t i0_rtout:1;
 581                 uint64_t po3_2sml:1;
 582                 uint64_t po2_2sml:1;
 583                 uint64_t po1_2sml:1;
 584                 uint64_t po0_2sml:1;
 585                 uint64_t pci_rsl:1;
 586                 uint64_t rml_wto:1;
 587                 uint64_t rml_rto:1;
 588         } s;
 589         struct cvmx_npi_int_enb_cn30xx {
 590                 uint64_t reserved_62_63:2;
 591                 uint64_t q1_a_f:1;
 592                 uint64_t q1_s_e:1;
 593                 uint64_t pdf_p_f:1;
 594                 uint64_t pdf_p_e:1;
 595                 uint64_t pcf_p_f:1;
 596                 uint64_t pcf_p_e:1;
 597                 uint64_t rdx_s_e:1;
 598                 uint64_t rwx_s_e:1;
 599                 uint64_t pnc_a_f:1;
 600                 uint64_t pnc_s_e:1;
 601                 uint64_t com_a_f:1;
 602                 uint64_t com_s_e:1;
 603                 uint64_t q3_a_f:1;
 604                 uint64_t q3_s_e:1;
 605                 uint64_t q2_a_f:1;
 606                 uint64_t q2_s_e:1;
 607                 uint64_t pcr_a_f:1;
 608                 uint64_t pcr_s_e:1;
 609                 uint64_t fcr_a_f:1;
 610                 uint64_t fcr_s_e:1;
 611                 uint64_t iobdma:1;
 612                 uint64_t p_dperr:1;
 613                 uint64_t win_rto:1;
 614                 uint64_t reserved_36_38:3;
 615                 uint64_t i0_pperr:1;
 616                 uint64_t reserved_32_34:3;
 617                 uint64_t p0_ptout:1;
 618                 uint64_t reserved_28_30:3;
 619                 uint64_t p0_pperr:1;
 620                 uint64_t reserved_24_26:3;
 621                 uint64_t g0_rtout:1;
 622                 uint64_t reserved_20_22:3;
 623                 uint64_t p0_perr:1;
 624                 uint64_t reserved_16_18:3;
 625                 uint64_t p0_rtout:1;
 626                 uint64_t reserved_12_14:3;
 627                 uint64_t i0_overf:1;
 628                 uint64_t reserved_8_10:3;
 629                 uint64_t i0_rtout:1;
 630                 uint64_t reserved_4_6:3;
 631                 uint64_t po0_2sml:1;
 632                 uint64_t pci_rsl:1;
 633                 uint64_t rml_wto:1;
 634                 uint64_t rml_rto:1;
 635         } cn30xx;
 636         struct cvmx_npi_int_enb_cn31xx {
 637                 uint64_t reserved_62_63:2;
 638                 uint64_t q1_a_f:1;
 639                 uint64_t q1_s_e:1;
 640                 uint64_t pdf_p_f:1;
 641                 uint64_t pdf_p_e:1;
 642                 uint64_t pcf_p_f:1;
 643                 uint64_t pcf_p_e:1;
 644                 uint64_t rdx_s_e:1;
 645                 uint64_t rwx_s_e:1;
 646                 uint64_t pnc_a_f:1;
 647                 uint64_t pnc_s_e:1;
 648                 uint64_t com_a_f:1;
 649                 uint64_t com_s_e:1;
 650                 uint64_t q3_a_f:1;
 651                 uint64_t q3_s_e:1;
 652                 uint64_t q2_a_f:1;
 653                 uint64_t q2_s_e:1;
 654                 uint64_t pcr_a_f:1;
 655                 uint64_t pcr_s_e:1;
 656                 uint64_t fcr_a_f:1;
 657                 uint64_t fcr_s_e:1;
 658                 uint64_t iobdma:1;
 659                 uint64_t p_dperr:1;
 660                 uint64_t win_rto:1;
 661                 uint64_t reserved_37_38:2;
 662                 uint64_t i1_pperr:1;
 663                 uint64_t i0_pperr:1;
 664                 uint64_t reserved_33_34:2;
 665                 uint64_t p1_ptout:1;
 666                 uint64_t p0_ptout:1;
 667                 uint64_t reserved_29_30:2;
 668                 uint64_t p1_pperr:1;
 669                 uint64_t p0_pperr:1;
 670                 uint64_t reserved_25_26:2;
 671                 uint64_t g1_rtout:1;
 672                 uint64_t g0_rtout:1;
 673                 uint64_t reserved_21_22:2;
 674                 uint64_t p1_perr:1;
 675                 uint64_t p0_perr:1;
 676                 uint64_t reserved_17_18:2;
 677                 uint64_t p1_rtout:1;
 678                 uint64_t p0_rtout:1;
 679                 uint64_t reserved_13_14:2;
 680                 uint64_t i1_overf:1;
 681                 uint64_t i0_overf:1;
 682                 uint64_t reserved_9_10:2;
 683                 uint64_t i1_rtout:1;
 684                 uint64_t i0_rtout:1;
 685                 uint64_t reserved_5_6:2;
 686                 uint64_t po1_2sml:1;
 687                 uint64_t po0_2sml:1;
 688                 uint64_t pci_rsl:1;
 689                 uint64_t rml_wto:1;
 690                 uint64_t rml_rto:1;
 691         } cn31xx;
 692         struct cvmx_npi_int_enb_s cn38xx;
 693         struct cvmx_npi_int_enb_cn38xxp2 {
 694                 uint64_t reserved_42_63:22;
 695                 uint64_t iobdma:1;
 696                 uint64_t p_dperr:1;
 697                 uint64_t win_rto:1;
 698                 uint64_t i3_pperr:1;
 699                 uint64_t i2_pperr:1;
 700                 uint64_t i1_pperr:1;
 701                 uint64_t i0_pperr:1;
 702                 uint64_t p3_ptout:1;
 703                 uint64_t p2_ptout:1;
 704                 uint64_t p1_ptout:1;
 705                 uint64_t p0_ptout:1;
 706                 uint64_t p3_pperr:1;
 707                 uint64_t p2_pperr:1;
 708                 uint64_t p1_pperr:1;
 709                 uint64_t p0_pperr:1;
 710                 uint64_t g3_rtout:1;
 711                 uint64_t g2_rtout:1;
 712                 uint64_t g1_rtout:1;
 713                 uint64_t g0_rtout:1;
 714                 uint64_t p3_perr:1;
 715                 uint64_t p2_perr:1;
 716                 uint64_t p1_perr:1;
 717                 uint64_t p0_perr:1;
 718                 uint64_t p3_rtout:1;
 719                 uint64_t p2_rtout:1;
 720                 uint64_t p1_rtout:1;
 721                 uint64_t p0_rtout:1;
 722                 uint64_t i3_overf:1;
 723                 uint64_t i2_overf:1;
 724                 uint64_t i1_overf:1;
 725                 uint64_t i0_overf:1;
 726                 uint64_t i3_rtout:1;
 727                 uint64_t i2_rtout:1;
 728                 uint64_t i1_rtout:1;
 729                 uint64_t i0_rtout:1;
 730                 uint64_t po3_2sml:1;
 731                 uint64_t po2_2sml:1;
 732                 uint64_t po1_2sml:1;
 733                 uint64_t po0_2sml:1;
 734                 uint64_t pci_rsl:1;
 735                 uint64_t rml_wto:1;
 736                 uint64_t rml_rto:1;
 737         } cn38xxp2;
 738         struct cvmx_npi_int_enb_cn31xx cn50xx;
 739         struct cvmx_npi_int_enb_s cn58xx;
 740         struct cvmx_npi_int_enb_s cn58xxp1;
 741 };
 742
 743 union cvmx_npi_int_sum {
 744         uint64_t u64;
 745         struct cvmx_npi_int_sum_s {
 746                 uint64_t reserved_62_63:2;
 747                 uint64_t q1_a_f:1;
 748                 uint64_t q1_s_e:1;
 749                 uint64_t pdf_p_f:1;
 750                 uint64_t pdf_p_e:1;
 751                 uint64_t pcf_p_f:1;
 752                 uint64_t pcf_p_e:1;
 753                 uint64_t rdx_s_e:1;
 754                 uint64_t rwx_s_e:1;
 755                 uint64_t pnc_a_f:1;
 756                 uint64_t pnc_s_e:1;
 757                 uint64_t com_a_f:1;
 758                 uint64_t com_s_e:1;
 759                 uint64_t q3_a_f:1;
 760                 uint64_t q3_s_e:1;
 761                 uint64_t q2_a_f:1;
 762                 uint64_t q2_s_e:1;
 763                 uint64_t pcr_a_f:1;
 764                 uint64_t pcr_s_e:1;
 765                 uint64_t fcr_a_f:1;
 766                 uint64_t fcr_s_e:1;
 767                 uint64_t iobdma:1;
 768                 uint64_t p_dperr:1;
 769                 uint64_t win_rto:1;
 770                 uint64_t i3_pperr:1;
 771                 uint64_t i2_pperr:1;
 772                 uint64_t i1_pperr:1;
 773                 uint64_t i0_pperr:1;
 774                 uint64_t p3_ptout:1;
 775                 uint64_t p2_ptout:1;
 776                 uint64_t p1_ptout:1;
 777                 uint64_t p0_ptout:1;
 778                 uint64_t p3_pperr:1;
 779                 uint64_t p2_pperr:1;
 780                 uint64_t p1_pperr:1;
 781                 uint64_t p0_pperr:1;
 782                 uint64_t g3_rtout:1;
 783                 uint64_t g2_rtout:1;
 784                 uint64_t g1_rtout:1;
 785                 uint64_t g0_rtout:1;
 786                 uint64_t p3_perr:1;
 787                 uint64_t p2_perr:1;
 788                 uint64_t p1_perr:1;
 789                 uint64_t p0_perr:1;
 790                 uint64_t p3_rtout:1;
 791                 uint64_t p2_rtout:1;
 792                 uint64_t p1_rtout:1;
 793                 uint64_t p0_rtout:1;
 794                 uint64_t i3_overf:1;
 795                 uint64_t i2_overf:1;
 796                 uint64_t i1_overf:1;
 797                 uint64_t i0_overf:1;
 798                 uint64_t i3_rtout:1;
 799                 uint64_t i2_rtout:1;
 800                 uint64_t i1_rtout:1;
 801                 uint64_t i0_rtout:1;
 802                 uint64_t po3_2sml:1;
 803                 uint64_t po2_2sml:1;
 804                 uint64_t po1_2sml:1;
 805                 uint64_t po0_2sml:1;
 806                 uint64_t pci_rsl:1;
 807                 uint64_t rml_wto:1;
 808                 uint64_t rml_rto:1;
 809         } s;
 810         struct cvmx_npi_int_sum_cn30xx {
 811                 uint64_t reserved_62_63:2;
 812                 uint64_t q1_a_f:1;
 813                 uint64_t q1_s_e:1;
 814                 uint64_t pdf_p_f:1;
 815                 uint64_t pdf_p_e:1;
 816                 uint64_t pcf_p_f:1;
 817                 uint64_t pcf_p_e:1;
 818                 uint64_t rdx_s_e:1;
 819                 uint64_t rwx_s_e:1;
 820                 uint64_t pnc_a_f:1;
 821                 uint64_t pnc_s_e:1;
 822                 uint64_t com_a_f:1;
 823                 uint64_t com_s_e:1;
 824                 uint64_t q3_a_f:1;
 825                 uint64_t q3_s_e:1;
 826                 uint64_t q2_a_f:1;
 827                 uint64_t q2_s_e:1;
 828                 uint64_t pcr_a_f:1;
 829                 uint64_t pcr_s_e:1;
 830                 uint64_t fcr_a_f:1;
 831                 uint64_t fcr_s_e:1;
 832                 uint64_t iobdma:1;
 833                 uint64_t p_dperr:1;
 834                 uint64_t win_rto:1;
 835                 uint64_t reserved_36_38:3;
 836                 uint64_t i0_pperr:1;
 837                 uint64_t reserved_32_34:3;
 838                 uint64_t p0_ptout:1;
 839                 uint64_t reserved_28_30:3;
 840                 uint64_t p0_pperr:1;
 841                 uint64_t reserved_24_26:3;
 842                 uint64_t g0_rtout:1;
 843                 uint64_t reserved_20_22:3;
 844                 uint64_t p0_perr:1;
 845                 uint64_t reserved_16_18:3;
 846                 uint64_t p0_rtout:1;
 847                 uint64_t reserved_12_14:3;
 848                 uint64_t i0_overf:1;
 849                 uint64_t reserved_8_10:3;
 850                 uint64_t i0_rtout:1;
 851                 uint64_t reserved_4_6:3;
 852                 uint64_t po0_2sml:1;
 853                 uint64_t pci_rsl:1;
 854                 uint64_t rml_wto:1;
 855                 uint64_t rml_rto:1;
 856         } cn30xx;
 857         struct cvmx_npi_int_sum_cn31xx {
 858                 uint64_t reserved_62_63:2;
 859                 uint64_t q1_a_f:1;
 860                 uint64_t q1_s_e:1;
 861                 uint64_t pdf_p_f:1;
 862                 uint64_t pdf_p_e:1;
 863                 uint64_t pcf_p_f:1;
 864                 uint64_t pcf_p_e:1;
 865                 uint64_t rdx_s_e:1;
 866                 uint64_t rwx_s_e:1;
 867                 uint64_t pnc_a_f:1;
 868                 uint64_t pnc_s_e:1;
 869                 uint64_t com_a_f:1;
 870                 uint64_t com_s_e:1;
 871                 uint64_t q3_a_f:1;
 872                 uint64_t q3_s_e:1;
 873                 uint64_t q2_a_f:1;
 874                 uint64_t q2_s_e:1;
 875                 uint64_t pcr_a_f:1;
 876                 uint64_t pcr_s_e:1;
 877                 uint64_t fcr_a_f:1;
 878                 uint64_t fcr_s_e:1;
 879                 uint64_t iobdma:1;
 880                 uint64_t p_dperr:1;
 881                 uint64_t win_rto:1;
 882                 uint64_t reserved_37_38:2;
 883                 uint64_t i1_pperr:1;
 884                 uint64_t i0_pperr:1;
 885                 uint64_t reserved_33_34:2;
 886                 uint64_t p1_ptout:1;
 887                 uint64_t p0_ptout:1;
 888                 uint64_t reserved_29_30:2;
 889                 uint64_t p1_pperr:1;
 890                 uint64_t p0_pperr:1;
 891                 uint64_t reserved_25_26:2;
 892                 uint64_t g1_rtout:1;
 893                 uint64_t g0_rtout:1;
 894                 uint64_t reserved_21_22:2;
 895                 uint64_t p1_perr:1;
 896                 uint64_t p0_perr:1;
 897                 uint64_t reserved_17_18:2;
 898                 uint64_t p1_rtout:1;
 899                 uint64_t p0_rtout:1;
 900                 uint64_t reserved_13_14:2;
 901                 uint64_t i1_overf:1;
 902                 uint64_t i0_overf:1;
 903                 uint64_t reserved_9_10:2;
 904                 uint64_t i1_rtout:1;
 905                 uint64_t i0_rtout:1;
 906                 uint64_t reserved_5_6:2;
 907                 uint64_t po1_2sml:1;
 908                 uint64_t po0_2sml:1;
 909                 uint64_t pci_rsl:1;
 910                 uint64_t rml_wto:1;
 911                 uint64_t rml_rto:1;
 912         } cn31xx;
 913         struct cvmx_npi_int_sum_s cn38xx;
 914         struct cvmx_npi_int_sum_cn38xxp2 {
 915                 uint64_t reserved_42_63:22;
 916                 uint64_t iobdma:1;
 917                 uint64_t p_dperr:1;
 918                 uint64_t win_rto:1;
 919                 uint64_t i3_pperr:1;
 920                 uint64_t i2_pperr:1;
 921                 uint64_t i1_pperr:1;
 922                 uint64_t i0_pperr:1;
 923                 uint64_t p3_ptout:1;
 924                 uint64_t p2_ptout:1;
 925                 uint64_t p1_ptout:1;
 926                 uint64_t p0_ptout:1;
 927                 uint64_t p3_pperr:1;
 928                 uint64_t p2_pperr:1;
 929                 uint64_t p1_pperr:1;
 930                 uint64_t p0_pperr:1;
 931                 uint64_t g3_rtout:1;
 932                 uint64_t g2_rtout:1;
 933                 uint64_t g1_rtout:1;
 934                 uint64_t g0_rtout:1;
 935                 uint64_t p3_perr:1;
 936                 uint64_t p2_perr:1;
 937                 uint64_t p1_perr:1;
 938                 uint64_t p0_perr:1;
 939                 uint64_t p3_rtout:1;
 940                 uint64_t p2_rtout:1;
 941                 uint64_t p1_rtout:1;
 942                 uint64_t p0_rtout:1;
 943                 uint64_t i3_overf:1;
 944                 uint64_t i2_overf:1;
 945                 uint64_t i1_overf:1;
 946                 uint64_t i0_overf:1;
 947                 uint64_t i3_rtout:1;
 948                 uint64_t i2_rtout:1;
 949                 uint64_t i1_rtout:1;
 950                 uint64_t i0_rtout:1;
 951                 uint64_t po3_2sml:1;
 952                 uint64_t po2_2sml:1;
 953                 uint64_t po1_2sml:1;
 954                 uint64_t po0_2sml:1;
 955                 uint64_t pci_rsl:1;
 956                 uint64_t rml_wto:1;
 957                 uint64_t rml_rto:1;
 958         } cn38xxp2;
 959         struct cvmx_npi_int_sum_cn31xx cn50xx;
 960         struct cvmx_npi_int_sum_s cn58xx;
 961         struct cvmx_npi_int_sum_s cn58xxp1;
 962 };
 963
 964 union cvmx_npi_lowp_dbell {
 965         uint64_t u64;
 966         struct cvmx_npi_lowp_dbell_s {
 967                 uint64_t reserved_16_63:48;
 968                 uint64_t dbell:16;
 969         } s;
 970         struct cvmx_npi_lowp_dbell_s cn30xx;
 971         struct cvmx_npi_lowp_dbell_s cn31xx;
 972         struct cvmx_npi_lowp_dbell_s cn38xx;
 973         struct cvmx_npi_lowp_dbell_s cn38xxp2;
 974         struct cvmx_npi_lowp_dbell_s cn50xx;
 975         struct cvmx_npi_lowp_dbell_s cn58xx;
 976         struct cvmx_npi_lowp_dbell_s cn58xxp1;
 977 };
 978
 979 union cvmx_npi_lowp_ibuff_saddr {
 980         uint64_t u64;
 981         struct cvmx_npi_lowp_ibuff_saddr_s {
 982                 uint64_t reserved_36_63:28;
 983                 uint64_t saddr:36;
 984         } s;
 985         struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
 986         struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
 987         struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
 988         struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
 989         struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
 990         struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
 991         struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
 992 };
 993
 994 union cvmx_npi_mem_access_subidx {
 995         uint64_t u64;
 996         struct cvmx_npi_mem_access_subidx_s {
 997                 uint64_t reserved_38_63:26;
 998                 uint64_t shortl:1;
 999                 uint64_t nmerge:1;
1000                 uint64_t esr:2;
1001                 uint64_t esw:2;
1002                 uint64_t nsr:1;
1003                 uint64_t nsw:1;
1004                 uint64_t ror:1;
1005                 uint64_t row:1;
1006                 uint64_t ba:28;
1007         } s;
1008         struct cvmx_npi_mem_access_subidx_s cn30xx;
1009         struct cvmx_npi_mem_access_subidx_cn31xx {
1010                 uint64_t reserved_36_63:28;
1011                 uint64_t esr:2;
1012                 uint64_t esw:2;
1013                 uint64_t nsr:1;
1014                 uint64_t nsw:1;
1015                 uint64_t ror:1;
1016                 uint64_t row:1;
1017                 uint64_t ba:28;
1018         } cn31xx;
1019         struct cvmx_npi_mem_access_subidx_s cn38xx;
1020         struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1021         struct cvmx_npi_mem_access_subidx_s cn50xx;
1022         struct cvmx_npi_mem_access_subidx_s cn58xx;
1023         struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1024 };
1025
1026 union cvmx_npi_msi_rcv {
1027         uint64_t u64;
1028         struct cvmx_npi_msi_rcv_s {
1029                 uint64_t int_vec:64;
1030         } s;
1031         struct cvmx_npi_msi_rcv_s cn30xx;
1032         struct cvmx_npi_msi_rcv_s cn31xx;
1033         struct cvmx_npi_msi_rcv_s cn38xx;
1034         struct cvmx_npi_msi_rcv_s cn38xxp2;
1035         struct cvmx_npi_msi_rcv_s cn50xx;
1036         struct cvmx_npi_msi_rcv_s cn58xx;
1037         struct cvmx_npi_msi_rcv_s cn58xxp1;
1038 };
1039
1040 union cvmx_npi_num_desc_outputx {
1041         uint64_t u64;
1042         struct cvmx_npi_num_desc_outputx_s {
1043                 uint64_t reserved_32_63:32;
1044                 uint64_t size:32;
1045         } s;
1046         struct cvmx_npi_num_desc_outputx_s cn30xx;
1047         struct cvmx_npi_num_desc_outputx_s cn31xx;
1048         struct cvmx_npi_num_desc_outputx_s cn38xx;
1049         struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1050         struct cvmx_npi_num_desc_outputx_s cn50xx;
1051         struct cvmx_npi_num_desc_outputx_s cn58xx;
1052         struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1053 };
1054
1055 union cvmx_npi_output_control {
1056         uint64_t u64;
1057         struct cvmx_npi_output_control_s {
1058                 uint64_t reserved_49_63:15;
1059                 uint64_t pkt_rr:1;
1060                 uint64_t p3_bmode:1;
1061                 uint64_t p2_bmode:1;
1062                 uint64_t p1_bmode:1;
1063                 uint64_t p0_bmode:1;
1064                 uint64_t o3_es:2;
1065                 uint64_t o3_ns:1;
1066                 uint64_t o3_ro:1;
1067                 uint64_t o2_es:2;
1068                 uint64_t o2_ns:1;
1069                 uint64_t o2_ro:1;
1070                 uint64_t o1_es:2;
1071                 uint64_t o1_ns:1;
1072                 uint64_t o1_ro:1;
1073                 uint64_t o0_es:2;
1074                 uint64_t o0_ns:1;
1075                 uint64_t o0_ro:1;
1076                 uint64_t o3_csrm:1;
1077                 uint64_t o2_csrm:1;
1078                 uint64_t o1_csrm:1;
1079                 uint64_t o0_csrm:1;
1080                 uint64_t reserved_20_23:4;
1081                 uint64_t iptr_o3:1;
1082                 uint64_t iptr_o2:1;
1083                 uint64_t iptr_o1:1;
1084                 uint64_t iptr_o0:1;
1085                 uint64_t esr_sl3:2;
1086                 uint64_t nsr_sl3:1;
1087                 uint64_t ror_sl3:1;
1088                 uint64_t esr_sl2:2;
1089                 uint64_t nsr_sl2:1;
1090                 uint64_t ror_sl2:1;
1091                 uint64_t esr_sl1:2;
1092                 uint64_t nsr_sl1:1;
1093                 uint64_t ror_sl1:1;
1094                 uint64_t esr_sl0:2;
1095                 uint64_t nsr_sl0:1;
1096                 uint64_t ror_sl0:1;
1097         } s;
1098         struct cvmx_npi_output_control_cn30xx {
1099                 uint64_t reserved_45_63:19;
1100                 uint64_t p0_bmode:1;
1101                 uint64_t reserved_32_43:12;
1102                 uint64_t o0_es:2;
1103                 uint64_t o0_ns:1;
1104                 uint64_t o0_ro:1;
1105                 uint64_t reserved_25_27:3;
1106                 uint64_t o0_csrm:1;
1107                 uint64_t reserved_17_23:7;
1108                 uint64_t iptr_o0:1;
1109                 uint64_t reserved_4_15:12;
1110                 uint64_t esr_sl0:2;
1111                 uint64_t nsr_sl0:1;
1112                 uint64_t ror_sl0:1;
1113         } cn30xx;
1114         struct cvmx_npi_output_control_cn31xx {
1115                 uint64_t reserved_46_63:18;
1116                 uint64_t p1_bmode:1;
1117                 uint64_t p0_bmode:1;
1118                 uint64_t reserved_36_43:8;
1119                 uint64_t o1_es:2;
1120                 uint64_t o1_ns:1;
1121                 uint64_t o1_ro:1;
1122                 uint64_t o0_es:2;
1123                 uint64_t o0_ns:1;
1124                 uint64_t o0_ro:1;
1125                 uint64_t reserved_26_27:2;
1126                 uint64_t o1_csrm:1;
1127                 uint64_t o0_csrm:1;
1128                 uint64_t reserved_18_23:6;
1129                 uint64_t iptr_o1:1;
1130                 uint64_t iptr_o0:1;
1131                 uint64_t reserved_8_15:8;
1132                 uint64_t esr_sl1:2;
1133                 uint64_t nsr_sl1:1;
1134                 uint64_t ror_sl1:1;
1135                 uint64_t esr_sl0:2;
1136                 uint64_t nsr_sl0:1;
1137                 uint64_t ror_sl0:1;
1138         } cn31xx;
1139         struct cvmx_npi_output_control_s cn38xx;
1140         struct cvmx_npi_output_control_cn38xxp2 {
1141                 uint64_t reserved_48_63:16;
1142                 uint64_t p3_bmode:1;
1143                 uint64_t p2_bmode:1;
1144                 uint64_t p1_bmode:1;
1145                 uint64_t p0_bmode:1;
1146                 uint64_t o3_es:2;
1147                 uint64_t o3_ns:1;
1148                 uint64_t o3_ro:1;
1149                 uint64_t o2_es:2;
1150                 uint64_t o2_ns:1;
1151                 uint64_t o2_ro:1;
1152                 uint64_t o1_es:2;
1153                 uint64_t o1_ns:1;
1154                 uint64_t o1_ro:1;
1155                 uint64_t o0_es:2;
1156                 uint64_t o0_ns:1;
1157                 uint64_t o0_ro:1;
1158                 uint64_t o3_csrm:1;
1159                 uint64_t o2_csrm:1;
1160                 uint64_t o1_csrm:1;
1161                 uint64_t o0_csrm:1;
1162                 uint64_t reserved_20_23:4;
1163                 uint64_t iptr_o3:1;
1164                 uint64_t iptr_o2:1;
1165                 uint64_t iptr_o1:1;
1166                 uint64_t iptr_o0:1;
1167                 uint64_t esr_sl3:2;
1168                 uint64_t nsr_sl3:1;
1169                 uint64_t ror_sl3:1;
1170                 uint64_t esr_sl2:2;
1171                 uint64_t nsr_sl2:1;
1172                 uint64_t ror_sl2:1;
1173                 uint64_t esr_sl1:2;
1174                 uint64_t nsr_sl1:1;
1175                 uint64_t ror_sl1:1;
1176                 uint64_t esr_sl0:2;
1177                 uint64_t nsr_sl0:1;
1178                 uint64_t ror_sl0:1;
1179         } cn38xxp2;
1180         struct cvmx_npi_output_control_cn50xx {
1181                 uint64_t reserved_49_63:15;
1182                 uint64_t pkt_rr:1;
1183                 uint64_t reserved_46_47:2;
1184                 uint64_t p1_bmode:1;
1185                 uint64_t p0_bmode:1;
1186                 uint64_t reserved_36_43:8;
1187                 uint64_t o1_es:2;
1188                 uint64_t o1_ns:1;
1189                 uint64_t o1_ro:1;
1190                 uint64_t o0_es:2;
1191                 uint64_t o0_ns:1;
1192                 uint64_t o0_ro:1;
1193                 uint64_t reserved_26_27:2;
1194                 uint64_t o1_csrm:1;
1195                 uint64_t o0_csrm:1;
1196                 uint64_t reserved_18_23:6;
1197                 uint64_t iptr_o1:1;
1198                 uint64_t iptr_o0:1;
1199                 uint64_t reserved_8_15:8;
1200                 uint64_t esr_sl1:2;
1201                 uint64_t nsr_sl1:1;
1202                 uint64_t ror_sl1:1;
1203                 uint64_t esr_sl0:2;
1204                 uint64_t nsr_sl0:1;
1205                 uint64_t ror_sl0:1;
1206         } cn50xx;
1207         struct cvmx_npi_output_control_s cn58xx;
1208         struct cvmx_npi_output_control_s cn58xxp1;
1209 };
1210
1211 union cvmx_npi_px_dbpair_addr {
1212         uint64_t u64;
1213         struct cvmx_npi_px_dbpair_addr_s {
1214                 uint64_t reserved_63_63:1;
1215                 uint64_t state:2;
1216                 uint64_t naddr:61;
1217         } s;
1218         struct cvmx_npi_px_dbpair_addr_s cn30xx;
1219         struct cvmx_npi_px_dbpair_addr_s cn31xx;
1220         struct cvmx_npi_px_dbpair_addr_s cn38xx;
1221         struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
1222         struct cvmx_npi_px_dbpair_addr_s cn50xx;
1223         struct cvmx_npi_px_dbpair_addr_s cn58xx;
1224         struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
1225 };
1226
1227 union cvmx_npi_px_instr_addr {
1228         uint64_t u64;
1229         struct cvmx_npi_px_instr_addr_s {
1230                 uint64_t state:3;
1231                 uint64_t naddr:61;
1232         } s;
1233         struct cvmx_npi_px_instr_addr_s cn30xx;
1234         struct cvmx_npi_px_instr_addr_s cn31xx;
1235         struct cvmx_npi_px_instr_addr_s cn38xx;
1236         struct cvmx_npi_px_instr_addr_s cn38xxp2;
1237         struct cvmx_npi_px_instr_addr_s cn50xx;
1238         struct cvmx_npi_px_instr_addr_s cn58xx;
1239         struct cvmx_npi_px_instr_addr_s cn58xxp1;
1240 };
1241
1242 union cvmx_npi_px_instr_cnts {
1243         uint64_t u64;
1244         struct cvmx_npi_px_instr_cnts_s {
1245                 uint64_t reserved_38_63:26;
1246                 uint64_t fcnt:6;
1247                 uint64_t avail:32;
1248         } s;
1249         struct cvmx_npi_px_instr_cnts_s cn30xx;
1250         struct cvmx_npi_px_instr_cnts_s cn31xx;
1251         struct cvmx_npi_px_instr_cnts_s cn38xx;
1252         struct cvmx_npi_px_instr_cnts_s cn38xxp2;
1253         struct cvmx_npi_px_instr_cnts_s cn50xx;
1254         struct cvmx_npi_px_instr_cnts_s cn58xx;
1255         struct cvmx_npi_px_instr_cnts_s cn58xxp1;
1256 };
1257
1258 union cvmx_npi_px_pair_cnts {
1259         uint64_t u64;
1260         struct cvmx_npi_px_pair_cnts_s {
1261                 uint64_t reserved_37_63:27;
1262                 uint64_t fcnt:5;
1263                 uint64_t avail:32;
1264         } s;
1265         struct cvmx_npi_px_pair_cnts_s cn30xx;
1266         struct cvmx_npi_px_pair_cnts_s cn31xx;
1267         struct cvmx_npi_px_pair_cnts_s cn38xx;
1268         struct cvmx_npi_px_pair_cnts_s cn38xxp2;
1269         struct cvmx_npi_px_pair_cnts_s cn50xx;
1270         struct cvmx_npi_px_pair_cnts_s cn58xx;
1271         struct cvmx_npi_px_pair_cnts_s cn58xxp1;
1272 };
1273
1274 union cvmx_npi_pci_burst_size {
1275         uint64_t u64;
1276         struct cvmx_npi_pci_burst_size_s {
1277                 uint64_t reserved_14_63:50;
1278                 uint64_t wr_brst:7;
1279                 uint64_t rd_brst:7;
1280         } s;
1281         struct cvmx_npi_pci_burst_size_s cn30xx;
1282         struct cvmx_npi_pci_burst_size_s cn31xx;
1283         struct cvmx_npi_pci_burst_size_s cn38xx;
1284         struct cvmx_npi_pci_burst_size_s cn38xxp2;
1285         struct cvmx_npi_pci_burst_size_s cn50xx;
1286         struct cvmx_npi_pci_burst_size_s cn58xx;
1287         struct cvmx_npi_pci_burst_size_s cn58xxp1;
1288 };
1289
1290 union cvmx_npi_pci_int_arb_cfg {
1291         uint64_t u64;
1292         struct cvmx_npi_pci_int_arb_cfg_s {
1293                 uint64_t reserved_13_63:51;
1294                 uint64_t hostmode:1;
1295                 uint64_t pci_ovr:4;
1296                 uint64_t reserved_5_7:3;
1297                 uint64_t en:1;
1298                 uint64_t park_mod:1;
1299                 uint64_t park_dev:3;
1300         } s;
1301         struct cvmx_npi_pci_int_arb_cfg_cn30xx {
1302                 uint64_t reserved_5_63:59;
1303                 uint64_t en:1;
1304                 uint64_t park_mod:1;
1305                 uint64_t park_dev:3;
1306         } cn30xx;
1307         struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
1308         struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
1309         struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
1310         struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
1311         struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
1312         struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
1313 };
1314
1315 union cvmx_npi_pci_read_cmd {
1316         uint64_t u64;
1317         struct cvmx_npi_pci_read_cmd_s {
1318                 uint64_t reserved_11_63:53;
1319                 uint64_t cmd_size:11;
1320         } s;
1321         struct cvmx_npi_pci_read_cmd_s cn30xx;
1322         struct cvmx_npi_pci_read_cmd_s cn31xx;
1323         struct cvmx_npi_pci_read_cmd_s cn38xx;
1324         struct cvmx_npi_pci_read_cmd_s cn38xxp2;
1325         struct cvmx_npi_pci_read_cmd_s cn50xx;
1326         struct cvmx_npi_pci_read_cmd_s cn58xx;
1327         struct cvmx_npi_pci_read_cmd_s cn58xxp1;
1328 };
1329
1330 union cvmx_npi_port32_instr_hdr {
1331         uint64_t u64;
1332         struct cvmx_npi_port32_instr_hdr_s {
1333                 uint64_t reserved_44_63:20;
1334                 uint64_t pbp:1;
1335                 uint64_t rsv_f:5;
1336                 uint64_t rparmode:2;
1337                 uint64_t rsv_e:1;
1338                 uint64_t rskp_len:7;
1339                 uint64_t rsv_d:6;
1340                 uint64_t use_ihdr:1;
1341                 uint64_t rsv_c:5;
1342                 uint64_t par_mode:2;
1343                 uint64_t rsv_b:1;
1344                 uint64_t skp_len:7;
1345                 uint64_t rsv_a:6;
1346         } s;
1347         struct cvmx_npi_port32_instr_hdr_s cn30xx;
1348         struct cvmx_npi_port32_instr_hdr_s cn31xx;
1349         struct cvmx_npi_port32_instr_hdr_s cn38xx;
1350         struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
1351         struct cvmx_npi_port32_instr_hdr_s cn50xx;
1352         struct cvmx_npi_port32_instr_hdr_s cn58xx;
1353         struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
1354 };
1355
1356 union cvmx_npi_port33_instr_hdr {
1357         uint64_t u64;
1358         struct cvmx_npi_port33_instr_hdr_s {
1359                 uint64_t reserved_44_63:20;
1360                 uint64_t pbp:1;
1361                 uint64_t rsv_f:5;
1362                 uint64_t rparmode:2;
1363                 uint64_t rsv_e:1;
1364                 uint64_t rskp_len:7;
1365                 uint64_t rsv_d:6;
1366                 uint64_t use_ihdr:1;
1367                 uint64_t rsv_c:5;
1368                 uint64_t par_mode:2;
1369                 uint64_t rsv_b:1;
1370                 uint64_t skp_len:7;
1371                 uint64_t rsv_a:6;
1372         } s;
1373         struct cvmx_npi_port33_instr_hdr_s cn31xx;
1374         struct cvmx_npi_port33_instr_hdr_s cn38xx;
1375         struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
1376         struct cvmx_npi_port33_instr_hdr_s cn50xx;
1377         struct cvmx_npi_port33_instr_hdr_s cn58xx;
1378         struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
1379 };
1380
1381 union cvmx_npi_port34_instr_hdr {
1382         uint64_t u64;
1383         struct cvmx_npi_port34_instr_hdr_s {
1384                 uint64_t reserved_44_63:20;
1385                 uint64_t pbp:1;
1386                 uint64_t rsv_f:5;
1387                 uint64_t rparmode:2;
1388                 uint64_t rsv_e:1;
1389                 uint64_t rskp_len:7;
1390                 uint64_t rsv_d:6;
1391                 uint64_t use_ihdr:1;
1392                 uint64_t rsv_c:5;
1393                 uint64_t par_mode:2;
1394                 uint64_t rsv_b:1;
1395                 uint64_t skp_len:7;
1396                 uint64_t rsv_a:6;
1397         } s;
1398         struct cvmx_npi_port34_instr_hdr_s cn38xx;
1399         struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
1400         struct cvmx_npi_port34_instr_hdr_s cn58xx;
1401         struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
1402 };
1403
1404 union cvmx_npi_port35_instr_hdr {
1405         uint64_t u64;
1406         struct cvmx_npi_port35_instr_hdr_s {
1407                 uint64_t reserved_44_63:20;
1408                 uint64_t pbp:1;
1409                 uint64_t rsv_f:5;
1410                 uint64_t rparmode:2;
1411                 uint64_t rsv_e:1;
1412                 uint64_t rskp_len:7;
1413                 uint64_t rsv_d:6;
1414                 uint64_t use_ihdr:1;
1415                 uint64_t rsv_c:5;
1416                 uint64_t par_mode:2;
1417                 uint64_t rsv_b:1;
1418                 uint64_t skp_len:7;
1419                 uint64_t rsv_a:6;
1420         } s;
1421         struct cvmx_npi_port35_instr_hdr_s cn38xx;
1422         struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
1423         struct cvmx_npi_port35_instr_hdr_s cn58xx;
1424         struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
1425 };
1426
1427 union cvmx_npi_port_bp_control {
1428         uint64_t u64;
1429         struct cvmx_npi_port_bp_control_s {
1430                 uint64_t reserved_8_63:56;
1431                 uint64_t bp_on:4;
1432                 uint64_t enb:4;
1433         } s;
1434         struct cvmx_npi_port_bp_control_s cn30xx;
1435         struct cvmx_npi_port_bp_control_s cn31xx;
1436         struct cvmx_npi_port_bp_control_s cn38xx;
1437         struct cvmx_npi_port_bp_control_s cn38xxp2;
1438         struct cvmx_npi_port_bp_control_s cn50xx;
1439         struct cvmx_npi_port_bp_control_s cn58xx;
1440         struct cvmx_npi_port_bp_control_s cn58xxp1;
1441 };
1442
1443 union cvmx_npi_rsl_int_blocks {
1444         uint64_t u64;
1445         struct cvmx_npi_rsl_int_blocks_s {
1446                 uint64_t reserved_32_63:32;
1447                 uint64_t rint_31:1;
1448                 uint64_t iob:1;
1449                 uint64_t reserved_28_29:2;
1450                 uint64_t rint_27:1;
1451                 uint64_t rint_26:1;
1452                 uint64_t rint_25:1;
1453                 uint64_t rint_24:1;
1454                 uint64_t asx1:1;
1455                 uint64_t asx0:1;
1456                 uint64_t rint_21:1;
1457                 uint64_t pip:1;
1458                 uint64_t spx1:1;
1459                 uint64_t spx0:1;
1460                 uint64_t lmc:1;
1461                 uint64_t l2c:1;
1462                 uint64_t rint_15:1;
1463                 uint64_t reserved_13_14:2;
1464                 uint64_t pow:1;
1465                 uint64_t tim:1;
1466                 uint64_t pko:1;
1467                 uint64_t ipd:1;
1468                 uint64_t rint_8:1;
1469                 uint64_t zip:1;
1470                 uint64_t dfa:1;
1471                 uint64_t fpa:1;
1472                 uint64_t key:1;
1473                 uint64_t npi:1;
1474                 uint64_t gmx1:1;
1475                 uint64_t gmx0:1;
1476                 uint64_t mio:1;
1477         } s;
1478         struct cvmx_npi_rsl_int_blocks_cn30xx {
1479                 uint64_t reserved_32_63:32;
1480                 uint64_t rint_31:1;
1481                 uint64_t iob:1;
1482                 uint64_t rint_29:1;
1483                 uint64_t rint_28:1;
1484                 uint64_t rint_27:1;
1485                 uint64_t rint_26:1;
1486                 uint64_t rint_25:1;
1487                 uint64_t rint_24:1;
1488                 uint64_t asx1:1;
1489                 uint64_t asx0:1;
1490                 uint64_t rint_21:1;
1491                 uint64_t pip:1;
1492                 uint64_t spx1:1;
1493                 uint64_t spx0:1;
1494                 uint64_t lmc:1;
1495                 uint64_t l2c:1;
1496                 uint64_t rint_15:1;
1497                 uint64_t rint_14:1;
1498                 uint64_t usb:1;
1499                 uint64_t pow:1;
1500                 uint64_t tim:1;
1501                 uint64_t pko:1;
1502                 uint64_t ipd:1;
1503                 uint64_t rint_8:1;
1504                 uint64_t zip:1;
1505                 uint64_t dfa:1;
1506                 uint64_t fpa:1;
1507                 uint64_t key:1;
1508                 uint64_t npi:1;
1509                 uint64_t gmx1:1;
1510                 uint64_t gmx0:1;
1511                 uint64_t mio:1;
1512         } cn30xx;
1513         struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
1514         struct cvmx_npi_rsl_int_blocks_cn38xx {
1515                 uint64_t reserved_32_63:32;
1516                 uint64_t rint_31:1;
1517                 uint64_t iob:1;
1518                 uint64_t rint_29:1;
1519                 uint64_t rint_28:1;
1520                 uint64_t rint_27:1;
1521                 uint64_t rint_26:1;
1522                 uint64_t rint_25:1;
1523                 uint64_t rint_24:1;
1524                 uint64_t asx1:1;
1525                 uint64_t asx0:1;
1526                 uint64_t rint_21:1;
1527                 uint64_t pip:1;
1528                 uint64_t spx1:1;
1529                 uint64_t spx0:1;
1530                 uint64_t lmc:1;
1531                 uint64_t l2c:1;
1532                 uint64_t rint_15:1;
1533                 uint64_t rint_14:1;
1534                 uint64_t rint_13:1;
1535                 uint64_t pow:1;
1536                 uint64_t tim:1;
1537                 uint64_t pko:1;
1538                 uint64_t ipd:1;
1539                 uint64_t rint_8:1;
1540                 uint64_t zip:1;
1541                 uint64_t dfa:1;
1542                 uint64_t fpa:1;
1543                 uint64_t key:1;
1544                 uint64_t npi:1;
1545                 uint64_t gmx1:1;
1546                 uint64_t gmx0:1;
1547                 uint64_t mio:1;
1548         } cn38xx;
1549         struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
1550         struct cvmx_npi_rsl_int_blocks_cn50xx {
1551                 uint64_t reserved_31_63:33;
1552                 uint64_t iob:1;
1553                 uint64_t lmc1:1;
1554                 uint64_t agl:1;
1555                 uint64_t reserved_24_27:4;
1556                 uint64_t asx1:1;
1557                 uint64_t asx0:1;
1558                 uint64_t reserved_21_21:1;
1559                 uint64_t pip:1;
1560                 uint64_t spx1:1;
1561                 uint64_t spx0:1;
1562                 uint64_t lmc:1;
1563                 uint64_t l2c:1;
1564                 uint64_t reserved_15_15:1;
1565                 uint64_t rad:1;
1566                 uint64_t usb:1;
1567                 uint64_t pow:1;
1568                 uint64_t tim:1;
1569                 uint64_t pko:1;
1570                 uint64_t ipd:1;
1571                 uint64_t reserved_8_8:1;
1572                 uint64_t zip:1;
1573                 uint64_t dfa:1;
1574                 uint64_t fpa:1;
1575                 uint64_t key:1;
1576                 uint64_t npi:1;
1577                 uint64_t gmx1:1;
1578                 uint64_t gmx0:1;
1579                 uint64_t mio:1;
1580         } cn50xx;
1581         struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
1582         struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
1583 };
1584
1585 union cvmx_npi_size_inputx {
1586         uint64_t u64;
1587         struct cvmx_npi_size_inputx_s {
1588                 uint64_t reserved_32_63:32;
1589                 uint64_t size:32;
1590         } s;
1591         struct cvmx_npi_size_inputx_s cn30xx;
1592         struct cvmx_npi_size_inputx_s cn31xx;
1593         struct cvmx_npi_size_inputx_s cn38xx;
1594         struct cvmx_npi_size_inputx_s cn38xxp2;
1595         struct cvmx_npi_size_inputx_s cn50xx;
1596         struct cvmx_npi_size_inputx_s cn58xx;
1597         struct cvmx_npi_size_inputx_s cn58xxp1;
1598 };
1599
1600 union cvmx_npi_win_read_to {
1601         uint64_t u64;
1602         struct cvmx_npi_win_read_to_s {
1603                 uint64_t reserved_32_63:32;
1604                 uint64_t time:32;
1605         } s;
1606         struct cvmx_npi_win_read_to_s cn30xx;
1607         struct cvmx_npi_win_read_to_s cn31xx;
1608         struct cvmx_npi_win_read_to_s cn38xx;
1609         struct cvmx_npi_win_read_to_s cn38xxp2;
1610         struct cvmx_npi_win_read_to_s cn50xx;
1611         struct cvmx_npi_win_read_to_s cn58xx;
1612         struct cvmx_npi_win_read_to_s cn58xxp1;
1613 };
1614
1615 #endif