arch/mips/include/asm/mach-powertv/cpu-feature-overrides.h

   1 /*
   2  * Copyright (C) 2010  Cisco Systems, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #ifndef _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
  20 #define _ASM_MACH_POWERTV_CPU_FEATURE_OVERRIDES_H_
  21 #define cpu_has_tlb                     1
  22 #define cpu_has_4kex                    1
  23 #define cpu_has_3k_cache                0
  24 #define cpu_has_4k_cache                1
  25 #define cpu_has_tx39_cache              0
  26 #define cpu_has_fpu                     0
  27 #define cpu_has_counter                 1
  28 #define cpu_has_watch                   1
  29 #define cpu_has_divec                   1
  30 #define cpu_has_vce                     0
  31 #define cpu_has_cache_cdex_p            0
  32 #define cpu_has_cache_cdex_s            0
  33 #define cpu_has_mcheck                  1
  34 #define cpu_has_ejtag                   1
  35 #define cpu_has_llsc                    1
  36 #define cpu_has_mips16                  0
  37 #define cpu_has_mdmx                    0
  38 #define cpu_has_mips3d                  0
  39 #define cpu_has_smartmips               0
  40 #define cpu_has_vtag_icache             0
  41 #define cpu_has_dc_aliases              0
  42 #define cpu_has_ic_fills_f_dc           0
  43 #define cpu_has_mips32r1                0
  44 #define cpu_has_mips32r2                1
  45 #define cpu_has_mips64r1                0
  46 #define cpu_has_mips64r2                0
  47 #define cpu_has_dsp                     0
  48 #define cpu_has_mipsmt                  0
  49 #define cpu_has_userlocal               0
  50 #define cpu_has_nofpuex                 0
  51 #define cpu_has_64bits                  0
  52 #define cpu_has_64bit_zero_reg          0
  53 #define cpu_has_vint                    1
  54 #define cpu_has_veic                    1
  55 #define cpu_has_inclusive_pcaches       0
  56
  57 #define cpu_dcache_line_size()          32
  58 #define cpu_icache_line_size()          32
  59 #endif